1 /* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _I915_DRM_H_ 28 #define _I915_DRM_H_ 29 30 #include "drm.h" 31 32 /* Please note that modifications to all structs defined here are 33 * subject to backwards-compatibility constraints. 34 */ 35 36 /* Each region is a minimum of 16k, and there are at most 255 of them. 37 */ 38 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 39 * of chars for next/prev indices */ 40 #define I915_LOG_MIN_TEX_REGION_SIZE 14 41 42 typedef struct _drm_i915_init { 43 enum { 44 I915_INIT_DMA = 0x01, 45 I915_CLEANUP_DMA = 0x02, 46 I915_RESUME_DMA = 0x03 47 } func; 48 unsigned int mmio_offset; 49 int sarea_priv_offset; 50 unsigned int ring_start; 51 unsigned int ring_end; 52 unsigned int ring_size; 53 unsigned int front_offset; 54 unsigned int back_offset; 55 unsigned int depth_offset; 56 unsigned int w; 57 unsigned int h; 58 unsigned int pitch; 59 unsigned int pitch_bits; 60 unsigned int back_pitch; 61 unsigned int depth_pitch; 62 unsigned int cpp; 63 unsigned int chipset; 64 } drm_i915_init_t; 65 66 typedef struct _drm_i915_sarea { 67 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 68 int last_upload; /* last time texture was uploaded */ 69 int last_enqueue; /* last time a buffer was enqueued */ 70 int last_dispatch; /* age of the most recently dispatched buffer */ 71 int ctxOwner; /* last context to upload state */ 72 int texAge; 73 int pf_enabled; /* is pageflipping allowed? */ 74 int pf_active; 75 int pf_current_page; /* which buffer is being displayed? */ 76 int perf_boxes; /* performance boxes to be displayed */ 77 int width, height; /* screen size in pixels */ 78 79 drm_handle_t front_handle; 80 int front_offset; 81 int front_size; 82 83 drm_handle_t back_handle; 84 int back_offset; 85 int back_size; 86 87 drm_handle_t depth_handle; 88 int depth_offset; 89 int depth_size; 90 91 drm_handle_t tex_handle; 92 int tex_offset; 93 int tex_size; 94 int log_tex_granularity; 95 int pitch; 96 int rotation; /* 0, 90, 180 or 270 */ 97 int rotated_offset; 98 int rotated_size; 99 int rotated_pitch; 100 int virtualX, virtualY; 101 102 unsigned int front_tiled; 103 unsigned int back_tiled; 104 unsigned int depth_tiled; 105 unsigned int rotated_tiled; 106 unsigned int rotated2_tiled; 107 108 int pipeA_x; 109 int pipeA_y; 110 int pipeA_w; 111 int pipeA_h; 112 int pipeB_x; 113 int pipeB_y; 114 int pipeB_w; 115 int pipeB_h; 116 117 /* fill out some space for old userspace triple buffer */ 118 drm_handle_t unused_handle; 119 __u32 unused1, unused2, unused3; 120 121 /* buffer object handles for static buffers. May change 122 * over the lifetime of the client. 123 */ 124 __u32 front_bo_handle; 125 __u32 back_bo_handle; 126 __u32 unused_bo_handle; 127 __u32 depth_bo_handle; 128 129 } drm_i915_sarea_t; 130 131 /* due to userspace building against these headers we need some compat here */ 132 #define planeA_x pipeA_x 133 #define planeA_y pipeA_y 134 #define planeA_w pipeA_w 135 #define planeA_h pipeA_h 136 #define planeB_x pipeB_x 137 #define planeB_y pipeB_y 138 #define planeB_w pipeB_w 139 #define planeB_h pipeB_h 140 141 /* Flags for perf_boxes 142 */ 143 #define I915_BOX_RING_EMPTY 0x1 144 #define I915_BOX_FLIP 0x2 145 #define I915_BOX_WAIT 0x4 146 #define I915_BOX_TEXTURE_LOAD 0x8 147 #define I915_BOX_LOST_CONTEXT 0x10 148 149 /* I915 specific ioctls 150 * The device specific ioctl range is 0x40 to 0x79. 151 */ 152 #define DRM_I915_INIT 0x00 153 #define DRM_I915_FLUSH 0x01 154 #define DRM_I915_FLIP 0x02 155 #define DRM_I915_BATCHBUFFER 0x03 156 #define DRM_I915_IRQ_EMIT 0x04 157 #define DRM_I915_IRQ_WAIT 0x05 158 #define DRM_I915_GETPARAM 0x06 159 #define DRM_I915_SETPARAM 0x07 160 #define DRM_I915_ALLOC 0x08 161 #define DRM_I915_FREE 0x09 162 #define DRM_I915_INIT_HEAP 0x0a 163 #define DRM_I915_CMDBUFFER 0x0b 164 #define DRM_I915_DESTROY_HEAP 0x0c 165 #define DRM_I915_SET_VBLANK_PIPE 0x0d 166 #define DRM_I915_GET_VBLANK_PIPE 0x0e 167 #define DRM_I915_VBLANK_SWAP 0x0f 168 #define DRM_I915_HWS_ADDR 0x11 169 #define DRM_I915_GEM_INIT 0x13 170 #define DRM_I915_GEM_EXECBUFFER 0x14 171 #define DRM_I915_GEM_PIN 0x15 172 #define DRM_I915_GEM_UNPIN 0x16 173 #define DRM_I915_GEM_BUSY 0x17 174 #define DRM_I915_GEM_THROTTLE 0x18 175 #define DRM_I915_GEM_ENTERVT 0x19 176 #define DRM_I915_GEM_LEAVEVT 0x1a 177 #define DRM_I915_GEM_CREATE 0x1b 178 #define DRM_I915_GEM_PREAD 0x1c 179 #define DRM_I915_GEM_PWRITE 0x1d 180 #define DRM_I915_GEM_MMAP 0x1e 181 #define DRM_I915_GEM_SET_DOMAIN 0x1f 182 #define DRM_I915_GEM_SW_FINISH 0x20 183 #define DRM_I915_GEM_SET_TILING 0x21 184 #define DRM_I915_GEM_GET_TILING 0x22 185 #define DRM_I915_GEM_GET_APERTURE 0x23 186 #define DRM_I915_GEM_MMAP_GTT 0x24 187 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 188 #define DRM_I915_GEM_MADVISE 0x26 189 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 190 #define DRM_I915_OVERLAY_ATTRS 0x28 191 #define DRM_I915_GEM_EXECBUFFER2 0x29 192 193 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 194 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 195 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 196 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 197 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 198 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 199 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 200 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 201 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 202 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 203 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 204 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 205 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 206 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 207 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 208 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 209 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 210 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 211 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 212 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 213 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 214 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 215 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 216 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 217 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 218 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 219 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 220 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 221 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 222 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 223 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 224 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 225 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 226 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 227 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 228 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 229 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 230 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 231 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_ATTRS, struct drm_intel_overlay_put_image) 232 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 233 234 /* Allow drivers to submit batchbuffers directly to hardware, relying 235 * on the security mechanisms provided by hardware. 236 */ 237 typedef struct drm_i915_batchbuffer { 238 int start; /* agp offset */ 239 int used; /* nr bytes in use */ 240 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 241 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 242 int num_cliprects; /* mulitpass with multiple cliprects? */ 243 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 244 } drm_i915_batchbuffer_t; 245 246 /* As above, but pass a pointer to userspace buffer which can be 247 * validated by the kernel prior to sending to hardware. 248 */ 249 typedef struct _drm_i915_cmdbuffer { 250 char __user *buf; /* pointer to userspace command buffer */ 251 int sz; /* nr bytes in buf */ 252 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 253 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 254 int num_cliprects; /* mulitpass with multiple cliprects? */ 255 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 256 } drm_i915_cmdbuffer_t; 257 258 /* Userspace can request & wait on irq's: 259 */ 260 typedef struct drm_i915_irq_emit { 261 int __user *irq_seq; 262 } drm_i915_irq_emit_t; 263 264 typedef struct drm_i915_irq_wait { 265 int irq_seq; 266 } drm_i915_irq_wait_t; 267 268 /* Ioctl to query kernel params: 269 */ 270 #define I915_PARAM_IRQ_ACTIVE 1 271 #define I915_PARAM_ALLOW_BATCHBUFFER 2 272 #define I915_PARAM_LAST_DISPATCH 3 273 #define I915_PARAM_CHIPSET_ID 4 274 #define I915_PARAM_HAS_GEM 5 275 #define I915_PARAM_NUM_FENCES_AVAIL 6 276 #define I915_PARAM_HAS_OVERLAY 7 277 #define I915_PARAM_HAS_PAGEFLIPPING 8 278 #define I915_PARAM_HAS_EXECBUF2 9 279 #define I915_PARAM_HAS_BSD 10 280 281 typedef struct drm_i915_getparam { 282 int param; 283 int __user *value; 284 } drm_i915_getparam_t; 285 286 /* Ioctl to set kernel params: 287 */ 288 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 289 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 290 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 291 #define I915_SETPARAM_NUM_USED_FENCES 4 292 293 typedef struct drm_i915_setparam { 294 int param; 295 int value; 296 } drm_i915_setparam_t; 297 298 /* A memory manager for regions of shared memory: 299 */ 300 #define I915_MEM_REGION_AGP 1 301 302 typedef struct drm_i915_mem_alloc { 303 int region; 304 int alignment; 305 int size; 306 int __user *region_offset; /* offset from start of fb or agp */ 307 } drm_i915_mem_alloc_t; 308 309 typedef struct drm_i915_mem_free { 310 int region; 311 int region_offset; 312 } drm_i915_mem_free_t; 313 314 typedef struct drm_i915_mem_init_heap { 315 int region; 316 int size; 317 int start; 318 } drm_i915_mem_init_heap_t; 319 320 /* Allow memory manager to be torn down and re-initialized (eg on 321 * rotate): 322 */ 323 typedef struct drm_i915_mem_destroy_heap { 324 int region; 325 } drm_i915_mem_destroy_heap_t; 326 327 /* Allow X server to configure which pipes to monitor for vblank signals 328 */ 329 #define DRM_I915_VBLANK_PIPE_A 1 330 #define DRM_I915_VBLANK_PIPE_B 2 331 332 typedef struct drm_i915_vblank_pipe { 333 int pipe; 334 } drm_i915_vblank_pipe_t; 335 336 /* Schedule buffer swap at given vertical blank: 337 */ 338 typedef struct drm_i915_vblank_swap { 339 drm_drawable_t drawable; 340 enum drm_vblank_seq_type seqtype; 341 unsigned int sequence; 342 } drm_i915_vblank_swap_t; 343 344 typedef struct drm_i915_hws_addr { 345 __u64 addr; 346 } drm_i915_hws_addr_t; 347 348 struct drm_i915_gem_init { 349 /** 350 * Beginning offset in the GTT to be managed by the DRM memory 351 * manager. 352 */ 353 __u64 gtt_start; 354 /** 355 * Ending offset in the GTT to be managed by the DRM memory 356 * manager. 357 */ 358 __u64 gtt_end; 359 }; 360 361 struct drm_i915_gem_create { 362 /** 363 * Requested size for the object. 364 * 365 * The (page-aligned) allocated size for the object will be returned. 366 */ 367 __u64 size; 368 /** 369 * Returned handle for the object. 370 * 371 * Object handles are nonzero. 372 */ 373 __u32 handle; 374 __u32 pad; 375 }; 376 377 struct drm_i915_gem_pread { 378 /** Handle for the object being read. */ 379 __u32 handle; 380 __u32 pad; 381 /** Offset into the object to read from */ 382 __u64 offset; 383 /** Length of data to read */ 384 __u64 size; 385 /** 386 * Pointer to write the data into. 387 * 388 * This is a fixed-size type for 32/64 compatibility. 389 */ 390 __u64 data_ptr; 391 }; 392 393 struct drm_i915_gem_pwrite { 394 /** Handle for the object being written to. */ 395 __u32 handle; 396 __u32 pad; 397 /** Offset into the object to write to */ 398 __u64 offset; 399 /** Length of data to write */ 400 __u64 size; 401 /** 402 * Pointer to read the data from. 403 * 404 * This is a fixed-size type for 32/64 compatibility. 405 */ 406 __u64 data_ptr; 407 }; 408 409 struct drm_i915_gem_mmap { 410 /** Handle for the object being mapped. */ 411 __u32 handle; 412 __u32 pad; 413 /** Offset in the object to map. */ 414 __u64 offset; 415 /** 416 * Length of data to map. 417 * 418 * The value will be page-aligned. 419 */ 420 __u64 size; 421 /** 422 * Returned pointer the data was mapped at. 423 * 424 * This is a fixed-size type for 32/64 compatibility. 425 */ 426 __u64 addr_ptr; 427 }; 428 429 struct drm_i915_gem_mmap_gtt { 430 /** Handle for the object being mapped. */ 431 __u32 handle; 432 __u32 pad; 433 /** 434 * Fake offset to use for subsequent mmap call 435 * 436 * This is a fixed-size type for 32/64 compatibility. 437 */ 438 __u64 offset; 439 }; 440 441 struct drm_i915_gem_set_domain { 442 /** Handle for the object */ 443 __u32 handle; 444 445 /** New read domains */ 446 __u32 read_domains; 447 448 /** New write domain */ 449 __u32 write_domain; 450 }; 451 452 struct drm_i915_gem_sw_finish { 453 /** Handle for the object */ 454 __u32 handle; 455 }; 456 457 struct drm_i915_gem_relocation_entry { 458 /** 459 * Handle of the buffer being pointed to by this relocation entry. 460 * 461 * It's appealing to make this be an index into the mm_validate_entry 462 * list to refer to the buffer, but this allows the driver to create 463 * a relocation list for state buffers and not re-write it per 464 * exec using the buffer. 465 */ 466 __u32 target_handle; 467 468 /** 469 * Value to be added to the offset of the target buffer to make up 470 * the relocation entry. 471 */ 472 __u32 delta; 473 474 /** Offset in the buffer the relocation entry will be written into */ 475 __u64 offset; 476 477 /** 478 * Offset value of the target buffer that the relocation entry was last 479 * written as. 480 * 481 * If the buffer has the same offset as last time, we can skip syncing 482 * and writing the relocation. This value is written back out by 483 * the execbuffer ioctl when the relocation is written. 484 */ 485 __u64 presumed_offset; 486 487 /** 488 * Target memory domains read by this operation. 489 */ 490 __u32 read_domains; 491 492 /** 493 * Target memory domains written by this operation. 494 * 495 * Note that only one domain may be written by the whole 496 * execbuffer operation, so that where there are conflicts, 497 * the application will get -EINVAL back. 498 */ 499 __u32 write_domain; 500 }; 501 502 /** @{ 503 * Intel memory domains 504 * 505 * Most of these just align with the various caches in 506 * the system and are used to flush and invalidate as 507 * objects end up cached in different domains. 508 */ 509 /** CPU cache */ 510 #define I915_GEM_DOMAIN_CPU 0x00000001 511 /** Render cache, used by 2D and 3D drawing */ 512 #define I915_GEM_DOMAIN_RENDER 0x00000002 513 /** Sampler cache, used by texture engine */ 514 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 515 /** Command queue, used to load batch buffers */ 516 #define I915_GEM_DOMAIN_COMMAND 0x00000008 517 /** Instruction cache, used by shader programs */ 518 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 519 /** Vertex address cache */ 520 #define I915_GEM_DOMAIN_VERTEX 0x00000020 521 /** GTT domain - aperture and scanout */ 522 #define I915_GEM_DOMAIN_GTT 0x00000040 523 /** @} */ 524 525 struct drm_i915_gem_exec_object { 526 /** 527 * User's handle for a buffer to be bound into the GTT for this 528 * operation. 529 */ 530 __u32 handle; 531 532 /** Number of relocations to be performed on this buffer */ 533 __u32 relocation_count; 534 /** 535 * Pointer to array of struct drm_i915_gem_relocation_entry containing 536 * the relocations to be performed in this buffer. 537 */ 538 __u64 relocs_ptr; 539 540 /** Required alignment in graphics aperture */ 541 __u64 alignment; 542 543 /** 544 * Returned value of the updated offset of the object, for future 545 * presumed_offset writes. 546 */ 547 __u64 offset; 548 }; 549 550 struct drm_i915_gem_execbuffer { 551 /** 552 * List of buffers to be validated with their relocations to be 553 * performend on them. 554 * 555 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 556 * 557 * These buffers must be listed in an order such that all relocations 558 * a buffer is performing refer to buffers that have already appeared 559 * in the validate list. 560 */ 561 __u64 buffers_ptr; 562 __u32 buffer_count; 563 564 /** Offset in the batchbuffer to start execution from. */ 565 __u32 batch_start_offset; 566 /** Bytes used in batchbuffer from batch_start_offset */ 567 __u32 batch_len; 568 __u32 DR1; 569 __u32 DR4; 570 __u32 num_cliprects; 571 /** This is a struct drm_clip_rect *cliprects */ 572 __u64 cliprects_ptr; 573 }; 574 575 struct drm_i915_gem_exec_object2 { 576 /** 577 * User's handle for a buffer to be bound into the GTT for this 578 * operation. 579 */ 580 __u32 handle; 581 582 /** Number of relocations to be performed on this buffer */ 583 __u32 relocation_count; 584 /** 585 * Pointer to array of struct drm_i915_gem_relocation_entry containing 586 * the relocations to be performed in this buffer. 587 */ 588 __u64 relocs_ptr; 589 590 /** Required alignment in graphics aperture */ 591 __u64 alignment; 592 593 /** 594 * Returned value of the updated offset of the object, for future 595 * presumed_offset writes. 596 */ 597 __u64 offset; 598 599 #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 600 __u64 flags; 601 __u64 rsvd1; 602 __u64 rsvd2; 603 }; 604 605 struct drm_i915_gem_execbuffer2 { 606 /** 607 * List of gem_exec_object2 structs 608 */ 609 __u64 buffers_ptr; 610 __u32 buffer_count; 611 612 /** Offset in the batchbuffer to start execution from. */ 613 __u32 batch_start_offset; 614 /** Bytes used in batchbuffer from batch_start_offset */ 615 __u32 batch_len; 616 __u32 DR1; 617 __u32 DR4; 618 __u32 num_cliprects; 619 /** This is a struct drm_clip_rect *cliprects */ 620 __u64 cliprects_ptr; 621 #define I915_EXEC_RENDER (1<<0) 622 #define I915_EXEC_BSD (1<<1) 623 __u64 flags; 624 __u64 rsvd1; 625 __u64 rsvd2; 626 }; 627 628 struct drm_i915_gem_pin { 629 /** Handle of the buffer to be pinned. */ 630 __u32 handle; 631 __u32 pad; 632 633 /** alignment required within the aperture */ 634 __u64 alignment; 635 636 /** Returned GTT offset of the buffer. */ 637 __u64 offset; 638 }; 639 640 struct drm_i915_gem_unpin { 641 /** Handle of the buffer to be unpinned. */ 642 __u32 handle; 643 __u32 pad; 644 }; 645 646 struct drm_i915_gem_busy { 647 /** Handle of the buffer to check for busy */ 648 __u32 handle; 649 650 /** Return busy status (1 if busy, 0 if idle) */ 651 __u32 busy; 652 }; 653 654 #define I915_TILING_NONE 0 655 #define I915_TILING_X 1 656 #define I915_TILING_Y 2 657 658 #define I915_BIT_6_SWIZZLE_NONE 0 659 #define I915_BIT_6_SWIZZLE_9 1 660 #define I915_BIT_6_SWIZZLE_9_10 2 661 #define I915_BIT_6_SWIZZLE_9_11 3 662 #define I915_BIT_6_SWIZZLE_9_10_11 4 663 /* Not seen by userland */ 664 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 665 /* Seen by userland. */ 666 #define I915_BIT_6_SWIZZLE_9_17 6 667 #define I915_BIT_6_SWIZZLE_9_10_17 7 668 669 struct drm_i915_gem_set_tiling { 670 /** Handle of the buffer to have its tiling state updated */ 671 __u32 handle; 672 673 /** 674 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 675 * I915_TILING_Y). 676 * 677 * This value is to be set on request, and will be updated by the 678 * kernel on successful return with the actual chosen tiling layout. 679 * 680 * The tiling mode may be demoted to I915_TILING_NONE when the system 681 * has bit 6 swizzling that can't be managed correctly by GEM. 682 * 683 * Buffer contents become undefined when changing tiling_mode. 684 */ 685 __u32 tiling_mode; 686 687 /** 688 * Stride in bytes for the object when in I915_TILING_X or 689 * I915_TILING_Y. 690 */ 691 __u32 stride; 692 693 /** 694 * Returned address bit 6 swizzling required for CPU access through 695 * mmap mapping. 696 */ 697 __u32 swizzle_mode; 698 }; 699 700 struct drm_i915_gem_get_tiling { 701 /** Handle of the buffer to get tiling state for. */ 702 __u32 handle; 703 704 /** 705 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 706 * I915_TILING_Y). 707 */ 708 __u32 tiling_mode; 709 710 /** 711 * Returned address bit 6 swizzling required for CPU access through 712 * mmap mapping. 713 */ 714 __u32 swizzle_mode; 715 }; 716 717 struct drm_i915_gem_get_aperture { 718 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 719 __u64 aper_size; 720 721 /** 722 * Available space in the aperture used by i915_gem_execbuffer, in 723 * bytes 724 */ 725 __u64 aper_available_size; 726 }; 727 728 struct drm_i915_get_pipe_from_crtc_id { 729 /** ID of CRTC being requested **/ 730 __u32 crtc_id; 731 732 /** pipe of requested CRTC **/ 733 __u32 pipe; 734 }; 735 736 #define I915_MADV_WILLNEED 0 737 #define I915_MADV_DONTNEED 1 738 #define __I915_MADV_PURGED 2 /* internal state */ 739 740 struct drm_i915_gem_madvise { 741 /** Handle of the buffer to change the backing store advice */ 742 __u32 handle; 743 744 /* Advice: either the buffer will be needed again in the near future, 745 * or wont be and could be discarded under memory pressure. 746 */ 747 __u32 madv; 748 749 /** Whether the backing store still exists. */ 750 __u32 retained; 751 }; 752 753 /* flags */ 754 #define I915_OVERLAY_TYPE_MASK 0xff 755 #define I915_OVERLAY_YUV_PLANAR 0x01 756 #define I915_OVERLAY_YUV_PACKED 0x02 757 #define I915_OVERLAY_RGB 0x03 758 759 #define I915_OVERLAY_DEPTH_MASK 0xff00 760 #define I915_OVERLAY_RGB24 0x1000 761 #define I915_OVERLAY_RGB16 0x2000 762 #define I915_OVERLAY_RGB15 0x3000 763 #define I915_OVERLAY_YUV422 0x0100 764 #define I915_OVERLAY_YUV411 0x0200 765 #define I915_OVERLAY_YUV420 0x0300 766 #define I915_OVERLAY_YUV410 0x0400 767 768 #define I915_OVERLAY_SWAP_MASK 0xff0000 769 #define I915_OVERLAY_NO_SWAP 0x000000 770 #define I915_OVERLAY_UV_SWAP 0x010000 771 #define I915_OVERLAY_Y_SWAP 0x020000 772 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 773 774 #define I915_OVERLAY_FLAGS_MASK 0xff000000 775 #define I915_OVERLAY_ENABLE 0x01000000 776 777 struct drm_intel_overlay_put_image { 778 /* various flags and src format description */ 779 __u32 flags; 780 /* source picture description */ 781 __u32 bo_handle; 782 /* stride values and offsets are in bytes, buffer relative */ 783 __u16 stride_Y; /* stride for packed formats */ 784 __u16 stride_UV; 785 __u32 offset_Y; /* offset for packet formats */ 786 __u32 offset_U; 787 __u32 offset_V; 788 /* in pixels */ 789 __u16 src_width; 790 __u16 src_height; 791 /* to compensate the scaling factors for partially covered surfaces */ 792 __u16 src_scan_width; 793 __u16 src_scan_height; 794 /* output crtc description */ 795 __u32 crtc_id; 796 __u16 dst_x; 797 __u16 dst_y; 798 __u16 dst_width; 799 __u16 dst_height; 800 }; 801 802 /* flags */ 803 #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 804 #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 805 struct drm_intel_overlay_attrs { 806 __u32 flags; 807 __u32 color_key; 808 __s32 brightness; 809 __u32 contrast; 810 __u32 saturation; 811 __u32 gamma0; 812 __u32 gamma1; 813 __u32 gamma2; 814 __u32 gamma3; 815 __u32 gamma4; 816 __u32 gamma5; 817 }; 818 819 #endif /* _I915_DRM_H_ */ 820