1 /* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _I915_DRM_H_ 28 #define _I915_DRM_H_ 29 30 #include "drm.h" 31 32 /* Please note that modifications to all structs defined here are 33 * subject to backwards-compatibility constraints. 34 */ 35 36 #ifdef __KERNEL__ 37 /* For use by IPS driver */ 38 extern unsigned long i915_read_mch_val(void); 39 extern bool i915_gpu_raise(void); 40 extern bool i915_gpu_lower(void); 41 extern bool i915_gpu_busy(void); 42 extern bool i915_gpu_turbo_disable(void); 43 #endif 44 45 /* Each region is a minimum of 16k, and there are at most 255 of them. 46 */ 47 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 48 * of chars for next/prev indices */ 49 #define I915_LOG_MIN_TEX_REGION_SIZE 14 50 51 typedef struct _drm_i915_init { 52 enum { 53 I915_INIT_DMA = 0x01, 54 I915_CLEANUP_DMA = 0x02, 55 I915_RESUME_DMA = 0x03 56 } func; 57 unsigned int mmio_offset; 58 int sarea_priv_offset; 59 unsigned int ring_start; 60 unsigned int ring_end; 61 unsigned int ring_size; 62 unsigned int front_offset; 63 unsigned int back_offset; 64 unsigned int depth_offset; 65 unsigned int w; 66 unsigned int h; 67 unsigned int pitch; 68 unsigned int pitch_bits; 69 unsigned int back_pitch; 70 unsigned int depth_pitch; 71 unsigned int cpp; 72 unsigned int chipset; 73 } drm_i915_init_t; 74 75 typedef struct _drm_i915_sarea { 76 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 77 int last_upload; /* last time texture was uploaded */ 78 int last_enqueue; /* last time a buffer was enqueued */ 79 int last_dispatch; /* age of the most recently dispatched buffer */ 80 int ctxOwner; /* last context to upload state */ 81 int texAge; 82 int pf_enabled; /* is pageflipping allowed? */ 83 int pf_active; 84 int pf_current_page; /* which buffer is being displayed? */ 85 int perf_boxes; /* performance boxes to be displayed */ 86 int width, height; /* screen size in pixels */ 87 88 drm_handle_t front_handle; 89 int front_offset; 90 int front_size; 91 92 drm_handle_t back_handle; 93 int back_offset; 94 int back_size; 95 96 drm_handle_t depth_handle; 97 int depth_offset; 98 int depth_size; 99 100 drm_handle_t tex_handle; 101 int tex_offset; 102 int tex_size; 103 int log_tex_granularity; 104 int pitch; 105 int rotation; /* 0, 90, 180 or 270 */ 106 int rotated_offset; 107 int rotated_size; 108 int rotated_pitch; 109 int virtualX, virtualY; 110 111 unsigned int front_tiled; 112 unsigned int back_tiled; 113 unsigned int depth_tiled; 114 unsigned int rotated_tiled; 115 unsigned int rotated2_tiled; 116 117 int pipeA_x; 118 int pipeA_y; 119 int pipeA_w; 120 int pipeA_h; 121 int pipeB_x; 122 int pipeB_y; 123 int pipeB_w; 124 int pipeB_h; 125 126 /* fill out some space for old userspace triple buffer */ 127 drm_handle_t unused_handle; 128 __u32 unused1, unused2, unused3; 129 130 /* buffer object handles for static buffers. May change 131 * over the lifetime of the client. 132 */ 133 __u32 front_bo_handle; 134 __u32 back_bo_handle; 135 __u32 unused_bo_handle; 136 __u32 depth_bo_handle; 137 138 } drm_i915_sarea_t; 139 140 /* due to userspace building against these headers we need some compat here */ 141 #define planeA_x pipeA_x 142 #define planeA_y pipeA_y 143 #define planeA_w pipeA_w 144 #define planeA_h pipeA_h 145 #define planeB_x pipeB_x 146 #define planeB_y pipeB_y 147 #define planeB_w pipeB_w 148 #define planeB_h pipeB_h 149 150 /* Flags for perf_boxes 151 */ 152 #define I915_BOX_RING_EMPTY 0x1 153 #define I915_BOX_FLIP 0x2 154 #define I915_BOX_WAIT 0x4 155 #define I915_BOX_TEXTURE_LOAD 0x8 156 #define I915_BOX_LOST_CONTEXT 0x10 157 158 /* I915 specific ioctls 159 * The device specific ioctl range is 0x40 to 0x79. 160 */ 161 #define DRM_I915_INIT 0x00 162 #define DRM_I915_FLUSH 0x01 163 #define DRM_I915_FLIP 0x02 164 #define DRM_I915_BATCHBUFFER 0x03 165 #define DRM_I915_IRQ_EMIT 0x04 166 #define DRM_I915_IRQ_WAIT 0x05 167 #define DRM_I915_GETPARAM 0x06 168 #define DRM_I915_SETPARAM 0x07 169 #define DRM_I915_ALLOC 0x08 170 #define DRM_I915_FREE 0x09 171 #define DRM_I915_INIT_HEAP 0x0a 172 #define DRM_I915_CMDBUFFER 0x0b 173 #define DRM_I915_DESTROY_HEAP 0x0c 174 #define DRM_I915_SET_VBLANK_PIPE 0x0d 175 #define DRM_I915_GET_VBLANK_PIPE 0x0e 176 #define DRM_I915_VBLANK_SWAP 0x0f 177 #define DRM_I915_HWS_ADDR 0x11 178 #define DRM_I915_GEM_INIT 0x13 179 #define DRM_I915_GEM_EXECBUFFER 0x14 180 #define DRM_I915_GEM_PIN 0x15 181 #define DRM_I915_GEM_UNPIN 0x16 182 #define DRM_I915_GEM_BUSY 0x17 183 #define DRM_I915_GEM_THROTTLE 0x18 184 #define DRM_I915_GEM_ENTERVT 0x19 185 #define DRM_I915_GEM_LEAVEVT 0x1a 186 #define DRM_I915_GEM_CREATE 0x1b 187 #define DRM_I915_GEM_PREAD 0x1c 188 #define DRM_I915_GEM_PWRITE 0x1d 189 #define DRM_I915_GEM_MMAP 0x1e 190 #define DRM_I915_GEM_SET_DOMAIN 0x1f 191 #define DRM_I915_GEM_SW_FINISH 0x20 192 #define DRM_I915_GEM_SET_TILING 0x21 193 #define DRM_I915_GEM_GET_TILING 0x22 194 #define DRM_I915_GEM_GET_APERTURE 0x23 195 #define DRM_I915_GEM_MMAP_GTT 0x24 196 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 197 #define DRM_I915_GEM_MADVISE 0x26 198 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 199 #define DRM_I915_OVERLAY_ATTRS 0x28 200 #define DRM_I915_GEM_EXECBUFFER2 0x29 201 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 202 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 203 #define DRM_I915_GEM_WAIT 0x2c 204 205 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 206 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 207 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 208 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 209 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 210 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 211 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 212 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 213 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 214 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 215 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 216 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 217 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 218 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 219 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 220 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 221 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 222 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 223 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 224 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 225 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 226 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 227 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 228 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 229 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 230 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 231 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 232 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 233 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 234 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 235 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 236 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 237 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 238 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 239 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 240 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 241 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 242 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 243 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 244 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 245 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 246 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 247 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 248 249 /* Allow drivers to submit batchbuffers directly to hardware, relying 250 * on the security mechanisms provided by hardware. 251 */ 252 typedef struct drm_i915_batchbuffer { 253 int start; /* agp offset */ 254 int used; /* nr bytes in use */ 255 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 256 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 257 int num_cliprects; /* mulitpass with multiple cliprects? */ 258 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 259 } drm_i915_batchbuffer_t; 260 261 /* As above, but pass a pointer to userspace buffer which can be 262 * validated by the kernel prior to sending to hardware. 263 */ 264 typedef struct _drm_i915_cmdbuffer { 265 char __user *buf; /* pointer to userspace command buffer */ 266 int sz; /* nr bytes in buf */ 267 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 268 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 269 int num_cliprects; /* mulitpass with multiple cliprects? */ 270 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 271 } drm_i915_cmdbuffer_t; 272 273 /* Userspace can request & wait on irq's: 274 */ 275 typedef struct drm_i915_irq_emit { 276 int __user *irq_seq; 277 } drm_i915_irq_emit_t; 278 279 typedef struct drm_i915_irq_wait { 280 int irq_seq; 281 } drm_i915_irq_wait_t; 282 283 /* Ioctl to query kernel params: 284 */ 285 #define I915_PARAM_IRQ_ACTIVE 1 286 #define I915_PARAM_ALLOW_BATCHBUFFER 2 287 #define I915_PARAM_LAST_DISPATCH 3 288 #define I915_PARAM_CHIPSET_ID 4 289 #define I915_PARAM_HAS_GEM 5 290 #define I915_PARAM_NUM_FENCES_AVAIL 6 291 #define I915_PARAM_HAS_OVERLAY 7 292 #define I915_PARAM_HAS_PAGEFLIPPING 8 293 #define I915_PARAM_HAS_EXECBUF2 9 294 #define I915_PARAM_HAS_BSD 10 295 #define I915_PARAM_HAS_BLT 11 296 #define I915_PARAM_HAS_RELAXED_FENCING 12 297 #define I915_PARAM_HAS_COHERENT_RINGS 13 298 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 299 #define I915_PARAM_HAS_RELAXED_DELTA 15 300 #define I915_PARAM_HAS_GEN7_SOL_RESET 16 301 #define I915_PARAM_HAS_LLC 17 302 #define I915_PARAM_HAS_ALIASING_PPGTT 18 303 #define I915_PARAM_HAS_WAIT_TIMEOUT 19 304 305 typedef struct drm_i915_getparam { 306 int param; 307 int __user *value; 308 } drm_i915_getparam_t; 309 310 /* Ioctl to set kernel params: 311 */ 312 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 313 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 314 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 315 #define I915_SETPARAM_NUM_USED_FENCES 4 316 317 typedef struct drm_i915_setparam { 318 int param; 319 int value; 320 } drm_i915_setparam_t; 321 322 /* A memory manager for regions of shared memory: 323 */ 324 #define I915_MEM_REGION_AGP 1 325 326 typedef struct drm_i915_mem_alloc { 327 int region; 328 int alignment; 329 int size; 330 int __user *region_offset; /* offset from start of fb or agp */ 331 } drm_i915_mem_alloc_t; 332 333 typedef struct drm_i915_mem_free { 334 int region; 335 int region_offset; 336 } drm_i915_mem_free_t; 337 338 typedef struct drm_i915_mem_init_heap { 339 int region; 340 int size; 341 int start; 342 } drm_i915_mem_init_heap_t; 343 344 /* Allow memory manager to be torn down and re-initialized (eg on 345 * rotate): 346 */ 347 typedef struct drm_i915_mem_destroy_heap { 348 int region; 349 } drm_i915_mem_destroy_heap_t; 350 351 /* Allow X server to configure which pipes to monitor for vblank signals 352 */ 353 #define DRM_I915_VBLANK_PIPE_A 1 354 #define DRM_I915_VBLANK_PIPE_B 2 355 356 typedef struct drm_i915_vblank_pipe { 357 int pipe; 358 } drm_i915_vblank_pipe_t; 359 360 /* Schedule buffer swap at given vertical blank: 361 */ 362 typedef struct drm_i915_vblank_swap { 363 drm_drawable_t drawable; 364 enum drm_vblank_seq_type seqtype; 365 unsigned int sequence; 366 } drm_i915_vblank_swap_t; 367 368 typedef struct drm_i915_hws_addr { 369 __u64 addr; 370 } drm_i915_hws_addr_t; 371 372 struct drm_i915_gem_init { 373 /** 374 * Beginning offset in the GTT to be managed by the DRM memory 375 * manager. 376 */ 377 __u64 gtt_start; 378 /** 379 * Ending offset in the GTT to be managed by the DRM memory 380 * manager. 381 */ 382 __u64 gtt_end; 383 }; 384 385 struct drm_i915_gem_create { 386 /** 387 * Requested size for the object. 388 * 389 * The (page-aligned) allocated size for the object will be returned. 390 */ 391 __u64 size; 392 /** 393 * Returned handle for the object. 394 * 395 * Object handles are nonzero. 396 */ 397 __u32 handle; 398 __u32 pad; 399 }; 400 401 struct drm_i915_gem_pread { 402 /** Handle for the object being read. */ 403 __u32 handle; 404 __u32 pad; 405 /** Offset into the object to read from */ 406 __u64 offset; 407 /** Length of data to read */ 408 __u64 size; 409 /** 410 * Pointer to write the data into. 411 * 412 * This is a fixed-size type for 32/64 compatibility. 413 */ 414 __u64 data_ptr; 415 }; 416 417 struct drm_i915_gem_pwrite { 418 /** Handle for the object being written to. */ 419 __u32 handle; 420 __u32 pad; 421 /** Offset into the object to write to */ 422 __u64 offset; 423 /** Length of data to write */ 424 __u64 size; 425 /** 426 * Pointer to read the data from. 427 * 428 * This is a fixed-size type for 32/64 compatibility. 429 */ 430 __u64 data_ptr; 431 }; 432 433 struct drm_i915_gem_mmap { 434 /** Handle for the object being mapped. */ 435 __u32 handle; 436 __u32 pad; 437 /** Offset in the object to map. */ 438 __u64 offset; 439 /** 440 * Length of data to map. 441 * 442 * The value will be page-aligned. 443 */ 444 __u64 size; 445 /** 446 * Returned pointer the data was mapped at. 447 * 448 * This is a fixed-size type for 32/64 compatibility. 449 */ 450 __u64 addr_ptr; 451 }; 452 453 struct drm_i915_gem_mmap_gtt { 454 /** Handle for the object being mapped. */ 455 __u32 handle; 456 __u32 pad; 457 /** 458 * Fake offset to use for subsequent mmap call 459 * 460 * This is a fixed-size type for 32/64 compatibility. 461 */ 462 __u64 offset; 463 }; 464 465 struct drm_i915_gem_set_domain { 466 /** Handle for the object */ 467 __u32 handle; 468 469 /** New read domains */ 470 __u32 read_domains; 471 472 /** New write domain */ 473 __u32 write_domain; 474 }; 475 476 struct drm_i915_gem_sw_finish { 477 /** Handle for the object */ 478 __u32 handle; 479 }; 480 481 struct drm_i915_gem_relocation_entry { 482 /** 483 * Handle of the buffer being pointed to by this relocation entry. 484 * 485 * It's appealing to make this be an index into the mm_validate_entry 486 * list to refer to the buffer, but this allows the driver to create 487 * a relocation list for state buffers and not re-write it per 488 * exec using the buffer. 489 */ 490 __u32 target_handle; 491 492 /** 493 * Value to be added to the offset of the target buffer to make up 494 * the relocation entry. 495 */ 496 __u32 delta; 497 498 /** Offset in the buffer the relocation entry will be written into */ 499 __u64 offset; 500 501 /** 502 * Offset value of the target buffer that the relocation entry was last 503 * written as. 504 * 505 * If the buffer has the same offset as last time, we can skip syncing 506 * and writing the relocation. This value is written back out by 507 * the execbuffer ioctl when the relocation is written. 508 */ 509 __u64 presumed_offset; 510 511 /** 512 * Target memory domains read by this operation. 513 */ 514 __u32 read_domains; 515 516 /** 517 * Target memory domains written by this operation. 518 * 519 * Note that only one domain may be written by the whole 520 * execbuffer operation, so that where there are conflicts, 521 * the application will get -EINVAL back. 522 */ 523 __u32 write_domain; 524 }; 525 526 /** @{ 527 * Intel memory domains 528 * 529 * Most of these just align with the various caches in 530 * the system and are used to flush and invalidate as 531 * objects end up cached in different domains. 532 */ 533 /** CPU cache */ 534 #define I915_GEM_DOMAIN_CPU 0x00000001 535 /** Render cache, used by 2D and 3D drawing */ 536 #define I915_GEM_DOMAIN_RENDER 0x00000002 537 /** Sampler cache, used by texture engine */ 538 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 539 /** Command queue, used to load batch buffers */ 540 #define I915_GEM_DOMAIN_COMMAND 0x00000008 541 /** Instruction cache, used by shader programs */ 542 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 543 /** Vertex address cache */ 544 #define I915_GEM_DOMAIN_VERTEX 0x00000020 545 /** GTT domain - aperture and scanout */ 546 #define I915_GEM_DOMAIN_GTT 0x00000040 547 /** @} */ 548 549 struct drm_i915_gem_exec_object { 550 /** 551 * User's handle for a buffer to be bound into the GTT for this 552 * operation. 553 */ 554 __u32 handle; 555 556 /** Number of relocations to be performed on this buffer */ 557 __u32 relocation_count; 558 /** 559 * Pointer to array of struct drm_i915_gem_relocation_entry containing 560 * the relocations to be performed in this buffer. 561 */ 562 __u64 relocs_ptr; 563 564 /** Required alignment in graphics aperture */ 565 __u64 alignment; 566 567 /** 568 * Returned value of the updated offset of the object, for future 569 * presumed_offset writes. 570 */ 571 __u64 offset; 572 }; 573 574 struct drm_i915_gem_execbuffer { 575 /** 576 * List of buffers to be validated with their relocations to be 577 * performend on them. 578 * 579 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 580 * 581 * These buffers must be listed in an order such that all relocations 582 * a buffer is performing refer to buffers that have already appeared 583 * in the validate list. 584 */ 585 __u64 buffers_ptr; 586 __u32 buffer_count; 587 588 /** Offset in the batchbuffer to start execution from. */ 589 __u32 batch_start_offset; 590 /** Bytes used in batchbuffer from batch_start_offset */ 591 __u32 batch_len; 592 __u32 DR1; 593 __u32 DR4; 594 __u32 num_cliprects; 595 /** This is a struct drm_clip_rect *cliprects */ 596 __u64 cliprects_ptr; 597 }; 598 599 struct drm_i915_gem_exec_object2 { 600 /** 601 * User's handle for a buffer to be bound into the GTT for this 602 * operation. 603 */ 604 __u32 handle; 605 606 /** Number of relocations to be performed on this buffer */ 607 __u32 relocation_count; 608 /** 609 * Pointer to array of struct drm_i915_gem_relocation_entry containing 610 * the relocations to be performed in this buffer. 611 */ 612 __u64 relocs_ptr; 613 614 /** Required alignment in graphics aperture */ 615 __u64 alignment; 616 617 /** 618 * Returned value of the updated offset of the object, for future 619 * presumed_offset writes. 620 */ 621 __u64 offset; 622 623 #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 624 __u64 flags; 625 __u64 rsvd1; 626 __u64 rsvd2; 627 }; 628 629 struct drm_i915_gem_execbuffer2 { 630 /** 631 * List of gem_exec_object2 structs 632 */ 633 __u64 buffers_ptr; 634 __u32 buffer_count; 635 636 /** Offset in the batchbuffer to start execution from. */ 637 __u32 batch_start_offset; 638 /** Bytes used in batchbuffer from batch_start_offset */ 639 __u32 batch_len; 640 __u32 DR1; 641 __u32 DR4; 642 __u32 num_cliprects; 643 /** This is a struct drm_clip_rect *cliprects */ 644 __u64 cliprects_ptr; 645 #define I915_EXEC_RING_MASK (7<<0) 646 #define I915_EXEC_DEFAULT (0<<0) 647 #define I915_EXEC_RENDER (1<<0) 648 #define I915_EXEC_BSD (2<<0) 649 #define I915_EXEC_BLT (3<<0) 650 651 /* Used for switching the constants addressing mode on gen4+ RENDER ring. 652 * Gen6+ only supports relative addressing to dynamic state (default) and 653 * absolute addressing. 654 * 655 * These flags are ignored for the BSD and BLT rings. 656 */ 657 #define I915_EXEC_CONSTANTS_MASK (3<<6) 658 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 659 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 660 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 661 __u64 flags; 662 __u64 rsvd1; 663 __u64 rsvd2; 664 }; 665 666 /** Resets the SO write offset registers for transform feedback on gen7. */ 667 #define I915_EXEC_GEN7_SOL_RESET (1<<8) 668 669 struct drm_i915_gem_pin { 670 /** Handle of the buffer to be pinned. */ 671 __u32 handle; 672 __u32 pad; 673 674 /** alignment required within the aperture */ 675 __u64 alignment; 676 677 /** Returned GTT offset of the buffer. */ 678 __u64 offset; 679 }; 680 681 struct drm_i915_gem_unpin { 682 /** Handle of the buffer to be unpinned. */ 683 __u32 handle; 684 __u32 pad; 685 }; 686 687 struct drm_i915_gem_busy { 688 /** Handle of the buffer to check for busy */ 689 __u32 handle; 690 691 /** Return busy status (1 if busy, 0 if idle) */ 692 __u32 busy; 693 }; 694 695 #define I915_TILING_NONE 0 696 #define I915_TILING_X 1 697 #define I915_TILING_Y 2 698 699 #define I915_BIT_6_SWIZZLE_NONE 0 700 #define I915_BIT_6_SWIZZLE_9 1 701 #define I915_BIT_6_SWIZZLE_9_10 2 702 #define I915_BIT_6_SWIZZLE_9_11 3 703 #define I915_BIT_6_SWIZZLE_9_10_11 4 704 /* Not seen by userland */ 705 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 706 /* Seen by userland. */ 707 #define I915_BIT_6_SWIZZLE_9_17 6 708 #define I915_BIT_6_SWIZZLE_9_10_17 7 709 710 struct drm_i915_gem_set_tiling { 711 /** Handle of the buffer to have its tiling state updated */ 712 __u32 handle; 713 714 /** 715 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 716 * I915_TILING_Y). 717 * 718 * This value is to be set on request, and will be updated by the 719 * kernel on successful return with the actual chosen tiling layout. 720 * 721 * The tiling mode may be demoted to I915_TILING_NONE when the system 722 * has bit 6 swizzling that can't be managed correctly by GEM. 723 * 724 * Buffer contents become undefined when changing tiling_mode. 725 */ 726 __u32 tiling_mode; 727 728 /** 729 * Stride in bytes for the object when in I915_TILING_X or 730 * I915_TILING_Y. 731 */ 732 __u32 stride; 733 734 /** 735 * Returned address bit 6 swizzling required for CPU access through 736 * mmap mapping. 737 */ 738 __u32 swizzle_mode; 739 }; 740 741 struct drm_i915_gem_get_tiling { 742 /** Handle of the buffer to get tiling state for. */ 743 __u32 handle; 744 745 /** 746 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 747 * I915_TILING_Y). 748 */ 749 __u32 tiling_mode; 750 751 /** 752 * Returned address bit 6 swizzling required for CPU access through 753 * mmap mapping. 754 */ 755 __u32 swizzle_mode; 756 }; 757 758 struct drm_i915_gem_get_aperture { 759 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 760 __u64 aper_size; 761 762 /** 763 * Available space in the aperture used by i915_gem_execbuffer, in 764 * bytes 765 */ 766 __u64 aper_available_size; 767 }; 768 769 struct drm_i915_get_pipe_from_crtc_id { 770 /** ID of CRTC being requested **/ 771 __u32 crtc_id; 772 773 /** pipe of requested CRTC **/ 774 __u32 pipe; 775 }; 776 777 #define I915_MADV_WILLNEED 0 778 #define I915_MADV_DONTNEED 1 779 #define __I915_MADV_PURGED 2 /* internal state */ 780 781 struct drm_i915_gem_madvise { 782 /** Handle of the buffer to change the backing store advice */ 783 __u32 handle; 784 785 /* Advice: either the buffer will be needed again in the near future, 786 * or wont be and could be discarded under memory pressure. 787 */ 788 __u32 madv; 789 790 /** Whether the backing store still exists. */ 791 __u32 retained; 792 }; 793 794 /* flags */ 795 #define I915_OVERLAY_TYPE_MASK 0xff 796 #define I915_OVERLAY_YUV_PLANAR 0x01 797 #define I915_OVERLAY_YUV_PACKED 0x02 798 #define I915_OVERLAY_RGB 0x03 799 800 #define I915_OVERLAY_DEPTH_MASK 0xff00 801 #define I915_OVERLAY_RGB24 0x1000 802 #define I915_OVERLAY_RGB16 0x2000 803 #define I915_OVERLAY_RGB15 0x3000 804 #define I915_OVERLAY_YUV422 0x0100 805 #define I915_OVERLAY_YUV411 0x0200 806 #define I915_OVERLAY_YUV420 0x0300 807 #define I915_OVERLAY_YUV410 0x0400 808 809 #define I915_OVERLAY_SWAP_MASK 0xff0000 810 #define I915_OVERLAY_NO_SWAP 0x000000 811 #define I915_OVERLAY_UV_SWAP 0x010000 812 #define I915_OVERLAY_Y_SWAP 0x020000 813 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 814 815 #define I915_OVERLAY_FLAGS_MASK 0xff000000 816 #define I915_OVERLAY_ENABLE 0x01000000 817 818 struct drm_intel_overlay_put_image { 819 /* various flags and src format description */ 820 __u32 flags; 821 /* source picture description */ 822 __u32 bo_handle; 823 /* stride values and offsets are in bytes, buffer relative */ 824 __u16 stride_Y; /* stride for packed formats */ 825 __u16 stride_UV; 826 __u32 offset_Y; /* offset for packet formats */ 827 __u32 offset_U; 828 __u32 offset_V; 829 /* in pixels */ 830 __u16 src_width; 831 __u16 src_height; 832 /* to compensate the scaling factors for partially covered surfaces */ 833 __u16 src_scan_width; 834 __u16 src_scan_height; 835 /* output crtc description */ 836 __u32 crtc_id; 837 __u16 dst_x; 838 __u16 dst_y; 839 __u16 dst_width; 840 __u16 dst_height; 841 }; 842 843 /* flags */ 844 #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 845 #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 846 struct drm_intel_overlay_attrs { 847 __u32 flags; 848 __u32 color_key; 849 __s32 brightness; 850 __u32 contrast; 851 __u32 saturation; 852 __u32 gamma0; 853 __u32 gamma1; 854 __u32 gamma2; 855 __u32 gamma3; 856 __u32 gamma4; 857 __u32 gamma5; 858 }; 859 860 /* 861 * Intel sprite handling 862 * 863 * Color keying works with a min/mask/max tuple. Both source and destination 864 * color keying is allowed. 865 * 866 * Source keying: 867 * Sprite pixels within the min & max values, masked against the color channels 868 * specified in the mask field, will be transparent. All other pixels will 869 * be displayed on top of the primary plane. For RGB surfaces, only the min 870 * and mask fields will be used; ranged compares are not allowed. 871 * 872 * Destination keying: 873 * Primary plane pixels that match the min value, masked against the color 874 * channels specified in the mask field, will be replaced by corresponding 875 * pixels from the sprite plane. 876 * 877 * Note that source & destination keying are exclusive; only one can be 878 * active on a given plane. 879 */ 880 881 #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 882 #define I915_SET_COLORKEY_DESTINATION (1<<1) 883 #define I915_SET_COLORKEY_SOURCE (1<<2) 884 struct drm_intel_sprite_colorkey { 885 __u32 plane_id; 886 __u32 min_value; 887 __u32 channel_mask; 888 __u32 max_value; 889 __u32 flags; 890 }; 891 892 struct drm_i915_gem_wait { 893 /** Handle of BO we shall wait on */ 894 __u32 bo_handle; 895 __u32 flags; 896 /** Number of nanoseconds to wait, Returns time remaining. */ 897 __s64 timeout_ns; 898 }; 899 900 #endif /* _I915_DRM_H_ */ 901