1c0e09200SDave Airlie /* 2c0e09200SDave Airlie * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3c0e09200SDave Airlie * All Rights Reserved. 4c0e09200SDave Airlie * 5c0e09200SDave Airlie * Permission is hereby granted, free of charge, to any person obtaining a 6c0e09200SDave Airlie * copy of this software and associated documentation files (the 7c0e09200SDave Airlie * "Software"), to deal in the Software without restriction, including 8c0e09200SDave Airlie * without limitation the rights to use, copy, modify, merge, publish, 9c0e09200SDave Airlie * distribute, sub license, and/or sell copies of the Software, and to 10c0e09200SDave Airlie * permit persons to whom the Software is furnished to do so, subject to 11c0e09200SDave Airlie * the following conditions: 12c0e09200SDave Airlie * 13c0e09200SDave Airlie * The above copyright notice and this permission notice (including the 14c0e09200SDave Airlie * next paragraph) shall be included in all copies or substantial portions 15c0e09200SDave Airlie * of the Software. 16c0e09200SDave Airlie * 17c0e09200SDave Airlie * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18c0e09200SDave Airlie * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19c0e09200SDave Airlie * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20c0e09200SDave Airlie * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21c0e09200SDave Airlie * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22c0e09200SDave Airlie * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23c0e09200SDave Airlie * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24c0e09200SDave Airlie * 25c0e09200SDave Airlie */ 26c0e09200SDave Airlie #ifndef _I915_DRM_H_ 27c0e09200SDave Airlie #define _I915_DRM_H_ 28c0e09200SDave Airlie 29a0a18075SJesse Barnes #include <drm/i915_pciids.h> 30718dceddSDavid Howells #include <uapi/drm/i915_drm.h> 311a95916fSKristian Høgsberg 32aa7ffc01SJesse Barnes /* For use by IPS driver */ 33aa7ffc01SJesse Barnes extern unsigned long i915_read_mch_val(void); 34aa7ffc01SJesse Barnes extern bool i915_gpu_raise(void); 35aa7ffc01SJesse Barnes extern bool i915_gpu_lower(void); 36aa7ffc01SJesse Barnes extern bool i915_gpu_busy(void); 37aa7ffc01SJesse Barnes extern bool i915_gpu_turbo_disable(void); 38a0a18075SJesse Barnes 3955f56fc4SMatthew Auld /* Exported from arch/x86/kernel/early-quirks.c */ 4055f56fc4SMatthew Auld extern struct resource intel_graphics_stolen_res; 4155f56fc4SMatthew Auld 42814c5f1fSJesse Barnes /* 43814c5f1fSJesse Barnes * The Bridge device's PCI config space has information about the 44814c5f1fSJesse Barnes * fb aperture size and the amount of pre-reserved memory. 45814c5f1fSJesse Barnes * This is all handled in the intel-gtt.ko module. i915.ko only 46814c5f1fSJesse Barnes * cares about the vga bit for the vga rbiter. 47814c5f1fSJesse Barnes */ 48814c5f1fSJesse Barnes #define INTEL_GMCH_CTRL 0x52 49814c5f1fSJesse Barnes #define INTEL_GMCH_VGA_DISABLE (1 << 1) 50814c5f1fSJesse Barnes #define SNB_GMCH_CTRL 0x50 51814c5f1fSJesse Barnes #define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */ 52814c5f1fSJesse Barnes #define SNB_GMCH_GGMS_MASK 0x3 53814c5f1fSJesse Barnes #define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */ 54814c5f1fSJesse Barnes #define SNB_GMCH_GMS_MASK 0x1f 559459d252SBen Widawsky #define BDW_GMCH_GGMS_SHIFT 6 569459d252SBen Widawsky #define BDW_GMCH_GGMS_MASK 0x3 579459d252SBen Widawsky #define BDW_GMCH_GMS_SHIFT 8 589459d252SBen Widawsky #define BDW_GMCH_GMS_MASK 0xff 59814c5f1fSJesse Barnes 60814c5f1fSJesse Barnes #define I830_GMCH_CTRL 0x52 61814c5f1fSJesse Barnes 62a4dff769SVille Syrjälä #define I830_GMCH_GMS_MASK 0x70 63a4dff769SVille Syrjälä #define I830_GMCH_GMS_LOCAL 0x10 64a4dff769SVille Syrjälä #define I830_GMCH_GMS_STOLEN_512 0x20 65a4dff769SVille Syrjälä #define I830_GMCH_GMS_STOLEN_1024 0x30 66a4dff769SVille Syrjälä #define I830_GMCH_GMS_STOLEN_8192 0x40 67a4dff769SVille Syrjälä 68814c5f1fSJesse Barnes #define I855_GMCH_GMS_MASK 0xF0 69814c5f1fSJesse Barnes #define I855_GMCH_GMS_STOLEN_0M 0x0 70814c5f1fSJesse Barnes #define I855_GMCH_GMS_STOLEN_1M (0x1 << 4) 71814c5f1fSJesse Barnes #define I855_GMCH_GMS_STOLEN_4M (0x2 << 4) 72814c5f1fSJesse Barnes #define I855_GMCH_GMS_STOLEN_8M (0x3 << 4) 73814c5f1fSJesse Barnes #define I855_GMCH_GMS_STOLEN_16M (0x4 << 4) 74814c5f1fSJesse Barnes #define I855_GMCH_GMS_STOLEN_32M (0x5 << 4) 75814c5f1fSJesse Barnes #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) 76814c5f1fSJesse Barnes #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) 77814c5f1fSJesse Barnes #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) 78814c5f1fSJesse Barnes #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) 79814c5f1fSJesse Barnes #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) 80814c5f1fSJesse Barnes #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) 81814c5f1fSJesse Barnes #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) 82814c5f1fSJesse Barnes #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) 83814c5f1fSJesse Barnes 84a4dff769SVille Syrjälä #define I830_DRB3 0x63 85a4dff769SVille Syrjälä #define I85X_DRB3 0x43 86a4dff769SVille Syrjälä #define I865_TOUD 0xc4 87a4dff769SVille Syrjälä 88a4dff769SVille Syrjälä #define I830_ESMRAMC 0x91 89a4dff769SVille Syrjälä #define I845_ESMRAMC 0x9e 90a4dff769SVille Syrjälä #define I85X_ESMRAMC 0x61 91a4dff769SVille Syrjälä #define TSEG_ENABLE (1 << 0) 92a4dff769SVille Syrjälä #define I830_TSEG_SIZE_512K (0 << 1) 93a4dff769SVille Syrjälä #define I830_TSEG_SIZE_1M (1 << 1) 94a4dff769SVille Syrjälä #define I845_TSEG_SIZE_MASK (3 << 1) 95a4dff769SVille Syrjälä #define I845_TSEG_SIZE_512K (2 << 1) 96a4dff769SVille Syrjälä #define I845_TSEG_SIZE_1M (3 << 1) 97a4dff769SVille Syrjälä 98c0dd3460SJoonas Lahtinen #define INTEL_BSM 0x5c 99db0c8d8bSPaulo Zanoni #define INTEL_GEN11_BSM_DW0 0xc0 100db0c8d8bSPaulo Zanoni #define INTEL_GEN11_BSM_DW1 0xc4 101aac440ffSDave Gordon #define INTEL_BSM_MASK (-(1u << 20)) 102c0dd3460SJoonas Lahtinen 103c0e09200SDave Airlie #endif /* _I915_DRM_H_ */ 104