1c0e09200SDave Airlie /* 2c0e09200SDave Airlie * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3c0e09200SDave Airlie * All Rights Reserved. 4c0e09200SDave Airlie * 5c0e09200SDave Airlie * Permission is hereby granted, free of charge, to any person obtaining a 6c0e09200SDave Airlie * copy of this software and associated documentation files (the 7c0e09200SDave Airlie * "Software"), to deal in the Software without restriction, including 8c0e09200SDave Airlie * without limitation the rights to use, copy, modify, merge, publish, 9c0e09200SDave Airlie * distribute, sub license, and/or sell copies of the Software, and to 10c0e09200SDave Airlie * permit persons to whom the Software is furnished to do so, subject to 11c0e09200SDave Airlie * the following conditions: 12c0e09200SDave Airlie * 13c0e09200SDave Airlie * The above copyright notice and this permission notice (including the 14c0e09200SDave Airlie * next paragraph) shall be included in all copies or substantial portions 15c0e09200SDave Airlie * of the Software. 16c0e09200SDave Airlie * 17c0e09200SDave Airlie * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18c0e09200SDave Airlie * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19c0e09200SDave Airlie * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20c0e09200SDave Airlie * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21c0e09200SDave Airlie * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22c0e09200SDave Airlie * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23c0e09200SDave Airlie * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24c0e09200SDave Airlie * 25c0e09200SDave Airlie */ 26c0e09200SDave Airlie 27c0e09200SDave Airlie #ifndef _I915_DRM_H_ 28c0e09200SDave Airlie #define _I915_DRM_H_ 29c0e09200SDave Airlie 30c0e09200SDave Airlie /* Please note that modifications to all structs defined here are 31c0e09200SDave Airlie * subject to backwards-compatibility constraints. 32c0e09200SDave Airlie */ 33c0e09200SDave Airlie 34c0e09200SDave Airlie #include "drm.h" 35c0e09200SDave Airlie 36c0e09200SDave Airlie /* Each region is a minimum of 16k, and there are at most 255 of them. 37c0e09200SDave Airlie */ 38c0e09200SDave Airlie #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 39c0e09200SDave Airlie * of chars for next/prev indices */ 40c0e09200SDave Airlie #define I915_LOG_MIN_TEX_REGION_SIZE 14 41c0e09200SDave Airlie 42c0e09200SDave Airlie typedef struct _drm_i915_init { 43c0e09200SDave Airlie enum { 44c0e09200SDave Airlie I915_INIT_DMA = 0x01, 45c0e09200SDave Airlie I915_CLEANUP_DMA = 0x02, 46c0e09200SDave Airlie I915_RESUME_DMA = 0x03 47c0e09200SDave Airlie } func; 48c0e09200SDave Airlie unsigned int mmio_offset; 49c0e09200SDave Airlie int sarea_priv_offset; 50c0e09200SDave Airlie unsigned int ring_start; 51c0e09200SDave Airlie unsigned int ring_end; 52c0e09200SDave Airlie unsigned int ring_size; 53c0e09200SDave Airlie unsigned int front_offset; 54c0e09200SDave Airlie unsigned int back_offset; 55c0e09200SDave Airlie unsigned int depth_offset; 56c0e09200SDave Airlie unsigned int w; 57c0e09200SDave Airlie unsigned int h; 58c0e09200SDave Airlie unsigned int pitch; 59c0e09200SDave Airlie unsigned int pitch_bits; 60c0e09200SDave Airlie unsigned int back_pitch; 61c0e09200SDave Airlie unsigned int depth_pitch; 62c0e09200SDave Airlie unsigned int cpp; 63c0e09200SDave Airlie unsigned int chipset; 64c0e09200SDave Airlie } drm_i915_init_t; 65c0e09200SDave Airlie 66c0e09200SDave Airlie typedef struct _drm_i915_sarea { 67c0e09200SDave Airlie struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 68c0e09200SDave Airlie int last_upload; /* last time texture was uploaded */ 69c0e09200SDave Airlie int last_enqueue; /* last time a buffer was enqueued */ 70c0e09200SDave Airlie int last_dispatch; /* age of the most recently dispatched buffer */ 71c0e09200SDave Airlie int ctxOwner; /* last context to upload state */ 72c0e09200SDave Airlie int texAge; 73c0e09200SDave Airlie int pf_enabled; /* is pageflipping allowed? */ 74c0e09200SDave Airlie int pf_active; 75c0e09200SDave Airlie int pf_current_page; /* which buffer is being displayed? */ 76c0e09200SDave Airlie int perf_boxes; /* performance boxes to be displayed */ 77c0e09200SDave Airlie int width, height; /* screen size in pixels */ 78c0e09200SDave Airlie 79c0e09200SDave Airlie drm_handle_t front_handle; 80c0e09200SDave Airlie int front_offset; 81c0e09200SDave Airlie int front_size; 82c0e09200SDave Airlie 83c0e09200SDave Airlie drm_handle_t back_handle; 84c0e09200SDave Airlie int back_offset; 85c0e09200SDave Airlie int back_size; 86c0e09200SDave Airlie 87c0e09200SDave Airlie drm_handle_t depth_handle; 88c0e09200SDave Airlie int depth_offset; 89c0e09200SDave Airlie int depth_size; 90c0e09200SDave Airlie 91c0e09200SDave Airlie drm_handle_t tex_handle; 92c0e09200SDave Airlie int tex_offset; 93c0e09200SDave Airlie int tex_size; 94c0e09200SDave Airlie int log_tex_granularity; 95c0e09200SDave Airlie int pitch; 96c0e09200SDave Airlie int rotation; /* 0, 90, 180 or 270 */ 97c0e09200SDave Airlie int rotated_offset; 98c0e09200SDave Airlie int rotated_size; 99c0e09200SDave Airlie int rotated_pitch; 100c0e09200SDave Airlie int virtualX, virtualY; 101c0e09200SDave Airlie 102c0e09200SDave Airlie unsigned int front_tiled; 103c0e09200SDave Airlie unsigned int back_tiled; 104c0e09200SDave Airlie unsigned int depth_tiled; 105c0e09200SDave Airlie unsigned int rotated_tiled; 106c0e09200SDave Airlie unsigned int rotated2_tiled; 107c0e09200SDave Airlie 108c0e09200SDave Airlie int pipeA_x; 109c0e09200SDave Airlie int pipeA_y; 110c0e09200SDave Airlie int pipeA_w; 111c0e09200SDave Airlie int pipeA_h; 112c0e09200SDave Airlie int pipeB_x; 113c0e09200SDave Airlie int pipeB_y; 114c0e09200SDave Airlie int pipeB_w; 115c0e09200SDave Airlie int pipeB_h; 116c0e09200SDave Airlie } drm_i915_sarea_t; 117c0e09200SDave Airlie 118c0e09200SDave Airlie /* Flags for perf_boxes 119c0e09200SDave Airlie */ 120c0e09200SDave Airlie #define I915_BOX_RING_EMPTY 0x1 121c0e09200SDave Airlie #define I915_BOX_FLIP 0x2 122c0e09200SDave Airlie #define I915_BOX_WAIT 0x4 123c0e09200SDave Airlie #define I915_BOX_TEXTURE_LOAD 0x8 124c0e09200SDave Airlie #define I915_BOX_LOST_CONTEXT 0x10 125c0e09200SDave Airlie 126c0e09200SDave Airlie /* I915 specific ioctls 127c0e09200SDave Airlie * The device specific ioctl range is 0x40 to 0x79. 128c0e09200SDave Airlie */ 129c0e09200SDave Airlie #define DRM_I915_INIT 0x00 130c0e09200SDave Airlie #define DRM_I915_FLUSH 0x01 131c0e09200SDave Airlie #define DRM_I915_FLIP 0x02 132c0e09200SDave Airlie #define DRM_I915_BATCHBUFFER 0x03 133c0e09200SDave Airlie #define DRM_I915_IRQ_EMIT 0x04 134c0e09200SDave Airlie #define DRM_I915_IRQ_WAIT 0x05 135c0e09200SDave Airlie #define DRM_I915_GETPARAM 0x06 136c0e09200SDave Airlie #define DRM_I915_SETPARAM 0x07 137c0e09200SDave Airlie #define DRM_I915_ALLOC 0x08 138c0e09200SDave Airlie #define DRM_I915_FREE 0x09 139c0e09200SDave Airlie #define DRM_I915_INIT_HEAP 0x0a 140c0e09200SDave Airlie #define DRM_I915_CMDBUFFER 0x0b 141c0e09200SDave Airlie #define DRM_I915_DESTROY_HEAP 0x0c 142c0e09200SDave Airlie #define DRM_I915_SET_VBLANK_PIPE 0x0d 143c0e09200SDave Airlie #define DRM_I915_GET_VBLANK_PIPE 0x0e 144c0e09200SDave Airlie #define DRM_I915_VBLANK_SWAP 0x0f 145c0e09200SDave Airlie #define DRM_I915_HWS_ADDR 0x11 146c0e09200SDave Airlie 147c0e09200SDave Airlie #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 148c0e09200SDave Airlie #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 149c0e09200SDave Airlie #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 150c0e09200SDave Airlie #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 151c0e09200SDave Airlie #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 152c0e09200SDave Airlie #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 153c0e09200SDave Airlie #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 154c0e09200SDave Airlie #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 155c0e09200SDave Airlie #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 156c0e09200SDave Airlie #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 157c0e09200SDave Airlie #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 158c0e09200SDave Airlie #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 159c0e09200SDave Airlie #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 160c0e09200SDave Airlie #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 161c0e09200SDave Airlie #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 162c0e09200SDave Airlie #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 163c0e09200SDave Airlie 164c0e09200SDave Airlie /* Allow drivers to submit batchbuffers directly to hardware, relying 165c0e09200SDave Airlie * on the security mechanisms provided by hardware. 166c0e09200SDave Airlie */ 167c0e09200SDave Airlie typedef struct _drm_i915_batchbuffer { 168c0e09200SDave Airlie int start; /* agp offset */ 169c0e09200SDave Airlie int used; /* nr bytes in use */ 170c0e09200SDave Airlie int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 171c0e09200SDave Airlie int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 172c0e09200SDave Airlie int num_cliprects; /* mulitpass with multiple cliprects? */ 173c0e09200SDave Airlie struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 174c0e09200SDave Airlie } drm_i915_batchbuffer_t; 175c0e09200SDave Airlie 176c0e09200SDave Airlie /* As above, but pass a pointer to userspace buffer which can be 177c0e09200SDave Airlie * validated by the kernel prior to sending to hardware. 178c0e09200SDave Airlie */ 179c0e09200SDave Airlie typedef struct _drm_i915_cmdbuffer { 180c0e09200SDave Airlie char __user *buf; /* pointer to userspace command buffer */ 181c0e09200SDave Airlie int sz; /* nr bytes in buf */ 182c0e09200SDave Airlie int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 183c0e09200SDave Airlie int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 184c0e09200SDave Airlie int num_cliprects; /* mulitpass with multiple cliprects? */ 185c0e09200SDave Airlie struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 186c0e09200SDave Airlie } drm_i915_cmdbuffer_t; 187c0e09200SDave Airlie 188c0e09200SDave Airlie /* Userspace can request & wait on irq's: 189c0e09200SDave Airlie */ 190c0e09200SDave Airlie typedef struct drm_i915_irq_emit { 191c0e09200SDave Airlie int __user *irq_seq; 192c0e09200SDave Airlie } drm_i915_irq_emit_t; 193c0e09200SDave Airlie 194c0e09200SDave Airlie typedef struct drm_i915_irq_wait { 195c0e09200SDave Airlie int irq_seq; 196c0e09200SDave Airlie } drm_i915_irq_wait_t; 197c0e09200SDave Airlie 198c0e09200SDave Airlie /* Ioctl to query kernel params: 199c0e09200SDave Airlie */ 200c0e09200SDave Airlie #define I915_PARAM_IRQ_ACTIVE 1 201c0e09200SDave Airlie #define I915_PARAM_ALLOW_BATCHBUFFER 2 202c0e09200SDave Airlie #define I915_PARAM_LAST_DISPATCH 3 203c0e09200SDave Airlie 204c0e09200SDave Airlie typedef struct drm_i915_getparam { 205c0e09200SDave Airlie int param; 206c0e09200SDave Airlie int __user *value; 207c0e09200SDave Airlie } drm_i915_getparam_t; 208c0e09200SDave Airlie 209c0e09200SDave Airlie /* Ioctl to set kernel params: 210c0e09200SDave Airlie */ 211c0e09200SDave Airlie #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 212c0e09200SDave Airlie #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 213c0e09200SDave Airlie #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 214c0e09200SDave Airlie 215c0e09200SDave Airlie typedef struct drm_i915_setparam { 216c0e09200SDave Airlie int param; 217c0e09200SDave Airlie int value; 218c0e09200SDave Airlie } drm_i915_setparam_t; 219c0e09200SDave Airlie 220c0e09200SDave Airlie /* A memory manager for regions of shared memory: 221c0e09200SDave Airlie */ 222c0e09200SDave Airlie #define I915_MEM_REGION_AGP 1 223c0e09200SDave Airlie 224c0e09200SDave Airlie typedef struct drm_i915_mem_alloc { 225c0e09200SDave Airlie int region; 226c0e09200SDave Airlie int alignment; 227c0e09200SDave Airlie int size; 228c0e09200SDave Airlie int __user *region_offset; /* offset from start of fb or agp */ 229c0e09200SDave Airlie } drm_i915_mem_alloc_t; 230c0e09200SDave Airlie 231c0e09200SDave Airlie typedef struct drm_i915_mem_free { 232c0e09200SDave Airlie int region; 233c0e09200SDave Airlie int region_offset; 234c0e09200SDave Airlie } drm_i915_mem_free_t; 235c0e09200SDave Airlie 236c0e09200SDave Airlie typedef struct drm_i915_mem_init_heap { 237c0e09200SDave Airlie int region; 238c0e09200SDave Airlie int size; 239c0e09200SDave Airlie int start; 240c0e09200SDave Airlie } drm_i915_mem_init_heap_t; 241c0e09200SDave Airlie 242c0e09200SDave Airlie /* Allow memory manager to be torn down and re-initialized (eg on 243c0e09200SDave Airlie * rotate): 244c0e09200SDave Airlie */ 245c0e09200SDave Airlie typedef struct drm_i915_mem_destroy_heap { 246c0e09200SDave Airlie int region; 247c0e09200SDave Airlie } drm_i915_mem_destroy_heap_t; 248c0e09200SDave Airlie 249c0e09200SDave Airlie /* Allow X server to configure which pipes to monitor for vblank signals 250c0e09200SDave Airlie */ 251c0e09200SDave Airlie #define DRM_I915_VBLANK_PIPE_A 1 252c0e09200SDave Airlie #define DRM_I915_VBLANK_PIPE_B 2 253c0e09200SDave Airlie 254c0e09200SDave Airlie typedef struct drm_i915_vblank_pipe { 255c0e09200SDave Airlie int pipe; 256c0e09200SDave Airlie } drm_i915_vblank_pipe_t; 257c0e09200SDave Airlie 258c0e09200SDave Airlie /* Schedule buffer swap at given vertical blank: 259c0e09200SDave Airlie */ 260c0e09200SDave Airlie typedef struct drm_i915_vblank_swap { 261c0e09200SDave Airlie drm_drawable_t drawable; 262c0e09200SDave Airlie enum drm_vblank_seq_type seqtype; 263c0e09200SDave Airlie unsigned int sequence; 264c0e09200SDave Airlie } drm_i915_vblank_swap_t; 265c0e09200SDave Airlie 266c0e09200SDave Airlie typedef struct drm_i915_hws_addr { 267c0e09200SDave Airlie uint64_t addr; 268c0e09200SDave Airlie } drm_i915_hws_addr_t; 269c0e09200SDave Airlie 270c0e09200SDave Airlie #endif /* _I915_DRM_H_ */ 271