1c0e09200SDave Airlie /* 2c0e09200SDave Airlie * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3c0e09200SDave Airlie * All Rights Reserved. 4c0e09200SDave Airlie * 5c0e09200SDave Airlie * Permission is hereby granted, free of charge, to any person obtaining a 6c0e09200SDave Airlie * copy of this software and associated documentation files (the 7c0e09200SDave Airlie * "Software"), to deal in the Software without restriction, including 8c0e09200SDave Airlie * without limitation the rights to use, copy, modify, merge, publish, 9c0e09200SDave Airlie * distribute, sub license, and/or sell copies of the Software, and to 10c0e09200SDave Airlie * permit persons to whom the Software is furnished to do so, subject to 11c0e09200SDave Airlie * the following conditions: 12c0e09200SDave Airlie * 13c0e09200SDave Airlie * The above copyright notice and this permission notice (including the 14c0e09200SDave Airlie * next paragraph) shall be included in all copies or substantial portions 15c0e09200SDave Airlie * of the Software. 16c0e09200SDave Airlie * 17c0e09200SDave Airlie * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18c0e09200SDave Airlie * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19c0e09200SDave Airlie * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20c0e09200SDave Airlie * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21c0e09200SDave Airlie * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22c0e09200SDave Airlie * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23c0e09200SDave Airlie * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24c0e09200SDave Airlie * 25c0e09200SDave Airlie */ 26c0e09200SDave Airlie 27c0e09200SDave Airlie #ifndef _I915_DRM_H_ 28c0e09200SDave Airlie #define _I915_DRM_H_ 29c0e09200SDave Airlie 30c0e09200SDave Airlie /* Please note that modifications to all structs defined here are 31c0e09200SDave Airlie * subject to backwards-compatibility constraints. 32c0e09200SDave Airlie */ 331d7f83d5SArnd Bergmann #include <linux/types.h> 34c0e09200SDave Airlie #include "drm.h" 35c0e09200SDave Airlie 36c0e09200SDave Airlie /* Each region is a minimum of 16k, and there are at most 255 of them. 37c0e09200SDave Airlie */ 38c0e09200SDave Airlie #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 39c0e09200SDave Airlie * of chars for next/prev indices */ 40c0e09200SDave Airlie #define I915_LOG_MIN_TEX_REGION_SIZE 14 41c0e09200SDave Airlie 42c0e09200SDave Airlie typedef struct _drm_i915_init { 43c0e09200SDave Airlie enum { 44c0e09200SDave Airlie I915_INIT_DMA = 0x01, 45c0e09200SDave Airlie I915_CLEANUP_DMA = 0x02, 46c0e09200SDave Airlie I915_RESUME_DMA = 0x03 47c0e09200SDave Airlie } func; 48c0e09200SDave Airlie unsigned int mmio_offset; 49c0e09200SDave Airlie int sarea_priv_offset; 50c0e09200SDave Airlie unsigned int ring_start; 51c0e09200SDave Airlie unsigned int ring_end; 52c0e09200SDave Airlie unsigned int ring_size; 53c0e09200SDave Airlie unsigned int front_offset; 54c0e09200SDave Airlie unsigned int back_offset; 55c0e09200SDave Airlie unsigned int depth_offset; 56c0e09200SDave Airlie unsigned int w; 57c0e09200SDave Airlie unsigned int h; 58c0e09200SDave Airlie unsigned int pitch; 59c0e09200SDave Airlie unsigned int pitch_bits; 60c0e09200SDave Airlie unsigned int back_pitch; 61c0e09200SDave Airlie unsigned int depth_pitch; 62c0e09200SDave Airlie unsigned int cpp; 63c0e09200SDave Airlie unsigned int chipset; 64c0e09200SDave Airlie } drm_i915_init_t; 65c0e09200SDave Airlie 66c0e09200SDave Airlie typedef struct _drm_i915_sarea { 67c0e09200SDave Airlie struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 68c0e09200SDave Airlie int last_upload; /* last time texture was uploaded */ 69c0e09200SDave Airlie int last_enqueue; /* last time a buffer was enqueued */ 70c0e09200SDave Airlie int last_dispatch; /* age of the most recently dispatched buffer */ 71c0e09200SDave Airlie int ctxOwner; /* last context to upload state */ 72c0e09200SDave Airlie int texAge; 73c0e09200SDave Airlie int pf_enabled; /* is pageflipping allowed? */ 74c0e09200SDave Airlie int pf_active; 75c0e09200SDave Airlie int pf_current_page; /* which buffer is being displayed? */ 76c0e09200SDave Airlie int perf_boxes; /* performance boxes to be displayed */ 77c0e09200SDave Airlie int width, height; /* screen size in pixels */ 78c0e09200SDave Airlie 79c0e09200SDave Airlie drm_handle_t front_handle; 80c0e09200SDave Airlie int front_offset; 81c0e09200SDave Airlie int front_size; 82c0e09200SDave Airlie 83c0e09200SDave Airlie drm_handle_t back_handle; 84c0e09200SDave Airlie int back_offset; 85c0e09200SDave Airlie int back_size; 86c0e09200SDave Airlie 87c0e09200SDave Airlie drm_handle_t depth_handle; 88c0e09200SDave Airlie int depth_offset; 89c0e09200SDave Airlie int depth_size; 90c0e09200SDave Airlie 91c0e09200SDave Airlie drm_handle_t tex_handle; 92c0e09200SDave Airlie int tex_offset; 93c0e09200SDave Airlie int tex_size; 94c0e09200SDave Airlie int log_tex_granularity; 95c0e09200SDave Airlie int pitch; 96c0e09200SDave Airlie int rotation; /* 0, 90, 180 or 270 */ 97c0e09200SDave Airlie int rotated_offset; 98c0e09200SDave Airlie int rotated_size; 99c0e09200SDave Airlie int rotated_pitch; 100c0e09200SDave Airlie int virtualX, virtualY; 101c0e09200SDave Airlie 102c0e09200SDave Airlie unsigned int front_tiled; 103c0e09200SDave Airlie unsigned int back_tiled; 104c0e09200SDave Airlie unsigned int depth_tiled; 105c0e09200SDave Airlie unsigned int rotated_tiled; 106c0e09200SDave Airlie unsigned int rotated2_tiled; 107c0e09200SDave Airlie 108c0e09200SDave Airlie int pipeA_x; 109c0e09200SDave Airlie int pipeA_y; 110c0e09200SDave Airlie int pipeA_w; 111c0e09200SDave Airlie int pipeA_h; 112c0e09200SDave Airlie int pipeB_x; 113c0e09200SDave Airlie int pipeB_y; 114c0e09200SDave Airlie int pipeB_w; 115c0e09200SDave Airlie int pipeB_h; 116dfef2459SDave Airlie 117dfef2459SDave Airlie /* fill out some space for old userspace triple buffer */ 118dfef2459SDave Airlie drm_handle_t unused_handle; 1191d7f83d5SArnd Bergmann __u32 unused1, unused2, unused3; 120dfef2459SDave Airlie 121dfef2459SDave Airlie /* buffer object handles for static buffers. May change 122dfef2459SDave Airlie * over the lifetime of the client. 123dfef2459SDave Airlie */ 1241d7f83d5SArnd Bergmann __u32 front_bo_handle; 1251d7f83d5SArnd Bergmann __u32 back_bo_handle; 1261d7f83d5SArnd Bergmann __u32 unused_bo_handle; 1271d7f83d5SArnd Bergmann __u32 depth_bo_handle; 128dfef2459SDave Airlie 129c0e09200SDave Airlie } drm_i915_sarea_t; 130c0e09200SDave Airlie 131dfef2459SDave Airlie /* due to userspace building against these headers we need some compat here */ 132dfef2459SDave Airlie #define planeA_x pipeA_x 133dfef2459SDave Airlie #define planeA_y pipeA_y 134dfef2459SDave Airlie #define planeA_w pipeA_w 135dfef2459SDave Airlie #define planeA_h pipeA_h 136dfef2459SDave Airlie #define planeB_x pipeB_x 137dfef2459SDave Airlie #define planeB_y pipeB_y 138dfef2459SDave Airlie #define planeB_w pipeB_w 139dfef2459SDave Airlie #define planeB_h pipeB_h 140dfef2459SDave Airlie 141c0e09200SDave Airlie /* Flags for perf_boxes 142c0e09200SDave Airlie */ 143c0e09200SDave Airlie #define I915_BOX_RING_EMPTY 0x1 144c0e09200SDave Airlie #define I915_BOX_FLIP 0x2 145c0e09200SDave Airlie #define I915_BOX_WAIT 0x4 146c0e09200SDave Airlie #define I915_BOX_TEXTURE_LOAD 0x8 147c0e09200SDave Airlie #define I915_BOX_LOST_CONTEXT 0x10 148c0e09200SDave Airlie 149c0e09200SDave Airlie /* I915 specific ioctls 150c0e09200SDave Airlie * The device specific ioctl range is 0x40 to 0x79. 151c0e09200SDave Airlie */ 152c0e09200SDave Airlie #define DRM_I915_INIT 0x00 153c0e09200SDave Airlie #define DRM_I915_FLUSH 0x01 154c0e09200SDave Airlie #define DRM_I915_FLIP 0x02 155c0e09200SDave Airlie #define DRM_I915_BATCHBUFFER 0x03 156c0e09200SDave Airlie #define DRM_I915_IRQ_EMIT 0x04 157c0e09200SDave Airlie #define DRM_I915_IRQ_WAIT 0x05 158c0e09200SDave Airlie #define DRM_I915_GETPARAM 0x06 159c0e09200SDave Airlie #define DRM_I915_SETPARAM 0x07 160c0e09200SDave Airlie #define DRM_I915_ALLOC 0x08 161c0e09200SDave Airlie #define DRM_I915_FREE 0x09 162c0e09200SDave Airlie #define DRM_I915_INIT_HEAP 0x0a 163c0e09200SDave Airlie #define DRM_I915_CMDBUFFER 0x0b 164c0e09200SDave Airlie #define DRM_I915_DESTROY_HEAP 0x0c 165c0e09200SDave Airlie #define DRM_I915_SET_VBLANK_PIPE 0x0d 166c0e09200SDave Airlie #define DRM_I915_GET_VBLANK_PIPE 0x0e 167c0e09200SDave Airlie #define DRM_I915_VBLANK_SWAP 0x0f 168c0e09200SDave Airlie #define DRM_I915_HWS_ADDR 0x11 169673a394bSEric Anholt #define DRM_I915_GEM_INIT 0x13 170673a394bSEric Anholt #define DRM_I915_GEM_EXECBUFFER 0x14 171673a394bSEric Anholt #define DRM_I915_GEM_PIN 0x15 172673a394bSEric Anholt #define DRM_I915_GEM_UNPIN 0x16 173673a394bSEric Anholt #define DRM_I915_GEM_BUSY 0x17 174673a394bSEric Anholt #define DRM_I915_GEM_THROTTLE 0x18 175673a394bSEric Anholt #define DRM_I915_GEM_ENTERVT 0x19 176673a394bSEric Anholt #define DRM_I915_GEM_LEAVEVT 0x1a 177673a394bSEric Anholt #define DRM_I915_GEM_CREATE 0x1b 178673a394bSEric Anholt #define DRM_I915_GEM_PREAD 0x1c 179673a394bSEric Anholt #define DRM_I915_GEM_PWRITE 0x1d 180673a394bSEric Anholt #define DRM_I915_GEM_MMAP 0x1e 181673a394bSEric Anholt #define DRM_I915_GEM_SET_DOMAIN 0x1f 182673a394bSEric Anholt #define DRM_I915_GEM_SW_FINISH 0x20 183673a394bSEric Anholt #define DRM_I915_GEM_SET_TILING 0x21 184673a394bSEric Anholt #define DRM_I915_GEM_GET_TILING 0x22 1855a125c3cSEric Anholt #define DRM_I915_GEM_GET_APERTURE 0x23 186de151cf6SJesse Barnes #define DRM_I915_GEM_MMAP_GTT 0x24 18708d7b3d1SCarl Worth #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 1883ef94daaSChris Wilson #define DRM_I915_GEM_MADVISE 0x26 189c0e09200SDave Airlie 190c0e09200SDave Airlie #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 191c0e09200SDave Airlie #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 192c0e09200SDave Airlie #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 193c0e09200SDave Airlie #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 194c0e09200SDave Airlie #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 195c0e09200SDave Airlie #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 196c0e09200SDave Airlie #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 197c0e09200SDave Airlie #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 198c0e09200SDave Airlie #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 199c0e09200SDave Airlie #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 200c0e09200SDave Airlie #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 201c0e09200SDave Airlie #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 202c0e09200SDave Airlie #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 203c0e09200SDave Airlie #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 204c0e09200SDave Airlie #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 205c0e09200SDave Airlie #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 2068d391aa4SEric Anholt #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 2078d391aa4SEric Anholt #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 208673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 209673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 210673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 211673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 212673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 213673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 214673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 215673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 216673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 217673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 218de151cf6SJesse Barnes #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 219673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 220673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 221673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 222673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 2235a125c3cSEric Anholt #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 22408d7b3d1SCarl Worth #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_intel_get_pipe_from_crtc_id) 2253ef94daaSChris Wilson #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 226c0e09200SDave Airlie 227c0e09200SDave Airlie /* Allow drivers to submit batchbuffers directly to hardware, relying 228c0e09200SDave Airlie * on the security mechanisms provided by hardware. 229c0e09200SDave Airlie */ 23079e53945SJesse Barnes typedef struct drm_i915_batchbuffer { 231c0e09200SDave Airlie int start; /* agp offset */ 232c0e09200SDave Airlie int used; /* nr bytes in use */ 233c0e09200SDave Airlie int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 234c0e09200SDave Airlie int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 235c0e09200SDave Airlie int num_cliprects; /* mulitpass with multiple cliprects? */ 236c0e09200SDave Airlie struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 237c0e09200SDave Airlie } drm_i915_batchbuffer_t; 238c0e09200SDave Airlie 239c0e09200SDave Airlie /* As above, but pass a pointer to userspace buffer which can be 240c0e09200SDave Airlie * validated by the kernel prior to sending to hardware. 241c0e09200SDave Airlie */ 242c0e09200SDave Airlie typedef struct _drm_i915_cmdbuffer { 243c0e09200SDave Airlie char __user *buf; /* pointer to userspace command buffer */ 244c0e09200SDave Airlie int sz; /* nr bytes in buf */ 245c0e09200SDave Airlie int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 246c0e09200SDave Airlie int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 247c0e09200SDave Airlie int num_cliprects; /* mulitpass with multiple cliprects? */ 248c0e09200SDave Airlie struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 249c0e09200SDave Airlie } drm_i915_cmdbuffer_t; 250c0e09200SDave Airlie 251c0e09200SDave Airlie /* Userspace can request & wait on irq's: 252c0e09200SDave Airlie */ 253c0e09200SDave Airlie typedef struct drm_i915_irq_emit { 254c0e09200SDave Airlie int __user *irq_seq; 255c0e09200SDave Airlie } drm_i915_irq_emit_t; 256c0e09200SDave Airlie 257c0e09200SDave Airlie typedef struct drm_i915_irq_wait { 258c0e09200SDave Airlie int irq_seq; 259c0e09200SDave Airlie } drm_i915_irq_wait_t; 260c0e09200SDave Airlie 261c0e09200SDave Airlie /* Ioctl to query kernel params: 262c0e09200SDave Airlie */ 263c0e09200SDave Airlie #define I915_PARAM_IRQ_ACTIVE 1 264c0e09200SDave Airlie #define I915_PARAM_ALLOW_BATCHBUFFER 2 265c0e09200SDave Airlie #define I915_PARAM_LAST_DISPATCH 3 266ed4c9c4aSKristian Høgsberg #define I915_PARAM_CHIPSET_ID 4 267673a394bSEric Anholt #define I915_PARAM_HAS_GEM 5 2680f973f27SJesse Barnes #define I915_PARAM_NUM_FENCES_AVAIL 6 269c0e09200SDave Airlie 270c0e09200SDave Airlie typedef struct drm_i915_getparam { 271c0e09200SDave Airlie int param; 272c0e09200SDave Airlie int __user *value; 273c0e09200SDave Airlie } drm_i915_getparam_t; 274c0e09200SDave Airlie 275c0e09200SDave Airlie /* Ioctl to set kernel params: 276c0e09200SDave Airlie */ 277c0e09200SDave Airlie #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 278c0e09200SDave Airlie #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 279c0e09200SDave Airlie #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 2800f973f27SJesse Barnes #define I915_SETPARAM_NUM_USED_FENCES 4 281c0e09200SDave Airlie 282c0e09200SDave Airlie typedef struct drm_i915_setparam { 283c0e09200SDave Airlie int param; 284c0e09200SDave Airlie int value; 285c0e09200SDave Airlie } drm_i915_setparam_t; 286c0e09200SDave Airlie 287c0e09200SDave Airlie /* A memory manager for regions of shared memory: 288c0e09200SDave Airlie */ 289c0e09200SDave Airlie #define I915_MEM_REGION_AGP 1 290c0e09200SDave Airlie 291c0e09200SDave Airlie typedef struct drm_i915_mem_alloc { 292c0e09200SDave Airlie int region; 293c0e09200SDave Airlie int alignment; 294c0e09200SDave Airlie int size; 295c0e09200SDave Airlie int __user *region_offset; /* offset from start of fb or agp */ 296c0e09200SDave Airlie } drm_i915_mem_alloc_t; 297c0e09200SDave Airlie 298c0e09200SDave Airlie typedef struct drm_i915_mem_free { 299c0e09200SDave Airlie int region; 300c0e09200SDave Airlie int region_offset; 301c0e09200SDave Airlie } drm_i915_mem_free_t; 302c0e09200SDave Airlie 303c0e09200SDave Airlie typedef struct drm_i915_mem_init_heap { 304c0e09200SDave Airlie int region; 305c0e09200SDave Airlie int size; 306c0e09200SDave Airlie int start; 307c0e09200SDave Airlie } drm_i915_mem_init_heap_t; 308c0e09200SDave Airlie 309c0e09200SDave Airlie /* Allow memory manager to be torn down and re-initialized (eg on 310c0e09200SDave Airlie * rotate): 311c0e09200SDave Airlie */ 312c0e09200SDave Airlie typedef struct drm_i915_mem_destroy_heap { 313c0e09200SDave Airlie int region; 314c0e09200SDave Airlie } drm_i915_mem_destroy_heap_t; 315c0e09200SDave Airlie 316c0e09200SDave Airlie /* Allow X server to configure which pipes to monitor for vblank signals 317c0e09200SDave Airlie */ 318c0e09200SDave Airlie #define DRM_I915_VBLANK_PIPE_A 1 319c0e09200SDave Airlie #define DRM_I915_VBLANK_PIPE_B 2 320c0e09200SDave Airlie 321c0e09200SDave Airlie typedef struct drm_i915_vblank_pipe { 322c0e09200SDave Airlie int pipe; 323c0e09200SDave Airlie } drm_i915_vblank_pipe_t; 324c0e09200SDave Airlie 325c0e09200SDave Airlie /* Schedule buffer swap at given vertical blank: 326c0e09200SDave Airlie */ 327c0e09200SDave Airlie typedef struct drm_i915_vblank_swap { 328c0e09200SDave Airlie drm_drawable_t drawable; 329c0e09200SDave Airlie enum drm_vblank_seq_type seqtype; 330c0e09200SDave Airlie unsigned int sequence; 331c0e09200SDave Airlie } drm_i915_vblank_swap_t; 332c0e09200SDave Airlie 333c0e09200SDave Airlie typedef struct drm_i915_hws_addr { 3341d7f83d5SArnd Bergmann __u64 addr; 335c0e09200SDave Airlie } drm_i915_hws_addr_t; 336c0e09200SDave Airlie 337673a394bSEric Anholt struct drm_i915_gem_init { 338673a394bSEric Anholt /** 339673a394bSEric Anholt * Beginning offset in the GTT to be managed by the DRM memory 340673a394bSEric Anholt * manager. 341673a394bSEric Anholt */ 3421d7f83d5SArnd Bergmann __u64 gtt_start; 343673a394bSEric Anholt /** 344673a394bSEric Anholt * Ending offset in the GTT to be managed by the DRM memory 345673a394bSEric Anholt * manager. 346673a394bSEric Anholt */ 3471d7f83d5SArnd Bergmann __u64 gtt_end; 348673a394bSEric Anholt }; 349673a394bSEric Anholt 350673a394bSEric Anholt struct drm_i915_gem_create { 351673a394bSEric Anholt /** 352673a394bSEric Anholt * Requested size for the object. 353673a394bSEric Anholt * 354673a394bSEric Anholt * The (page-aligned) allocated size for the object will be returned. 355673a394bSEric Anholt */ 3561d7f83d5SArnd Bergmann __u64 size; 357673a394bSEric Anholt /** 358673a394bSEric Anholt * Returned handle for the object. 359673a394bSEric Anholt * 360673a394bSEric Anholt * Object handles are nonzero. 361673a394bSEric Anholt */ 3621d7f83d5SArnd Bergmann __u32 handle; 3631d7f83d5SArnd Bergmann __u32 pad; 364673a394bSEric Anholt }; 365673a394bSEric Anholt 366673a394bSEric Anholt struct drm_i915_gem_pread { 367673a394bSEric Anholt /** Handle for the object being read. */ 3681d7f83d5SArnd Bergmann __u32 handle; 3691d7f83d5SArnd Bergmann __u32 pad; 370673a394bSEric Anholt /** Offset into the object to read from */ 3711d7f83d5SArnd Bergmann __u64 offset; 372673a394bSEric Anholt /** Length of data to read */ 3731d7f83d5SArnd Bergmann __u64 size; 374673a394bSEric Anholt /** 375673a394bSEric Anholt * Pointer to write the data into. 376673a394bSEric Anholt * 377673a394bSEric Anholt * This is a fixed-size type for 32/64 compatibility. 378673a394bSEric Anholt */ 3791d7f83d5SArnd Bergmann __u64 data_ptr; 380673a394bSEric Anholt }; 381673a394bSEric Anholt 382673a394bSEric Anholt struct drm_i915_gem_pwrite { 383673a394bSEric Anholt /** Handle for the object being written to. */ 3841d7f83d5SArnd Bergmann __u32 handle; 3851d7f83d5SArnd Bergmann __u32 pad; 386673a394bSEric Anholt /** Offset into the object to write to */ 3871d7f83d5SArnd Bergmann __u64 offset; 388673a394bSEric Anholt /** Length of data to write */ 3891d7f83d5SArnd Bergmann __u64 size; 390673a394bSEric Anholt /** 391673a394bSEric Anholt * Pointer to read the data from. 392673a394bSEric Anholt * 393673a394bSEric Anholt * This is a fixed-size type for 32/64 compatibility. 394673a394bSEric Anholt */ 3951d7f83d5SArnd Bergmann __u64 data_ptr; 396673a394bSEric Anholt }; 397673a394bSEric Anholt 398673a394bSEric Anholt struct drm_i915_gem_mmap { 399673a394bSEric Anholt /** Handle for the object being mapped. */ 4001d7f83d5SArnd Bergmann __u32 handle; 4011d7f83d5SArnd Bergmann __u32 pad; 402673a394bSEric Anholt /** Offset in the object to map. */ 4031d7f83d5SArnd Bergmann __u64 offset; 404673a394bSEric Anholt /** 405673a394bSEric Anholt * Length of data to map. 406673a394bSEric Anholt * 407673a394bSEric Anholt * The value will be page-aligned. 408673a394bSEric Anholt */ 4091d7f83d5SArnd Bergmann __u64 size; 410673a394bSEric Anholt /** 411673a394bSEric Anholt * Returned pointer the data was mapped at. 412673a394bSEric Anholt * 413673a394bSEric Anholt * This is a fixed-size type for 32/64 compatibility. 414673a394bSEric Anholt */ 4151d7f83d5SArnd Bergmann __u64 addr_ptr; 416673a394bSEric Anholt }; 417673a394bSEric Anholt 418de151cf6SJesse Barnes struct drm_i915_gem_mmap_gtt { 419de151cf6SJesse Barnes /** Handle for the object being mapped. */ 4201d7f83d5SArnd Bergmann __u32 handle; 4211d7f83d5SArnd Bergmann __u32 pad; 422de151cf6SJesse Barnes /** 423de151cf6SJesse Barnes * Fake offset to use for subsequent mmap call 424de151cf6SJesse Barnes * 425de151cf6SJesse Barnes * This is a fixed-size type for 32/64 compatibility. 426de151cf6SJesse Barnes */ 4271d7f83d5SArnd Bergmann __u64 offset; 428de151cf6SJesse Barnes }; 429de151cf6SJesse Barnes 430673a394bSEric Anholt struct drm_i915_gem_set_domain { 431673a394bSEric Anholt /** Handle for the object */ 4321d7f83d5SArnd Bergmann __u32 handle; 433673a394bSEric Anholt 434673a394bSEric Anholt /** New read domains */ 4351d7f83d5SArnd Bergmann __u32 read_domains; 436673a394bSEric Anholt 437673a394bSEric Anholt /** New write domain */ 4381d7f83d5SArnd Bergmann __u32 write_domain; 439673a394bSEric Anholt }; 440673a394bSEric Anholt 441673a394bSEric Anholt struct drm_i915_gem_sw_finish { 442673a394bSEric Anholt /** Handle for the object */ 4431d7f83d5SArnd Bergmann __u32 handle; 444673a394bSEric Anholt }; 445673a394bSEric Anholt 446673a394bSEric Anholt struct drm_i915_gem_relocation_entry { 447673a394bSEric Anholt /** 448673a394bSEric Anholt * Handle of the buffer being pointed to by this relocation entry. 449673a394bSEric Anholt * 450673a394bSEric Anholt * It's appealing to make this be an index into the mm_validate_entry 451673a394bSEric Anholt * list to refer to the buffer, but this allows the driver to create 452673a394bSEric Anholt * a relocation list for state buffers and not re-write it per 453673a394bSEric Anholt * exec using the buffer. 454673a394bSEric Anholt */ 4551d7f83d5SArnd Bergmann __u32 target_handle; 456673a394bSEric Anholt 457673a394bSEric Anholt /** 458673a394bSEric Anholt * Value to be added to the offset of the target buffer to make up 459673a394bSEric Anholt * the relocation entry. 460673a394bSEric Anholt */ 4611d7f83d5SArnd Bergmann __u32 delta; 462673a394bSEric Anholt 463673a394bSEric Anholt /** Offset in the buffer the relocation entry will be written into */ 4641d7f83d5SArnd Bergmann __u64 offset; 465673a394bSEric Anholt 466673a394bSEric Anholt /** 467673a394bSEric Anholt * Offset value of the target buffer that the relocation entry was last 468673a394bSEric Anholt * written as. 469673a394bSEric Anholt * 470673a394bSEric Anholt * If the buffer has the same offset as last time, we can skip syncing 471673a394bSEric Anholt * and writing the relocation. This value is written back out by 472673a394bSEric Anholt * the execbuffer ioctl when the relocation is written. 473673a394bSEric Anholt */ 4741d7f83d5SArnd Bergmann __u64 presumed_offset; 475673a394bSEric Anholt 476673a394bSEric Anholt /** 477673a394bSEric Anholt * Target memory domains read by this operation. 478673a394bSEric Anholt */ 4791d7f83d5SArnd Bergmann __u32 read_domains; 480673a394bSEric Anholt 481673a394bSEric Anholt /** 482673a394bSEric Anholt * Target memory domains written by this operation. 483673a394bSEric Anholt * 484673a394bSEric Anholt * Note that only one domain may be written by the whole 485673a394bSEric Anholt * execbuffer operation, so that where there are conflicts, 486673a394bSEric Anholt * the application will get -EINVAL back. 487673a394bSEric Anholt */ 4881d7f83d5SArnd Bergmann __u32 write_domain; 489673a394bSEric Anholt }; 490673a394bSEric Anholt 491673a394bSEric Anholt /** @{ 492673a394bSEric Anholt * Intel memory domains 493673a394bSEric Anholt * 494673a394bSEric Anholt * Most of these just align with the various caches in 495673a394bSEric Anholt * the system and are used to flush and invalidate as 496673a394bSEric Anholt * objects end up cached in different domains. 497673a394bSEric Anholt */ 498673a394bSEric Anholt /** CPU cache */ 499673a394bSEric Anholt #define I915_GEM_DOMAIN_CPU 0x00000001 500673a394bSEric Anholt /** Render cache, used by 2D and 3D drawing */ 501673a394bSEric Anholt #define I915_GEM_DOMAIN_RENDER 0x00000002 502673a394bSEric Anholt /** Sampler cache, used by texture engine */ 503673a394bSEric Anholt #define I915_GEM_DOMAIN_SAMPLER 0x00000004 504673a394bSEric Anholt /** Command queue, used to load batch buffers */ 505673a394bSEric Anholt #define I915_GEM_DOMAIN_COMMAND 0x00000008 506673a394bSEric Anholt /** Instruction cache, used by shader programs */ 507673a394bSEric Anholt #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 508673a394bSEric Anholt /** Vertex address cache */ 509673a394bSEric Anholt #define I915_GEM_DOMAIN_VERTEX 0x00000020 510673a394bSEric Anholt /** GTT domain - aperture and scanout */ 511673a394bSEric Anholt #define I915_GEM_DOMAIN_GTT 0x00000040 512673a394bSEric Anholt /** @} */ 513673a394bSEric Anholt 514673a394bSEric Anholt struct drm_i915_gem_exec_object { 515673a394bSEric Anholt /** 516673a394bSEric Anholt * User's handle for a buffer to be bound into the GTT for this 517673a394bSEric Anholt * operation. 518673a394bSEric Anholt */ 5191d7f83d5SArnd Bergmann __u32 handle; 520673a394bSEric Anholt 521673a394bSEric Anholt /** Number of relocations to be performed on this buffer */ 5221d7f83d5SArnd Bergmann __u32 relocation_count; 523673a394bSEric Anholt /** 524673a394bSEric Anholt * Pointer to array of struct drm_i915_gem_relocation_entry containing 525673a394bSEric Anholt * the relocations to be performed in this buffer. 526673a394bSEric Anholt */ 5271d7f83d5SArnd Bergmann __u64 relocs_ptr; 528673a394bSEric Anholt 529673a394bSEric Anholt /** Required alignment in graphics aperture */ 5301d7f83d5SArnd Bergmann __u64 alignment; 531673a394bSEric Anholt 532673a394bSEric Anholt /** 533673a394bSEric Anholt * Returned value of the updated offset of the object, for future 534673a394bSEric Anholt * presumed_offset writes. 535673a394bSEric Anholt */ 5361d7f83d5SArnd Bergmann __u64 offset; 537673a394bSEric Anholt }; 538673a394bSEric Anholt 539673a394bSEric Anholt struct drm_i915_gem_execbuffer { 540673a394bSEric Anholt /** 541673a394bSEric Anholt * List of buffers to be validated with their relocations to be 542673a394bSEric Anholt * performend on them. 543673a394bSEric Anholt * 544673a394bSEric Anholt * This is a pointer to an array of struct drm_i915_gem_validate_entry. 545673a394bSEric Anholt * 546673a394bSEric Anholt * These buffers must be listed in an order such that all relocations 547673a394bSEric Anholt * a buffer is performing refer to buffers that have already appeared 548673a394bSEric Anholt * in the validate list. 549673a394bSEric Anholt */ 5501d7f83d5SArnd Bergmann __u64 buffers_ptr; 5511d7f83d5SArnd Bergmann __u32 buffer_count; 552673a394bSEric Anholt 553673a394bSEric Anholt /** Offset in the batchbuffer to start execution from. */ 5541d7f83d5SArnd Bergmann __u32 batch_start_offset; 555673a394bSEric Anholt /** Bytes used in batchbuffer from batch_start_offset */ 5561d7f83d5SArnd Bergmann __u32 batch_len; 5571d7f83d5SArnd Bergmann __u32 DR1; 5581d7f83d5SArnd Bergmann __u32 DR4; 5591d7f83d5SArnd Bergmann __u32 num_cliprects; 560673a394bSEric Anholt /** This is a struct drm_clip_rect *cliprects */ 5611d7f83d5SArnd Bergmann __u64 cliprects_ptr; 562673a394bSEric Anholt }; 563673a394bSEric Anholt 564673a394bSEric Anholt struct drm_i915_gem_pin { 565673a394bSEric Anholt /** Handle of the buffer to be pinned. */ 5661d7f83d5SArnd Bergmann __u32 handle; 5671d7f83d5SArnd Bergmann __u32 pad; 568673a394bSEric Anholt 569673a394bSEric Anholt /** alignment required within the aperture */ 5701d7f83d5SArnd Bergmann __u64 alignment; 571673a394bSEric Anholt 572673a394bSEric Anholt /** Returned GTT offset of the buffer. */ 5731d7f83d5SArnd Bergmann __u64 offset; 574673a394bSEric Anholt }; 575673a394bSEric Anholt 576673a394bSEric Anholt struct drm_i915_gem_unpin { 577673a394bSEric Anholt /** Handle of the buffer to be unpinned. */ 5781d7f83d5SArnd Bergmann __u32 handle; 5791d7f83d5SArnd Bergmann __u32 pad; 580673a394bSEric Anholt }; 581673a394bSEric Anholt 582673a394bSEric Anholt struct drm_i915_gem_busy { 583673a394bSEric Anholt /** Handle of the buffer to check for busy */ 5841d7f83d5SArnd Bergmann __u32 handle; 585673a394bSEric Anholt 586673a394bSEric Anholt /** Return busy status (1 if busy, 0 if idle) */ 5871d7f83d5SArnd Bergmann __u32 busy; 588673a394bSEric Anholt }; 589673a394bSEric Anholt 590673a394bSEric Anholt #define I915_TILING_NONE 0 591673a394bSEric Anholt #define I915_TILING_X 1 592673a394bSEric Anholt #define I915_TILING_Y 2 593673a394bSEric Anholt 594673a394bSEric Anholt #define I915_BIT_6_SWIZZLE_NONE 0 595673a394bSEric Anholt #define I915_BIT_6_SWIZZLE_9 1 596673a394bSEric Anholt #define I915_BIT_6_SWIZZLE_9_10 2 597673a394bSEric Anholt #define I915_BIT_6_SWIZZLE_9_11 3 598673a394bSEric Anholt #define I915_BIT_6_SWIZZLE_9_10_11 4 599673a394bSEric Anholt /* Not seen by userland */ 600673a394bSEric Anholt #define I915_BIT_6_SWIZZLE_UNKNOWN 5 601280b713bSEric Anholt /* Seen by userland. */ 602280b713bSEric Anholt #define I915_BIT_6_SWIZZLE_9_17 6 603280b713bSEric Anholt #define I915_BIT_6_SWIZZLE_9_10_17 7 604673a394bSEric Anholt 605673a394bSEric Anholt struct drm_i915_gem_set_tiling { 606673a394bSEric Anholt /** Handle of the buffer to have its tiling state updated */ 6071d7f83d5SArnd Bergmann __u32 handle; 608673a394bSEric Anholt 609673a394bSEric Anholt /** 610673a394bSEric Anholt * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 611673a394bSEric Anholt * I915_TILING_Y). 612673a394bSEric Anholt * 613673a394bSEric Anholt * This value is to be set on request, and will be updated by the 614673a394bSEric Anholt * kernel on successful return with the actual chosen tiling layout. 615673a394bSEric Anholt * 616673a394bSEric Anholt * The tiling mode may be demoted to I915_TILING_NONE when the system 617673a394bSEric Anholt * has bit 6 swizzling that can't be managed correctly by GEM. 618673a394bSEric Anholt * 619673a394bSEric Anholt * Buffer contents become undefined when changing tiling_mode. 620673a394bSEric Anholt */ 6211d7f83d5SArnd Bergmann __u32 tiling_mode; 622673a394bSEric Anholt 623673a394bSEric Anholt /** 624673a394bSEric Anholt * Stride in bytes for the object when in I915_TILING_X or 625673a394bSEric Anholt * I915_TILING_Y. 626673a394bSEric Anholt */ 6271d7f83d5SArnd Bergmann __u32 stride; 628673a394bSEric Anholt 629673a394bSEric Anholt /** 630673a394bSEric Anholt * Returned address bit 6 swizzling required for CPU access through 631673a394bSEric Anholt * mmap mapping. 632673a394bSEric Anholt */ 6331d7f83d5SArnd Bergmann __u32 swizzle_mode; 634673a394bSEric Anholt }; 635673a394bSEric Anholt 636673a394bSEric Anholt struct drm_i915_gem_get_tiling { 637673a394bSEric Anholt /** Handle of the buffer to get tiling state for. */ 6381d7f83d5SArnd Bergmann __u32 handle; 639673a394bSEric Anholt 640673a394bSEric Anholt /** 641673a394bSEric Anholt * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 642673a394bSEric Anholt * I915_TILING_Y). 643673a394bSEric Anholt */ 6441d7f83d5SArnd Bergmann __u32 tiling_mode; 645673a394bSEric Anholt 646673a394bSEric Anholt /** 647673a394bSEric Anholt * Returned address bit 6 swizzling required for CPU access through 648673a394bSEric Anholt * mmap mapping. 649673a394bSEric Anholt */ 6501d7f83d5SArnd Bergmann __u32 swizzle_mode; 651673a394bSEric Anholt }; 652673a394bSEric Anholt 6535a125c3cSEric Anholt struct drm_i915_gem_get_aperture { 6545a125c3cSEric Anholt /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 6551d7f83d5SArnd Bergmann __u64 aper_size; 6565a125c3cSEric Anholt 6575a125c3cSEric Anholt /** 6585a125c3cSEric Anholt * Available space in the aperture used by i915_gem_execbuffer, in 6595a125c3cSEric Anholt * bytes 6605a125c3cSEric Anholt */ 6611d7f83d5SArnd Bergmann __u64 aper_available_size; 6625a125c3cSEric Anholt }; 6635a125c3cSEric Anholt 66408d7b3d1SCarl Worth struct drm_i915_get_pipe_from_crtc_id { 66508d7b3d1SCarl Worth /** ID of CRTC being requested **/ 66608d7b3d1SCarl Worth __u32 crtc_id; 66708d7b3d1SCarl Worth 66808d7b3d1SCarl Worth /** pipe of requested CRTC **/ 66908d7b3d1SCarl Worth __u32 pipe; 67008d7b3d1SCarl Worth }; 67108d7b3d1SCarl Worth 6723ef94daaSChris Wilson #define I915_MADV_WILLNEED 0 6733ef94daaSChris Wilson #define I915_MADV_DONTNEED 1 674bb6baf76SChris Wilson #define __I915_MADV_PURGED 2 /* internal state */ 6753ef94daaSChris Wilson 6763ef94daaSChris Wilson struct drm_i915_gem_madvise { 6773ef94daaSChris Wilson /** Handle of the buffer to change the backing store advice */ 6783ef94daaSChris Wilson __u32 handle; 6793ef94daaSChris Wilson 6803ef94daaSChris Wilson /* Advice: either the buffer will be needed again in the near future, 6813ef94daaSChris Wilson * or wont be and could be discarded under memory pressure. 6823ef94daaSChris Wilson */ 6833ef94daaSChris Wilson __u32 madv; 6843ef94daaSChris Wilson 6853ef94daaSChris Wilson /** Whether the backing store still exists. */ 6863ef94daaSChris Wilson __u32 retained; 6873ef94daaSChris Wilson }; 6883ef94daaSChris Wilson 689c0e09200SDave Airlie #endif /* _I915_DRM_H_ */ 690