1c0e09200SDave Airlie /* 2c0e09200SDave Airlie * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3c0e09200SDave Airlie * All Rights Reserved. 4c0e09200SDave Airlie * 5c0e09200SDave Airlie * Permission is hereby granted, free of charge, to any person obtaining a 6c0e09200SDave Airlie * copy of this software and associated documentation files (the 7c0e09200SDave Airlie * "Software"), to deal in the Software without restriction, including 8c0e09200SDave Airlie * without limitation the rights to use, copy, modify, merge, publish, 9c0e09200SDave Airlie * distribute, sub license, and/or sell copies of the Software, and to 10c0e09200SDave Airlie * permit persons to whom the Software is furnished to do so, subject to 11c0e09200SDave Airlie * the following conditions: 12c0e09200SDave Airlie * 13c0e09200SDave Airlie * The above copyright notice and this permission notice (including the 14c0e09200SDave Airlie * next paragraph) shall be included in all copies or substantial portions 15c0e09200SDave Airlie * of the Software. 16c0e09200SDave Airlie * 17c0e09200SDave Airlie * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18c0e09200SDave Airlie * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19c0e09200SDave Airlie * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20c0e09200SDave Airlie * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21c0e09200SDave Airlie * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22c0e09200SDave Airlie * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23c0e09200SDave Airlie * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24c0e09200SDave Airlie * 25c0e09200SDave Airlie */ 26c0e09200SDave Airlie 27c0e09200SDave Airlie #ifndef _I915_DRM_H_ 28c0e09200SDave Airlie #define _I915_DRM_H_ 29c0e09200SDave Airlie 301a95916fSKristian Høgsberg #include "drm.h" 311a95916fSKristian Høgsberg 32c0e09200SDave Airlie /* Please note that modifications to all structs defined here are 33c0e09200SDave Airlie * subject to backwards-compatibility constraints. 34c0e09200SDave Airlie */ 35c0e09200SDave Airlie 36aa7ffc01SJesse Barnes #ifdef __KERNEL__ 37aa7ffc01SJesse Barnes /* For use by IPS driver */ 38aa7ffc01SJesse Barnes extern unsigned long i915_read_mch_val(void); 39aa7ffc01SJesse Barnes extern bool i915_gpu_raise(void); 40aa7ffc01SJesse Barnes extern bool i915_gpu_lower(void); 41aa7ffc01SJesse Barnes extern bool i915_gpu_busy(void); 42aa7ffc01SJesse Barnes extern bool i915_gpu_turbo_disable(void); 43aa7ffc01SJesse Barnes #endif 44aa7ffc01SJesse Barnes 45c0e09200SDave Airlie /* Each region is a minimum of 16k, and there are at most 255 of them. 46c0e09200SDave Airlie */ 47c0e09200SDave Airlie #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 48c0e09200SDave Airlie * of chars for next/prev indices */ 49c0e09200SDave Airlie #define I915_LOG_MIN_TEX_REGION_SIZE 14 50c0e09200SDave Airlie 51c0e09200SDave Airlie typedef struct _drm_i915_init { 52c0e09200SDave Airlie enum { 53c0e09200SDave Airlie I915_INIT_DMA = 0x01, 54c0e09200SDave Airlie I915_CLEANUP_DMA = 0x02, 55c0e09200SDave Airlie I915_RESUME_DMA = 0x03 56c0e09200SDave Airlie } func; 57c0e09200SDave Airlie unsigned int mmio_offset; 58c0e09200SDave Airlie int sarea_priv_offset; 59c0e09200SDave Airlie unsigned int ring_start; 60c0e09200SDave Airlie unsigned int ring_end; 61c0e09200SDave Airlie unsigned int ring_size; 62c0e09200SDave Airlie unsigned int front_offset; 63c0e09200SDave Airlie unsigned int back_offset; 64c0e09200SDave Airlie unsigned int depth_offset; 65c0e09200SDave Airlie unsigned int w; 66c0e09200SDave Airlie unsigned int h; 67c0e09200SDave Airlie unsigned int pitch; 68c0e09200SDave Airlie unsigned int pitch_bits; 69c0e09200SDave Airlie unsigned int back_pitch; 70c0e09200SDave Airlie unsigned int depth_pitch; 71c0e09200SDave Airlie unsigned int cpp; 72c0e09200SDave Airlie unsigned int chipset; 73c0e09200SDave Airlie } drm_i915_init_t; 74c0e09200SDave Airlie 75c0e09200SDave Airlie typedef struct _drm_i915_sarea { 76c0e09200SDave Airlie struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 77c0e09200SDave Airlie int last_upload; /* last time texture was uploaded */ 78c0e09200SDave Airlie int last_enqueue; /* last time a buffer was enqueued */ 79c0e09200SDave Airlie int last_dispatch; /* age of the most recently dispatched buffer */ 80c0e09200SDave Airlie int ctxOwner; /* last context to upload state */ 81c0e09200SDave Airlie int texAge; 82c0e09200SDave Airlie int pf_enabled; /* is pageflipping allowed? */ 83c0e09200SDave Airlie int pf_active; 84c0e09200SDave Airlie int pf_current_page; /* which buffer is being displayed? */ 85c0e09200SDave Airlie int perf_boxes; /* performance boxes to be displayed */ 86c0e09200SDave Airlie int width, height; /* screen size in pixels */ 87c0e09200SDave Airlie 88c0e09200SDave Airlie drm_handle_t front_handle; 89c0e09200SDave Airlie int front_offset; 90c0e09200SDave Airlie int front_size; 91c0e09200SDave Airlie 92c0e09200SDave Airlie drm_handle_t back_handle; 93c0e09200SDave Airlie int back_offset; 94c0e09200SDave Airlie int back_size; 95c0e09200SDave Airlie 96c0e09200SDave Airlie drm_handle_t depth_handle; 97c0e09200SDave Airlie int depth_offset; 98c0e09200SDave Airlie int depth_size; 99c0e09200SDave Airlie 100c0e09200SDave Airlie drm_handle_t tex_handle; 101c0e09200SDave Airlie int tex_offset; 102c0e09200SDave Airlie int tex_size; 103c0e09200SDave Airlie int log_tex_granularity; 104c0e09200SDave Airlie int pitch; 105c0e09200SDave Airlie int rotation; /* 0, 90, 180 or 270 */ 106c0e09200SDave Airlie int rotated_offset; 107c0e09200SDave Airlie int rotated_size; 108c0e09200SDave Airlie int rotated_pitch; 109c0e09200SDave Airlie int virtualX, virtualY; 110c0e09200SDave Airlie 111c0e09200SDave Airlie unsigned int front_tiled; 112c0e09200SDave Airlie unsigned int back_tiled; 113c0e09200SDave Airlie unsigned int depth_tiled; 114c0e09200SDave Airlie unsigned int rotated_tiled; 115c0e09200SDave Airlie unsigned int rotated2_tiled; 116c0e09200SDave Airlie 117c0e09200SDave Airlie int pipeA_x; 118c0e09200SDave Airlie int pipeA_y; 119c0e09200SDave Airlie int pipeA_w; 120c0e09200SDave Airlie int pipeA_h; 121c0e09200SDave Airlie int pipeB_x; 122c0e09200SDave Airlie int pipeB_y; 123c0e09200SDave Airlie int pipeB_w; 124c0e09200SDave Airlie int pipeB_h; 125dfef2459SDave Airlie 126dfef2459SDave Airlie /* fill out some space for old userspace triple buffer */ 127dfef2459SDave Airlie drm_handle_t unused_handle; 1281d7f83d5SArnd Bergmann __u32 unused1, unused2, unused3; 129dfef2459SDave Airlie 130dfef2459SDave Airlie /* buffer object handles for static buffers. May change 131dfef2459SDave Airlie * over the lifetime of the client. 132dfef2459SDave Airlie */ 1331d7f83d5SArnd Bergmann __u32 front_bo_handle; 1341d7f83d5SArnd Bergmann __u32 back_bo_handle; 1351d7f83d5SArnd Bergmann __u32 unused_bo_handle; 1361d7f83d5SArnd Bergmann __u32 depth_bo_handle; 137dfef2459SDave Airlie 138c0e09200SDave Airlie } drm_i915_sarea_t; 139c0e09200SDave Airlie 140dfef2459SDave Airlie /* due to userspace building against these headers we need some compat here */ 141dfef2459SDave Airlie #define planeA_x pipeA_x 142dfef2459SDave Airlie #define planeA_y pipeA_y 143dfef2459SDave Airlie #define planeA_w pipeA_w 144dfef2459SDave Airlie #define planeA_h pipeA_h 145dfef2459SDave Airlie #define planeB_x pipeB_x 146dfef2459SDave Airlie #define planeB_y pipeB_y 147dfef2459SDave Airlie #define planeB_w pipeB_w 148dfef2459SDave Airlie #define planeB_h pipeB_h 149dfef2459SDave Airlie 150c0e09200SDave Airlie /* Flags for perf_boxes 151c0e09200SDave Airlie */ 152c0e09200SDave Airlie #define I915_BOX_RING_EMPTY 0x1 153c0e09200SDave Airlie #define I915_BOX_FLIP 0x2 154c0e09200SDave Airlie #define I915_BOX_WAIT 0x4 155c0e09200SDave Airlie #define I915_BOX_TEXTURE_LOAD 0x8 156c0e09200SDave Airlie #define I915_BOX_LOST_CONTEXT 0x10 157c0e09200SDave Airlie 158c0e09200SDave Airlie /* I915 specific ioctls 159c0e09200SDave Airlie * The device specific ioctl range is 0x40 to 0x79. 160c0e09200SDave Airlie */ 161c0e09200SDave Airlie #define DRM_I915_INIT 0x00 162c0e09200SDave Airlie #define DRM_I915_FLUSH 0x01 163c0e09200SDave Airlie #define DRM_I915_FLIP 0x02 164c0e09200SDave Airlie #define DRM_I915_BATCHBUFFER 0x03 165c0e09200SDave Airlie #define DRM_I915_IRQ_EMIT 0x04 166c0e09200SDave Airlie #define DRM_I915_IRQ_WAIT 0x05 167c0e09200SDave Airlie #define DRM_I915_GETPARAM 0x06 168c0e09200SDave Airlie #define DRM_I915_SETPARAM 0x07 169c0e09200SDave Airlie #define DRM_I915_ALLOC 0x08 170c0e09200SDave Airlie #define DRM_I915_FREE 0x09 171c0e09200SDave Airlie #define DRM_I915_INIT_HEAP 0x0a 172c0e09200SDave Airlie #define DRM_I915_CMDBUFFER 0x0b 173c0e09200SDave Airlie #define DRM_I915_DESTROY_HEAP 0x0c 174c0e09200SDave Airlie #define DRM_I915_SET_VBLANK_PIPE 0x0d 175c0e09200SDave Airlie #define DRM_I915_GET_VBLANK_PIPE 0x0e 176c0e09200SDave Airlie #define DRM_I915_VBLANK_SWAP 0x0f 177c0e09200SDave Airlie #define DRM_I915_HWS_ADDR 0x11 178673a394bSEric Anholt #define DRM_I915_GEM_INIT 0x13 179673a394bSEric Anholt #define DRM_I915_GEM_EXECBUFFER 0x14 180673a394bSEric Anholt #define DRM_I915_GEM_PIN 0x15 181673a394bSEric Anholt #define DRM_I915_GEM_UNPIN 0x16 182673a394bSEric Anholt #define DRM_I915_GEM_BUSY 0x17 183673a394bSEric Anholt #define DRM_I915_GEM_THROTTLE 0x18 184673a394bSEric Anholt #define DRM_I915_GEM_ENTERVT 0x19 185673a394bSEric Anholt #define DRM_I915_GEM_LEAVEVT 0x1a 186673a394bSEric Anholt #define DRM_I915_GEM_CREATE 0x1b 187673a394bSEric Anholt #define DRM_I915_GEM_PREAD 0x1c 188673a394bSEric Anholt #define DRM_I915_GEM_PWRITE 0x1d 189673a394bSEric Anholt #define DRM_I915_GEM_MMAP 0x1e 190673a394bSEric Anholt #define DRM_I915_GEM_SET_DOMAIN 0x1f 191673a394bSEric Anholt #define DRM_I915_GEM_SW_FINISH 0x20 192673a394bSEric Anholt #define DRM_I915_GEM_SET_TILING 0x21 193673a394bSEric Anholt #define DRM_I915_GEM_GET_TILING 0x22 1945a125c3cSEric Anholt #define DRM_I915_GEM_GET_APERTURE 0x23 195de151cf6SJesse Barnes #define DRM_I915_GEM_MMAP_GTT 0x24 19608d7b3d1SCarl Worth #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 1973ef94daaSChris Wilson #define DRM_I915_GEM_MADVISE 0x26 19802e792fbSDaniel Vetter #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 19902e792fbSDaniel Vetter #define DRM_I915_OVERLAY_ATTRS 0x28 20076446cacSJesse Barnes #define DRM_I915_GEM_EXECBUFFER2 0x29 201c0e09200SDave Airlie 202c0e09200SDave Airlie #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 203c0e09200SDave Airlie #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 204c0e09200SDave Airlie #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 205c0e09200SDave Airlie #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 206c0e09200SDave Airlie #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 207c0e09200SDave Airlie #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 208c0e09200SDave Airlie #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 209c0e09200SDave Airlie #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 210c0e09200SDave Airlie #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 211c0e09200SDave Airlie #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 212c0e09200SDave Airlie #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 213c0e09200SDave Airlie #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 214c0e09200SDave Airlie #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 215c0e09200SDave Airlie #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 216c0e09200SDave Airlie #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 217c0e09200SDave Airlie #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 2188d391aa4SEric Anholt #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 2198d391aa4SEric Anholt #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 22076446cacSJesse Barnes #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 221673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 222673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 223673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 224673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 225673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 226673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 227673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 228673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 229673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 230673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 231de151cf6SJesse Barnes #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 232673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 233673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 234673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 235673a394bSEric Anholt #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 2365a125c3cSEric Anholt #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 23704b2d218SKristian Høgsberg #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 2383ef94daaSChris Wilson #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 23902e792fbSDaniel Vetter #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_ATTRS, struct drm_intel_overlay_put_image) 24002e792fbSDaniel Vetter #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 241c0e09200SDave Airlie 242c0e09200SDave Airlie /* Allow drivers to submit batchbuffers directly to hardware, relying 243c0e09200SDave Airlie * on the security mechanisms provided by hardware. 244c0e09200SDave Airlie */ 24579e53945SJesse Barnes typedef struct drm_i915_batchbuffer { 246c0e09200SDave Airlie int start; /* agp offset */ 247c0e09200SDave Airlie int used; /* nr bytes in use */ 248c0e09200SDave Airlie int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 249c0e09200SDave Airlie int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 250c0e09200SDave Airlie int num_cliprects; /* mulitpass with multiple cliprects? */ 251c0e09200SDave Airlie struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 252c0e09200SDave Airlie } drm_i915_batchbuffer_t; 253c0e09200SDave Airlie 254c0e09200SDave Airlie /* As above, but pass a pointer to userspace buffer which can be 255c0e09200SDave Airlie * validated by the kernel prior to sending to hardware. 256c0e09200SDave Airlie */ 257c0e09200SDave Airlie typedef struct _drm_i915_cmdbuffer { 258c0e09200SDave Airlie char __user *buf; /* pointer to userspace command buffer */ 259c0e09200SDave Airlie int sz; /* nr bytes in buf */ 260c0e09200SDave Airlie int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 261c0e09200SDave Airlie int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 262c0e09200SDave Airlie int num_cliprects; /* mulitpass with multiple cliprects? */ 263c0e09200SDave Airlie struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 264c0e09200SDave Airlie } drm_i915_cmdbuffer_t; 265c0e09200SDave Airlie 266c0e09200SDave Airlie /* Userspace can request & wait on irq's: 267c0e09200SDave Airlie */ 268c0e09200SDave Airlie typedef struct drm_i915_irq_emit { 269c0e09200SDave Airlie int __user *irq_seq; 270c0e09200SDave Airlie } drm_i915_irq_emit_t; 271c0e09200SDave Airlie 272c0e09200SDave Airlie typedef struct drm_i915_irq_wait { 273c0e09200SDave Airlie int irq_seq; 274c0e09200SDave Airlie } drm_i915_irq_wait_t; 275c0e09200SDave Airlie 276c0e09200SDave Airlie /* Ioctl to query kernel params: 277c0e09200SDave Airlie */ 278c0e09200SDave Airlie #define I915_PARAM_IRQ_ACTIVE 1 279c0e09200SDave Airlie #define I915_PARAM_ALLOW_BATCHBUFFER 2 280c0e09200SDave Airlie #define I915_PARAM_LAST_DISPATCH 3 281ed4c9c4aSKristian Høgsberg #define I915_PARAM_CHIPSET_ID 4 282673a394bSEric Anholt #define I915_PARAM_HAS_GEM 5 2830f973f27SJesse Barnes #define I915_PARAM_NUM_FENCES_AVAIL 6 28402e792fbSDaniel Vetter #define I915_PARAM_HAS_OVERLAY 7 285e9560f7cSJesse Barnes #define I915_PARAM_HAS_PAGEFLIPPING 8 28676446cacSJesse Barnes #define I915_PARAM_HAS_EXECBUF2 9 287e3a815fcSZou Nan hai #define I915_PARAM_HAS_BSD 10 288c0e09200SDave Airlie 289c0e09200SDave Airlie typedef struct drm_i915_getparam { 290c0e09200SDave Airlie int param; 291c0e09200SDave Airlie int __user *value; 292c0e09200SDave Airlie } drm_i915_getparam_t; 293c0e09200SDave Airlie 294c0e09200SDave Airlie /* Ioctl to set kernel params: 295c0e09200SDave Airlie */ 296c0e09200SDave Airlie #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 297c0e09200SDave Airlie #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 298c0e09200SDave Airlie #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 2990f973f27SJesse Barnes #define I915_SETPARAM_NUM_USED_FENCES 4 300c0e09200SDave Airlie 301c0e09200SDave Airlie typedef struct drm_i915_setparam { 302c0e09200SDave Airlie int param; 303c0e09200SDave Airlie int value; 304c0e09200SDave Airlie } drm_i915_setparam_t; 305c0e09200SDave Airlie 306c0e09200SDave Airlie /* A memory manager for regions of shared memory: 307c0e09200SDave Airlie */ 308c0e09200SDave Airlie #define I915_MEM_REGION_AGP 1 309c0e09200SDave Airlie 310c0e09200SDave Airlie typedef struct drm_i915_mem_alloc { 311c0e09200SDave Airlie int region; 312c0e09200SDave Airlie int alignment; 313c0e09200SDave Airlie int size; 314c0e09200SDave Airlie int __user *region_offset; /* offset from start of fb or agp */ 315c0e09200SDave Airlie } drm_i915_mem_alloc_t; 316c0e09200SDave Airlie 317c0e09200SDave Airlie typedef struct drm_i915_mem_free { 318c0e09200SDave Airlie int region; 319c0e09200SDave Airlie int region_offset; 320c0e09200SDave Airlie } drm_i915_mem_free_t; 321c0e09200SDave Airlie 322c0e09200SDave Airlie typedef struct drm_i915_mem_init_heap { 323c0e09200SDave Airlie int region; 324c0e09200SDave Airlie int size; 325c0e09200SDave Airlie int start; 326c0e09200SDave Airlie } drm_i915_mem_init_heap_t; 327c0e09200SDave Airlie 328c0e09200SDave Airlie /* Allow memory manager to be torn down and re-initialized (eg on 329c0e09200SDave Airlie * rotate): 330c0e09200SDave Airlie */ 331c0e09200SDave Airlie typedef struct drm_i915_mem_destroy_heap { 332c0e09200SDave Airlie int region; 333c0e09200SDave Airlie } drm_i915_mem_destroy_heap_t; 334c0e09200SDave Airlie 335c0e09200SDave Airlie /* Allow X server to configure which pipes to monitor for vblank signals 336c0e09200SDave Airlie */ 337c0e09200SDave Airlie #define DRM_I915_VBLANK_PIPE_A 1 338c0e09200SDave Airlie #define DRM_I915_VBLANK_PIPE_B 2 339c0e09200SDave Airlie 340c0e09200SDave Airlie typedef struct drm_i915_vblank_pipe { 341c0e09200SDave Airlie int pipe; 342c0e09200SDave Airlie } drm_i915_vblank_pipe_t; 343c0e09200SDave Airlie 344c0e09200SDave Airlie /* Schedule buffer swap at given vertical blank: 345c0e09200SDave Airlie */ 346c0e09200SDave Airlie typedef struct drm_i915_vblank_swap { 347c0e09200SDave Airlie drm_drawable_t drawable; 348c0e09200SDave Airlie enum drm_vblank_seq_type seqtype; 349c0e09200SDave Airlie unsigned int sequence; 350c0e09200SDave Airlie } drm_i915_vblank_swap_t; 351c0e09200SDave Airlie 352c0e09200SDave Airlie typedef struct drm_i915_hws_addr { 3531d7f83d5SArnd Bergmann __u64 addr; 354c0e09200SDave Airlie } drm_i915_hws_addr_t; 355c0e09200SDave Airlie 356673a394bSEric Anholt struct drm_i915_gem_init { 357673a394bSEric Anholt /** 358673a394bSEric Anholt * Beginning offset in the GTT to be managed by the DRM memory 359673a394bSEric Anholt * manager. 360673a394bSEric Anholt */ 3611d7f83d5SArnd Bergmann __u64 gtt_start; 362673a394bSEric Anholt /** 363673a394bSEric Anholt * Ending offset in the GTT to be managed by the DRM memory 364673a394bSEric Anholt * manager. 365673a394bSEric Anholt */ 3661d7f83d5SArnd Bergmann __u64 gtt_end; 367673a394bSEric Anholt }; 368673a394bSEric Anholt 369673a394bSEric Anholt struct drm_i915_gem_create { 370673a394bSEric Anholt /** 371673a394bSEric Anholt * Requested size for the object. 372673a394bSEric Anholt * 373673a394bSEric Anholt * The (page-aligned) allocated size for the object will be returned. 374673a394bSEric Anholt */ 3751d7f83d5SArnd Bergmann __u64 size; 376673a394bSEric Anholt /** 377673a394bSEric Anholt * Returned handle for the object. 378673a394bSEric Anholt * 379673a394bSEric Anholt * Object handles are nonzero. 380673a394bSEric Anholt */ 3811d7f83d5SArnd Bergmann __u32 handle; 3821d7f83d5SArnd Bergmann __u32 pad; 383673a394bSEric Anholt }; 384673a394bSEric Anholt 385673a394bSEric Anholt struct drm_i915_gem_pread { 386673a394bSEric Anholt /** Handle for the object being read. */ 3871d7f83d5SArnd Bergmann __u32 handle; 3881d7f83d5SArnd Bergmann __u32 pad; 389673a394bSEric Anholt /** Offset into the object to read from */ 3901d7f83d5SArnd Bergmann __u64 offset; 391673a394bSEric Anholt /** Length of data to read */ 3921d7f83d5SArnd Bergmann __u64 size; 393673a394bSEric Anholt /** 394673a394bSEric Anholt * Pointer to write the data into. 395673a394bSEric Anholt * 396673a394bSEric Anholt * This is a fixed-size type for 32/64 compatibility. 397673a394bSEric Anholt */ 3981d7f83d5SArnd Bergmann __u64 data_ptr; 399673a394bSEric Anholt }; 400673a394bSEric Anholt 401673a394bSEric Anholt struct drm_i915_gem_pwrite { 402673a394bSEric Anholt /** Handle for the object being written to. */ 4031d7f83d5SArnd Bergmann __u32 handle; 4041d7f83d5SArnd Bergmann __u32 pad; 405673a394bSEric Anholt /** Offset into the object to write to */ 4061d7f83d5SArnd Bergmann __u64 offset; 407673a394bSEric Anholt /** Length of data to write */ 4081d7f83d5SArnd Bergmann __u64 size; 409673a394bSEric Anholt /** 410673a394bSEric Anholt * Pointer to read the data from. 411673a394bSEric Anholt * 412673a394bSEric Anholt * This is a fixed-size type for 32/64 compatibility. 413673a394bSEric Anholt */ 4141d7f83d5SArnd Bergmann __u64 data_ptr; 415673a394bSEric Anholt }; 416673a394bSEric Anholt 417673a394bSEric Anholt struct drm_i915_gem_mmap { 418673a394bSEric Anholt /** Handle for the object being mapped. */ 4191d7f83d5SArnd Bergmann __u32 handle; 4201d7f83d5SArnd Bergmann __u32 pad; 421673a394bSEric Anholt /** Offset in the object to map. */ 4221d7f83d5SArnd Bergmann __u64 offset; 423673a394bSEric Anholt /** 424673a394bSEric Anholt * Length of data to map. 425673a394bSEric Anholt * 426673a394bSEric Anholt * The value will be page-aligned. 427673a394bSEric Anholt */ 4281d7f83d5SArnd Bergmann __u64 size; 429673a394bSEric Anholt /** 430673a394bSEric Anholt * Returned pointer the data was mapped at. 431673a394bSEric Anholt * 432673a394bSEric Anholt * This is a fixed-size type for 32/64 compatibility. 433673a394bSEric Anholt */ 4341d7f83d5SArnd Bergmann __u64 addr_ptr; 435673a394bSEric Anholt }; 436673a394bSEric Anholt 437de151cf6SJesse Barnes struct drm_i915_gem_mmap_gtt { 438de151cf6SJesse Barnes /** Handle for the object being mapped. */ 4391d7f83d5SArnd Bergmann __u32 handle; 4401d7f83d5SArnd Bergmann __u32 pad; 441de151cf6SJesse Barnes /** 442de151cf6SJesse Barnes * Fake offset to use for subsequent mmap call 443de151cf6SJesse Barnes * 444de151cf6SJesse Barnes * This is a fixed-size type for 32/64 compatibility. 445de151cf6SJesse Barnes */ 4461d7f83d5SArnd Bergmann __u64 offset; 447de151cf6SJesse Barnes }; 448de151cf6SJesse Barnes 449673a394bSEric Anholt struct drm_i915_gem_set_domain { 450673a394bSEric Anholt /** Handle for the object */ 4511d7f83d5SArnd Bergmann __u32 handle; 452673a394bSEric Anholt 453673a394bSEric Anholt /** New read domains */ 4541d7f83d5SArnd Bergmann __u32 read_domains; 455673a394bSEric Anholt 456673a394bSEric Anholt /** New write domain */ 4571d7f83d5SArnd Bergmann __u32 write_domain; 458673a394bSEric Anholt }; 459673a394bSEric Anholt 460673a394bSEric Anholt struct drm_i915_gem_sw_finish { 461673a394bSEric Anholt /** Handle for the object */ 4621d7f83d5SArnd Bergmann __u32 handle; 463673a394bSEric Anholt }; 464673a394bSEric Anholt 465673a394bSEric Anholt struct drm_i915_gem_relocation_entry { 466673a394bSEric Anholt /** 467673a394bSEric Anholt * Handle of the buffer being pointed to by this relocation entry. 468673a394bSEric Anholt * 469673a394bSEric Anholt * It's appealing to make this be an index into the mm_validate_entry 470673a394bSEric Anholt * list to refer to the buffer, but this allows the driver to create 471673a394bSEric Anholt * a relocation list for state buffers and not re-write it per 472673a394bSEric Anholt * exec using the buffer. 473673a394bSEric Anholt */ 4741d7f83d5SArnd Bergmann __u32 target_handle; 475673a394bSEric Anholt 476673a394bSEric Anholt /** 477673a394bSEric Anholt * Value to be added to the offset of the target buffer to make up 478673a394bSEric Anholt * the relocation entry. 479673a394bSEric Anholt */ 4801d7f83d5SArnd Bergmann __u32 delta; 481673a394bSEric Anholt 482673a394bSEric Anholt /** Offset in the buffer the relocation entry will be written into */ 4831d7f83d5SArnd Bergmann __u64 offset; 484673a394bSEric Anholt 485673a394bSEric Anholt /** 486673a394bSEric Anholt * Offset value of the target buffer that the relocation entry was last 487673a394bSEric Anholt * written as. 488673a394bSEric Anholt * 489673a394bSEric Anholt * If the buffer has the same offset as last time, we can skip syncing 490673a394bSEric Anholt * and writing the relocation. This value is written back out by 491673a394bSEric Anholt * the execbuffer ioctl when the relocation is written. 492673a394bSEric Anholt */ 4931d7f83d5SArnd Bergmann __u64 presumed_offset; 494673a394bSEric Anholt 495673a394bSEric Anholt /** 496673a394bSEric Anholt * Target memory domains read by this operation. 497673a394bSEric Anholt */ 4981d7f83d5SArnd Bergmann __u32 read_domains; 499673a394bSEric Anholt 500673a394bSEric Anholt /** 501673a394bSEric Anholt * Target memory domains written by this operation. 502673a394bSEric Anholt * 503673a394bSEric Anholt * Note that only one domain may be written by the whole 504673a394bSEric Anholt * execbuffer operation, so that where there are conflicts, 505673a394bSEric Anholt * the application will get -EINVAL back. 506673a394bSEric Anholt */ 5071d7f83d5SArnd Bergmann __u32 write_domain; 508673a394bSEric Anholt }; 509673a394bSEric Anholt 510673a394bSEric Anholt /** @{ 511673a394bSEric Anholt * Intel memory domains 512673a394bSEric Anholt * 513673a394bSEric Anholt * Most of these just align with the various caches in 514673a394bSEric Anholt * the system and are used to flush and invalidate as 515673a394bSEric Anholt * objects end up cached in different domains. 516673a394bSEric Anholt */ 517673a394bSEric Anholt /** CPU cache */ 518673a394bSEric Anholt #define I915_GEM_DOMAIN_CPU 0x00000001 519673a394bSEric Anholt /** Render cache, used by 2D and 3D drawing */ 520673a394bSEric Anholt #define I915_GEM_DOMAIN_RENDER 0x00000002 521673a394bSEric Anholt /** Sampler cache, used by texture engine */ 522673a394bSEric Anholt #define I915_GEM_DOMAIN_SAMPLER 0x00000004 523673a394bSEric Anholt /** Command queue, used to load batch buffers */ 524673a394bSEric Anholt #define I915_GEM_DOMAIN_COMMAND 0x00000008 525673a394bSEric Anholt /** Instruction cache, used by shader programs */ 526673a394bSEric Anholt #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 527673a394bSEric Anholt /** Vertex address cache */ 528673a394bSEric Anholt #define I915_GEM_DOMAIN_VERTEX 0x00000020 529673a394bSEric Anholt /** GTT domain - aperture and scanout */ 530673a394bSEric Anholt #define I915_GEM_DOMAIN_GTT 0x00000040 531673a394bSEric Anholt /** @} */ 532673a394bSEric Anholt 533673a394bSEric Anholt struct drm_i915_gem_exec_object { 534673a394bSEric Anholt /** 535673a394bSEric Anholt * User's handle for a buffer to be bound into the GTT for this 536673a394bSEric Anholt * operation. 537673a394bSEric Anholt */ 5381d7f83d5SArnd Bergmann __u32 handle; 539673a394bSEric Anholt 540673a394bSEric Anholt /** Number of relocations to be performed on this buffer */ 5411d7f83d5SArnd Bergmann __u32 relocation_count; 542673a394bSEric Anholt /** 543673a394bSEric Anholt * Pointer to array of struct drm_i915_gem_relocation_entry containing 544673a394bSEric Anholt * the relocations to be performed in this buffer. 545673a394bSEric Anholt */ 5461d7f83d5SArnd Bergmann __u64 relocs_ptr; 547673a394bSEric Anholt 548673a394bSEric Anholt /** Required alignment in graphics aperture */ 5491d7f83d5SArnd Bergmann __u64 alignment; 550673a394bSEric Anholt 551673a394bSEric Anholt /** 552673a394bSEric Anholt * Returned value of the updated offset of the object, for future 553673a394bSEric Anholt * presumed_offset writes. 554673a394bSEric Anholt */ 5551d7f83d5SArnd Bergmann __u64 offset; 556673a394bSEric Anholt }; 557673a394bSEric Anholt 558673a394bSEric Anholt struct drm_i915_gem_execbuffer { 559673a394bSEric Anholt /** 560673a394bSEric Anholt * List of buffers to be validated with their relocations to be 561673a394bSEric Anholt * performend on them. 562673a394bSEric Anholt * 563673a394bSEric Anholt * This is a pointer to an array of struct drm_i915_gem_validate_entry. 564673a394bSEric Anholt * 565673a394bSEric Anholt * These buffers must be listed in an order such that all relocations 566673a394bSEric Anholt * a buffer is performing refer to buffers that have already appeared 567673a394bSEric Anholt * in the validate list. 568673a394bSEric Anholt */ 5691d7f83d5SArnd Bergmann __u64 buffers_ptr; 5701d7f83d5SArnd Bergmann __u32 buffer_count; 571673a394bSEric Anholt 572673a394bSEric Anholt /** Offset in the batchbuffer to start execution from. */ 5731d7f83d5SArnd Bergmann __u32 batch_start_offset; 574673a394bSEric Anholt /** Bytes used in batchbuffer from batch_start_offset */ 5751d7f83d5SArnd Bergmann __u32 batch_len; 5761d7f83d5SArnd Bergmann __u32 DR1; 5771d7f83d5SArnd Bergmann __u32 DR4; 5781d7f83d5SArnd Bergmann __u32 num_cliprects; 579673a394bSEric Anholt /** This is a struct drm_clip_rect *cliprects */ 5801d7f83d5SArnd Bergmann __u64 cliprects_ptr; 581673a394bSEric Anholt }; 582673a394bSEric Anholt 58376446cacSJesse Barnes struct drm_i915_gem_exec_object2 { 58476446cacSJesse Barnes /** 58576446cacSJesse Barnes * User's handle for a buffer to be bound into the GTT for this 58676446cacSJesse Barnes * operation. 58776446cacSJesse Barnes */ 58876446cacSJesse Barnes __u32 handle; 58976446cacSJesse Barnes 59076446cacSJesse Barnes /** Number of relocations to be performed on this buffer */ 59176446cacSJesse Barnes __u32 relocation_count; 59276446cacSJesse Barnes /** 59376446cacSJesse Barnes * Pointer to array of struct drm_i915_gem_relocation_entry containing 59476446cacSJesse Barnes * the relocations to be performed in this buffer. 59576446cacSJesse Barnes */ 59676446cacSJesse Barnes __u64 relocs_ptr; 59776446cacSJesse Barnes 59876446cacSJesse Barnes /** Required alignment in graphics aperture */ 59976446cacSJesse Barnes __u64 alignment; 60076446cacSJesse Barnes 60176446cacSJesse Barnes /** 60276446cacSJesse Barnes * Returned value of the updated offset of the object, for future 60376446cacSJesse Barnes * presumed_offset writes. 60476446cacSJesse Barnes */ 60576446cacSJesse Barnes __u64 offset; 60676446cacSJesse Barnes 60776446cacSJesse Barnes #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 60876446cacSJesse Barnes __u64 flags; 60976446cacSJesse Barnes __u64 rsvd1; 61076446cacSJesse Barnes __u64 rsvd2; 61176446cacSJesse Barnes }; 61276446cacSJesse Barnes 61376446cacSJesse Barnes struct drm_i915_gem_execbuffer2 { 61476446cacSJesse Barnes /** 61576446cacSJesse Barnes * List of gem_exec_object2 structs 61676446cacSJesse Barnes */ 61776446cacSJesse Barnes __u64 buffers_ptr; 61876446cacSJesse Barnes __u32 buffer_count; 61976446cacSJesse Barnes 62076446cacSJesse Barnes /** Offset in the batchbuffer to start execution from. */ 62176446cacSJesse Barnes __u32 batch_start_offset; 62276446cacSJesse Barnes /** Bytes used in batchbuffer from batch_start_offset */ 62376446cacSJesse Barnes __u32 batch_len; 62476446cacSJesse Barnes __u32 DR1; 62576446cacSJesse Barnes __u32 DR4; 62676446cacSJesse Barnes __u32 num_cliprects; 62776446cacSJesse Barnes /** This is a struct drm_clip_rect *cliprects */ 62876446cacSJesse Barnes __u64 cliprects_ptr; 6298187a2b7SZou Nan hai #define I915_EXEC_RENDER (1<<0) 6308187a2b7SZou Nan hai #define I915_EXEC_BSD (1<<1) 6318187a2b7SZou Nan hai __u64 flags; 63276446cacSJesse Barnes __u64 rsvd1; 63376446cacSJesse Barnes __u64 rsvd2; 63476446cacSJesse Barnes }; 63576446cacSJesse Barnes 636673a394bSEric Anholt struct drm_i915_gem_pin { 637673a394bSEric Anholt /** Handle of the buffer to be pinned. */ 6381d7f83d5SArnd Bergmann __u32 handle; 6391d7f83d5SArnd Bergmann __u32 pad; 640673a394bSEric Anholt 641673a394bSEric Anholt /** alignment required within the aperture */ 6421d7f83d5SArnd Bergmann __u64 alignment; 643673a394bSEric Anholt 644673a394bSEric Anholt /** Returned GTT offset of the buffer. */ 6451d7f83d5SArnd Bergmann __u64 offset; 646673a394bSEric Anholt }; 647673a394bSEric Anholt 648673a394bSEric Anholt struct drm_i915_gem_unpin { 649673a394bSEric Anholt /** Handle of the buffer to be unpinned. */ 6501d7f83d5SArnd Bergmann __u32 handle; 6511d7f83d5SArnd Bergmann __u32 pad; 652673a394bSEric Anholt }; 653673a394bSEric Anholt 654673a394bSEric Anholt struct drm_i915_gem_busy { 655673a394bSEric Anholt /** Handle of the buffer to check for busy */ 6561d7f83d5SArnd Bergmann __u32 handle; 657673a394bSEric Anholt 658673a394bSEric Anholt /** Return busy status (1 if busy, 0 if idle) */ 6591d7f83d5SArnd Bergmann __u32 busy; 660673a394bSEric Anholt }; 661673a394bSEric Anholt 662673a394bSEric Anholt #define I915_TILING_NONE 0 663673a394bSEric Anholt #define I915_TILING_X 1 664673a394bSEric Anholt #define I915_TILING_Y 2 665673a394bSEric Anholt 666673a394bSEric Anholt #define I915_BIT_6_SWIZZLE_NONE 0 667673a394bSEric Anholt #define I915_BIT_6_SWIZZLE_9 1 668673a394bSEric Anholt #define I915_BIT_6_SWIZZLE_9_10 2 669673a394bSEric Anholt #define I915_BIT_6_SWIZZLE_9_11 3 670673a394bSEric Anholt #define I915_BIT_6_SWIZZLE_9_10_11 4 671673a394bSEric Anholt /* Not seen by userland */ 672673a394bSEric Anholt #define I915_BIT_6_SWIZZLE_UNKNOWN 5 673280b713bSEric Anholt /* Seen by userland. */ 674280b713bSEric Anholt #define I915_BIT_6_SWIZZLE_9_17 6 675280b713bSEric Anholt #define I915_BIT_6_SWIZZLE_9_10_17 7 676673a394bSEric Anholt 677673a394bSEric Anholt struct drm_i915_gem_set_tiling { 678673a394bSEric Anholt /** Handle of the buffer to have its tiling state updated */ 6791d7f83d5SArnd Bergmann __u32 handle; 680673a394bSEric Anholt 681673a394bSEric Anholt /** 682673a394bSEric Anholt * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 683673a394bSEric Anholt * I915_TILING_Y). 684673a394bSEric Anholt * 685673a394bSEric Anholt * This value is to be set on request, and will be updated by the 686673a394bSEric Anholt * kernel on successful return with the actual chosen tiling layout. 687673a394bSEric Anholt * 688673a394bSEric Anholt * The tiling mode may be demoted to I915_TILING_NONE when the system 689673a394bSEric Anholt * has bit 6 swizzling that can't be managed correctly by GEM. 690673a394bSEric Anholt * 691673a394bSEric Anholt * Buffer contents become undefined when changing tiling_mode. 692673a394bSEric Anholt */ 6931d7f83d5SArnd Bergmann __u32 tiling_mode; 694673a394bSEric Anholt 695673a394bSEric Anholt /** 696673a394bSEric Anholt * Stride in bytes for the object when in I915_TILING_X or 697673a394bSEric Anholt * I915_TILING_Y. 698673a394bSEric Anholt */ 6991d7f83d5SArnd Bergmann __u32 stride; 700673a394bSEric Anholt 701673a394bSEric Anholt /** 702673a394bSEric Anholt * Returned address bit 6 swizzling required for CPU access through 703673a394bSEric Anholt * mmap mapping. 704673a394bSEric Anholt */ 7051d7f83d5SArnd Bergmann __u32 swizzle_mode; 706673a394bSEric Anholt }; 707673a394bSEric Anholt 708673a394bSEric Anholt struct drm_i915_gem_get_tiling { 709673a394bSEric Anholt /** Handle of the buffer to get tiling state for. */ 7101d7f83d5SArnd Bergmann __u32 handle; 711673a394bSEric Anholt 712673a394bSEric Anholt /** 713673a394bSEric Anholt * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 714673a394bSEric Anholt * I915_TILING_Y). 715673a394bSEric Anholt */ 7161d7f83d5SArnd Bergmann __u32 tiling_mode; 717673a394bSEric Anholt 718673a394bSEric Anholt /** 719673a394bSEric Anholt * Returned address bit 6 swizzling required for CPU access through 720673a394bSEric Anholt * mmap mapping. 721673a394bSEric Anholt */ 7221d7f83d5SArnd Bergmann __u32 swizzle_mode; 723673a394bSEric Anholt }; 724673a394bSEric Anholt 7255a125c3cSEric Anholt struct drm_i915_gem_get_aperture { 7265a125c3cSEric Anholt /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 7271d7f83d5SArnd Bergmann __u64 aper_size; 7285a125c3cSEric Anholt 7295a125c3cSEric Anholt /** 7305a125c3cSEric Anholt * Available space in the aperture used by i915_gem_execbuffer, in 7315a125c3cSEric Anholt * bytes 7325a125c3cSEric Anholt */ 7331d7f83d5SArnd Bergmann __u64 aper_available_size; 7345a125c3cSEric Anholt }; 7355a125c3cSEric Anholt 73608d7b3d1SCarl Worth struct drm_i915_get_pipe_from_crtc_id { 73708d7b3d1SCarl Worth /** ID of CRTC being requested **/ 73808d7b3d1SCarl Worth __u32 crtc_id; 73908d7b3d1SCarl Worth 74008d7b3d1SCarl Worth /** pipe of requested CRTC **/ 74108d7b3d1SCarl Worth __u32 pipe; 74208d7b3d1SCarl Worth }; 74308d7b3d1SCarl Worth 7443ef94daaSChris Wilson #define I915_MADV_WILLNEED 0 7453ef94daaSChris Wilson #define I915_MADV_DONTNEED 1 746bb6baf76SChris Wilson #define __I915_MADV_PURGED 2 /* internal state */ 7473ef94daaSChris Wilson 7483ef94daaSChris Wilson struct drm_i915_gem_madvise { 7493ef94daaSChris Wilson /** Handle of the buffer to change the backing store advice */ 7503ef94daaSChris Wilson __u32 handle; 7513ef94daaSChris Wilson 7523ef94daaSChris Wilson /* Advice: either the buffer will be needed again in the near future, 7533ef94daaSChris Wilson * or wont be and could be discarded under memory pressure. 7543ef94daaSChris Wilson */ 7553ef94daaSChris Wilson __u32 madv; 7563ef94daaSChris Wilson 7573ef94daaSChris Wilson /** Whether the backing store still exists. */ 7583ef94daaSChris Wilson __u32 retained; 7593ef94daaSChris Wilson }; 7603ef94daaSChris Wilson 76102e792fbSDaniel Vetter /* flags */ 76202e792fbSDaniel Vetter #define I915_OVERLAY_TYPE_MASK 0xff 76302e792fbSDaniel Vetter #define I915_OVERLAY_YUV_PLANAR 0x01 76402e792fbSDaniel Vetter #define I915_OVERLAY_YUV_PACKED 0x02 76502e792fbSDaniel Vetter #define I915_OVERLAY_RGB 0x03 76602e792fbSDaniel Vetter 76702e792fbSDaniel Vetter #define I915_OVERLAY_DEPTH_MASK 0xff00 76802e792fbSDaniel Vetter #define I915_OVERLAY_RGB24 0x1000 76902e792fbSDaniel Vetter #define I915_OVERLAY_RGB16 0x2000 77002e792fbSDaniel Vetter #define I915_OVERLAY_RGB15 0x3000 77102e792fbSDaniel Vetter #define I915_OVERLAY_YUV422 0x0100 77202e792fbSDaniel Vetter #define I915_OVERLAY_YUV411 0x0200 77302e792fbSDaniel Vetter #define I915_OVERLAY_YUV420 0x0300 77402e792fbSDaniel Vetter #define I915_OVERLAY_YUV410 0x0400 77502e792fbSDaniel Vetter 77602e792fbSDaniel Vetter #define I915_OVERLAY_SWAP_MASK 0xff0000 77702e792fbSDaniel Vetter #define I915_OVERLAY_NO_SWAP 0x000000 77802e792fbSDaniel Vetter #define I915_OVERLAY_UV_SWAP 0x010000 77902e792fbSDaniel Vetter #define I915_OVERLAY_Y_SWAP 0x020000 78002e792fbSDaniel Vetter #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 78102e792fbSDaniel Vetter 78202e792fbSDaniel Vetter #define I915_OVERLAY_FLAGS_MASK 0xff000000 78302e792fbSDaniel Vetter #define I915_OVERLAY_ENABLE 0x01000000 78402e792fbSDaniel Vetter 78502e792fbSDaniel Vetter struct drm_intel_overlay_put_image { 78602e792fbSDaniel Vetter /* various flags and src format description */ 78702e792fbSDaniel Vetter __u32 flags; 78802e792fbSDaniel Vetter /* source picture description */ 78902e792fbSDaniel Vetter __u32 bo_handle; 79002e792fbSDaniel Vetter /* stride values and offsets are in bytes, buffer relative */ 79102e792fbSDaniel Vetter __u16 stride_Y; /* stride for packed formats */ 79202e792fbSDaniel Vetter __u16 stride_UV; 79302e792fbSDaniel Vetter __u32 offset_Y; /* offset for packet formats */ 79402e792fbSDaniel Vetter __u32 offset_U; 79502e792fbSDaniel Vetter __u32 offset_V; 79602e792fbSDaniel Vetter /* in pixels */ 79702e792fbSDaniel Vetter __u16 src_width; 79802e792fbSDaniel Vetter __u16 src_height; 79902e792fbSDaniel Vetter /* to compensate the scaling factors for partially covered surfaces */ 80002e792fbSDaniel Vetter __u16 src_scan_width; 80102e792fbSDaniel Vetter __u16 src_scan_height; 80202e792fbSDaniel Vetter /* output crtc description */ 80302e792fbSDaniel Vetter __u32 crtc_id; 80402e792fbSDaniel Vetter __u16 dst_x; 80502e792fbSDaniel Vetter __u16 dst_y; 80602e792fbSDaniel Vetter __u16 dst_width; 80702e792fbSDaniel Vetter __u16 dst_height; 80802e792fbSDaniel Vetter }; 80902e792fbSDaniel Vetter 81002e792fbSDaniel Vetter /* flags */ 81102e792fbSDaniel Vetter #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 81202e792fbSDaniel Vetter #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 81302e792fbSDaniel Vetter struct drm_intel_overlay_attrs { 81402e792fbSDaniel Vetter __u32 flags; 81502e792fbSDaniel Vetter __u32 color_key; 81602e792fbSDaniel Vetter __s32 brightness; 81702e792fbSDaniel Vetter __u32 contrast; 81802e792fbSDaniel Vetter __u32 saturation; 81902e792fbSDaniel Vetter __u32 gamma0; 82002e792fbSDaniel Vetter __u32 gamma1; 82102e792fbSDaniel Vetter __u32 gamma2; 82202e792fbSDaniel Vetter __u32 gamma3; 82302e792fbSDaniel Vetter __u32 gamma4; 82402e792fbSDaniel Vetter __u32 gamma5; 82502e792fbSDaniel Vetter }; 82602e792fbSDaniel Vetter 827c0e09200SDave Airlie #endif /* _I915_DRM_H_ */ 828