1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef _DRM_GPU_SCHEDULER_H_ 25 #define _DRM_GPU_SCHEDULER_H_ 26 27 #include <drm/spsc_queue.h> 28 #include <linux/dma-fence.h> 29 #include <linux/completion.h> 30 31 #define MAX_WAIT_SCHED_ENTITY_Q_EMPTY msecs_to_jiffies(1000) 32 33 struct drm_gpu_scheduler; 34 struct drm_sched_rq; 35 36 enum drm_sched_priority { 37 DRM_SCHED_PRIORITY_MIN, 38 DRM_SCHED_PRIORITY_LOW = DRM_SCHED_PRIORITY_MIN, 39 DRM_SCHED_PRIORITY_NORMAL, 40 DRM_SCHED_PRIORITY_HIGH_SW, 41 DRM_SCHED_PRIORITY_HIGH_HW, 42 DRM_SCHED_PRIORITY_KERNEL, 43 DRM_SCHED_PRIORITY_MAX, 44 DRM_SCHED_PRIORITY_INVALID = -1, 45 DRM_SCHED_PRIORITY_UNSET = -2 46 }; 47 48 /** 49 * struct drm_sched_entity - A wrapper around a job queue (typically 50 * attached to the DRM file_priv). 51 * 52 * @list: used to append this struct to the list of entities in the 53 * runqueue. 54 * @rq: runqueue on which this entity is currently scheduled. 55 * @sched_list: a list of drm_gpu_schedulers on which jobs from this entity can 56 * be scheduled 57 * @num_sched_list: number of drm_gpu_schedulers in the sched_list. 58 * @rq_lock: lock to modify the runqueue to which this entity belongs. 59 * @job_queue: the list of jobs of this entity. 60 * @fence_seq: a linearly increasing seqno incremented with each 61 * new &drm_sched_fence which is part of the entity. 62 * @fence_context: a unique context for all the fences which belong 63 * to this entity. 64 * The &drm_sched_fence.scheduled uses the 65 * fence_context but &drm_sched_fence.finished uses 66 * fence_context + 1. 67 * @dependency: the dependency fence of the job which is on the top 68 * of the job queue. 69 * @cb: callback for the dependency fence above. 70 * @guilty: points to ctx's guilty. 71 * @fini_status: contains the exit status in case the process was signalled. 72 * @last_scheduled: points to the finished fence of the last scheduled job. 73 * @last_user: last group leader pushing a job into the entity. 74 * @stopped: Marks the enity as removed from rq and destined for termination. 75 * @entity_idle: Signals when enityt is not in use 76 * 77 * Entities will emit jobs in order to their corresponding hardware 78 * ring, and the scheduler will alternate between entities based on 79 * scheduling policy. 80 */ 81 struct drm_sched_entity { 82 struct list_head list; 83 struct drm_sched_rq *rq; 84 struct drm_gpu_scheduler **sched_list; 85 unsigned int num_sched_list; 86 enum drm_sched_priority priority; 87 spinlock_t rq_lock; 88 89 struct spsc_queue job_queue; 90 91 atomic_t fence_seq; 92 uint64_t fence_context; 93 94 struct dma_fence *dependency; 95 struct dma_fence_cb cb; 96 atomic_t *guilty; 97 struct dma_fence *last_scheduled; 98 struct task_struct *last_user; 99 bool stopped; 100 struct completion entity_idle; 101 }; 102 103 /** 104 * struct drm_sched_rq - queue of entities to be scheduled. 105 * 106 * @lock: to modify the entities list. 107 * @sched: the scheduler to which this rq belongs to. 108 * @entities: list of the entities to be scheduled. 109 * @current_entity: the entity which is to be scheduled. 110 * 111 * Run queue is a set of entities scheduling command submissions for 112 * one specific ring. It implements the scheduling policy that selects 113 * the next entity to emit commands from. 114 */ 115 struct drm_sched_rq { 116 spinlock_t lock; 117 struct drm_gpu_scheduler *sched; 118 struct list_head entities; 119 struct drm_sched_entity *current_entity; 120 }; 121 122 /** 123 * struct drm_sched_fence - fences corresponding to the scheduling of a job. 124 */ 125 struct drm_sched_fence { 126 /** 127 * @scheduled: this fence is what will be signaled by the scheduler 128 * when the job is scheduled. 129 */ 130 struct dma_fence scheduled; 131 132 /** 133 * @finished: this fence is what will be signaled by the scheduler 134 * when the job is completed. 135 * 136 * When setting up an out fence for the job, you should use 137 * this, since it's available immediately upon 138 * drm_sched_job_init(), and the fence returned by the driver 139 * from run_job() won't be created until the dependencies have 140 * resolved. 141 */ 142 struct dma_fence finished; 143 144 /** 145 * @parent: the fence returned by &drm_sched_backend_ops.run_job 146 * when scheduling the job on hardware. We signal the 147 * &drm_sched_fence.finished fence once parent is signalled. 148 */ 149 struct dma_fence *parent; 150 /** 151 * @sched: the scheduler instance to which the job having this struct 152 * belongs to. 153 */ 154 struct drm_gpu_scheduler *sched; 155 /** 156 * @lock: the lock used by the scheduled and the finished fences. 157 */ 158 spinlock_t lock; 159 /** 160 * @owner: job owner for debugging 161 */ 162 void *owner; 163 }; 164 165 struct drm_sched_fence *to_drm_sched_fence(struct dma_fence *f); 166 167 /** 168 * struct drm_sched_job - A job to be run by an entity. 169 * 170 * @queue_node: used to append this struct to the queue of jobs in an entity. 171 * @sched: the scheduler instance on which this job is scheduled. 172 * @s_fence: contains the fences for the scheduling of job. 173 * @finish_cb: the callback for the finished fence. 174 * @node: used to append this struct to the @drm_gpu_scheduler.ring_mirror_list. 175 * @id: a unique id assigned to each job scheduled on the scheduler. 176 * @karma: increment on every hang caused by this job. If this exceeds the hang 177 * limit of the scheduler then the job is marked guilty and will not 178 * be scheduled further. 179 * @s_priority: the priority of the job. 180 * @entity: the entity to which this job belongs. 181 * @cb: the callback for the parent fence in s_fence. 182 * 183 * A job is created by the driver using drm_sched_job_init(), and 184 * should call drm_sched_entity_push_job() once it wants the scheduler 185 * to schedule the job. 186 */ 187 struct drm_sched_job { 188 struct spsc_node queue_node; 189 struct drm_gpu_scheduler *sched; 190 struct drm_sched_fence *s_fence; 191 struct dma_fence_cb finish_cb; 192 struct list_head node; 193 uint64_t id; 194 atomic_t karma; 195 enum drm_sched_priority s_priority; 196 struct drm_sched_entity *entity; 197 struct dma_fence_cb cb; 198 }; 199 200 static inline bool drm_sched_invalidate_job(struct drm_sched_job *s_job, 201 int threshold) 202 { 203 return (s_job && atomic_inc_return(&s_job->karma) > threshold); 204 } 205 206 /** 207 * struct drm_sched_backend_ops 208 * 209 * Define the backend operations called by the scheduler, 210 * these functions should be implemented in driver side. 211 */ 212 struct drm_sched_backend_ops { 213 /** 214 * @dependency: Called when the scheduler is considering scheduling 215 * this job next, to get another struct dma_fence for this job to 216 * block on. Once it returns NULL, run_job() may be called. 217 */ 218 struct dma_fence *(*dependency)(struct drm_sched_job *sched_job, 219 struct drm_sched_entity *s_entity); 220 221 /** 222 * @run_job: Called to execute the job once all of the dependencies 223 * have been resolved. This may be called multiple times, if 224 * timedout_job() has happened and drm_sched_job_recovery() 225 * decides to try it again. 226 */ 227 struct dma_fence *(*run_job)(struct drm_sched_job *sched_job); 228 229 /** 230 * @timedout_job: Called when a job has taken too long to execute, 231 * to trigger GPU recovery. 232 */ 233 void (*timedout_job)(struct drm_sched_job *sched_job); 234 235 /** 236 * @free_job: Called once the job's finished fence has been signaled 237 * and it's time to clean it up. 238 */ 239 void (*free_job)(struct drm_sched_job *sched_job); 240 }; 241 242 /** 243 * struct drm_gpu_scheduler 244 * 245 * @ops: backend operations provided by the driver. 246 * @hw_submission_limit: the max size of the hardware queue. 247 * @timeout: the time after which a job is removed from the scheduler. 248 * @name: name of the ring for which this scheduler is being used. 249 * @sched_rq: priority wise array of run queues. 250 * @wake_up_worker: the wait queue on which the scheduler sleeps until a job 251 * is ready to be scheduled. 252 * @job_scheduled: once @drm_sched_entity_do_release is called the scheduler 253 * waits on this wait queue until all the scheduled jobs are 254 * finished. 255 * @hw_rq_count: the number of jobs currently in the hardware queue. 256 * @job_id_count: used to assign unique id to the each job. 257 * @work_tdr: schedules a delayed call to @drm_sched_job_timedout after the 258 * timeout interval is over. 259 * @thread: the kthread on which the scheduler which run. 260 * @ring_mirror_list: the list of jobs which are currently in the job queue. 261 * @job_list_lock: lock to protect the ring_mirror_list. 262 * @hang_limit: once the hangs by a job crosses this limit then it is marked 263 * guilty and it will be considered for scheduling further. 264 * @score: score to help loadbalancer pick a idle sched 265 * @ready: marks if the underlying HW is ready to work 266 * @free_guilty: A hit to time out handler to free the guilty job. 267 * 268 * One scheduler is implemented for each hardware ring. 269 */ 270 struct drm_gpu_scheduler { 271 const struct drm_sched_backend_ops *ops; 272 uint32_t hw_submission_limit; 273 long timeout; 274 const char *name; 275 struct drm_sched_rq sched_rq[DRM_SCHED_PRIORITY_MAX]; 276 wait_queue_head_t wake_up_worker; 277 wait_queue_head_t job_scheduled; 278 atomic_t hw_rq_count; 279 atomic64_t job_id_count; 280 struct delayed_work work_tdr; 281 struct task_struct *thread; 282 struct list_head ring_mirror_list; 283 spinlock_t job_list_lock; 284 int hang_limit; 285 atomic_t score; 286 bool ready; 287 bool free_guilty; 288 }; 289 290 int drm_sched_init(struct drm_gpu_scheduler *sched, 291 const struct drm_sched_backend_ops *ops, 292 uint32_t hw_submission, unsigned hang_limit, long timeout, 293 const char *name); 294 295 void drm_sched_fini(struct drm_gpu_scheduler *sched); 296 int drm_sched_job_init(struct drm_sched_job *job, 297 struct drm_sched_entity *entity, 298 void *owner); 299 void drm_sched_job_cleanup(struct drm_sched_job *job); 300 void drm_sched_wakeup(struct drm_gpu_scheduler *sched); 301 void drm_sched_stop(struct drm_gpu_scheduler *sched, struct drm_sched_job *bad); 302 void drm_sched_start(struct drm_gpu_scheduler *sched, bool full_recovery); 303 void drm_sched_resubmit_jobs(struct drm_gpu_scheduler *sched); 304 void drm_sched_increase_karma(struct drm_sched_job *bad); 305 bool drm_sched_dependency_optimized(struct dma_fence* fence, 306 struct drm_sched_entity *entity); 307 void drm_sched_fault(struct drm_gpu_scheduler *sched); 308 void drm_sched_job_kickout(struct drm_sched_job *s_job); 309 310 void drm_sched_rq_add_entity(struct drm_sched_rq *rq, 311 struct drm_sched_entity *entity); 312 void drm_sched_rq_remove_entity(struct drm_sched_rq *rq, 313 struct drm_sched_entity *entity); 314 315 int drm_sched_entity_init(struct drm_sched_entity *entity, 316 enum drm_sched_priority priority, 317 struct drm_gpu_scheduler **sched_list, 318 unsigned int num_sched_list, 319 atomic_t *guilty); 320 long drm_sched_entity_flush(struct drm_sched_entity *entity, long timeout); 321 void drm_sched_entity_fini(struct drm_sched_entity *entity); 322 void drm_sched_entity_destroy(struct drm_sched_entity *entity); 323 void drm_sched_entity_select_rq(struct drm_sched_entity *entity); 324 struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity); 325 void drm_sched_entity_push_job(struct drm_sched_job *sched_job, 326 struct drm_sched_entity *entity); 327 void drm_sched_entity_set_priority(struct drm_sched_entity *entity, 328 enum drm_sched_priority priority); 329 bool drm_sched_entity_is_ready(struct drm_sched_entity *entity); 330 331 struct drm_sched_fence *drm_sched_fence_create( 332 struct drm_sched_entity *s_entity, void *owner); 333 void drm_sched_fence_scheduled(struct drm_sched_fence *fence); 334 void drm_sched_fence_finished(struct drm_sched_fence *fence); 335 336 unsigned long drm_sched_suspend_timeout(struct drm_gpu_scheduler *sched); 337 void drm_sched_resume_timeout(struct drm_gpu_scheduler *sched, 338 unsigned long remaining); 339 340 #endif 341