1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef _DRM_GPU_SCHEDULER_H_ 25 #define _DRM_GPU_SCHEDULER_H_ 26 27 #include <drm/spsc_queue.h> 28 #include <linux/dma-fence.h> 29 #include <linux/completion.h> 30 #include <linux/xarray.h> 31 #include <linux/workqueue.h> 32 33 #define MAX_WAIT_SCHED_ENTITY_Q_EMPTY msecs_to_jiffies(1000) 34 35 /** 36 * DRM_SCHED_FENCE_DONT_PIPELINE - Prefent dependency pipelining 37 * 38 * Setting this flag on a scheduler fence prevents pipelining of jobs depending 39 * on this fence. In other words we always insert a full CPU round trip before 40 * dependen jobs are pushed to the hw queue. 41 */ 42 #define DRM_SCHED_FENCE_DONT_PIPELINE DMA_FENCE_FLAG_USER_BITS 43 44 /** 45 * DRM_SCHED_FENCE_FLAG_HAS_DEADLINE_BIT - A fence deadline hint has been set 46 * 47 * Because we could have a deadline hint can be set before the backing hw 48 * fence is created, we need to keep track of whether a deadline has already 49 * been set. 50 */ 51 #define DRM_SCHED_FENCE_FLAG_HAS_DEADLINE_BIT (DMA_FENCE_FLAG_USER_BITS + 1) 52 53 enum dma_resv_usage; 54 struct dma_resv; 55 struct drm_gem_object; 56 57 struct drm_gpu_scheduler; 58 struct drm_sched_rq; 59 60 struct drm_file; 61 62 /* These are often used as an (initial) index 63 * to an array, and as such should start at 0. 64 */ 65 enum drm_sched_priority { 66 DRM_SCHED_PRIORITY_MIN, 67 DRM_SCHED_PRIORITY_NORMAL, 68 DRM_SCHED_PRIORITY_HIGH, 69 DRM_SCHED_PRIORITY_KERNEL, 70 71 DRM_SCHED_PRIORITY_COUNT, 72 DRM_SCHED_PRIORITY_UNSET = -2 73 }; 74 75 /* Used to chose between FIFO and RR jobs scheduling */ 76 extern int drm_sched_policy; 77 78 #define DRM_SCHED_POLICY_RR 0 79 #define DRM_SCHED_POLICY_FIFO 1 80 81 /** 82 * struct drm_sched_entity - A wrapper around a job queue (typically 83 * attached to the DRM file_priv). 84 * 85 * Entities will emit jobs in order to their corresponding hardware 86 * ring, and the scheduler will alternate between entities based on 87 * scheduling policy. 88 */ 89 struct drm_sched_entity { 90 /** 91 * @list: 92 * 93 * Used to append this struct to the list of entities in the runqueue 94 * @rq under &drm_sched_rq.entities. 95 * 96 * Protected by &drm_sched_rq.lock of @rq. 97 */ 98 struct list_head list; 99 100 /** 101 * @rq: 102 * 103 * Runqueue on which this entity is currently scheduled. 104 * 105 * FIXME: Locking is very unclear for this. Writers are protected by 106 * @rq_lock, but readers are generally lockless and seem to just race 107 * with not even a READ_ONCE. 108 */ 109 struct drm_sched_rq *rq; 110 111 /** 112 * @sched_list: 113 * 114 * A list of schedulers (struct drm_gpu_scheduler). Jobs from this entity can 115 * be scheduled on any scheduler on this list. 116 * 117 * This can be modified by calling drm_sched_entity_modify_sched(). 118 * Locking is entirely up to the driver, see the above function for more 119 * details. 120 * 121 * This will be set to NULL if &num_sched_list equals 1 and @rq has been 122 * set already. 123 * 124 * FIXME: This means priority changes through 125 * drm_sched_entity_set_priority() will be lost henceforth in this case. 126 */ 127 struct drm_gpu_scheduler **sched_list; 128 129 /** 130 * @num_sched_list: 131 * 132 * Number of drm_gpu_schedulers in the @sched_list. 133 */ 134 unsigned int num_sched_list; 135 136 /** 137 * @priority: 138 * 139 * Priority of the entity. This can be modified by calling 140 * drm_sched_entity_set_priority(). Protected by &rq_lock. 141 */ 142 enum drm_sched_priority priority; 143 144 /** 145 * @rq_lock: 146 * 147 * Lock to modify the runqueue to which this entity belongs. 148 */ 149 spinlock_t rq_lock; 150 151 /** 152 * @job_queue: the list of jobs of this entity. 153 */ 154 struct spsc_queue job_queue; 155 156 /** 157 * @fence_seq: 158 * 159 * A linearly increasing seqno incremented with each new 160 * &drm_sched_fence which is part of the entity. 161 * 162 * FIXME: Callers of drm_sched_job_arm() need to ensure correct locking, 163 * this doesn't need to be atomic. 164 */ 165 atomic_t fence_seq; 166 167 /** 168 * @fence_context: 169 * 170 * A unique context for all the fences which belong to this entity. The 171 * &drm_sched_fence.scheduled uses the fence_context but 172 * &drm_sched_fence.finished uses fence_context + 1. 173 */ 174 uint64_t fence_context; 175 176 /** 177 * @dependency: 178 * 179 * The dependency fence of the job which is on the top of the job queue. 180 */ 181 struct dma_fence *dependency; 182 183 /** 184 * @cb: 185 * 186 * Callback for the dependency fence above. 187 */ 188 struct dma_fence_cb cb; 189 190 /** 191 * @guilty: 192 * 193 * Points to entities' guilty. 194 */ 195 atomic_t *guilty; 196 197 /** 198 * @last_scheduled: 199 * 200 * Points to the finished fence of the last scheduled job. Only written 201 * by the scheduler thread, can be accessed locklessly from 202 * drm_sched_job_arm() iff the queue is empty. 203 */ 204 struct dma_fence *last_scheduled; 205 206 /** 207 * @last_user: last group leader pushing a job into the entity. 208 */ 209 struct task_struct *last_user; 210 211 /** 212 * @stopped: 213 * 214 * Marks the enity as removed from rq and destined for 215 * termination. This is set by calling drm_sched_entity_flush() and by 216 * drm_sched_fini(). 217 */ 218 bool stopped; 219 220 /** 221 * @entity_idle: 222 * 223 * Signals when entity is not in use, used to sequence entity cleanup in 224 * drm_sched_entity_fini(). 225 */ 226 struct completion entity_idle; 227 228 /** 229 * @oldest_job_waiting: 230 * 231 * Marks earliest job waiting in SW queue 232 */ 233 ktime_t oldest_job_waiting; 234 235 /** 236 * @rb_tree_node: 237 * 238 * The node used to insert this entity into time based priority queue 239 */ 240 struct rb_node rb_tree_node; 241 242 /** 243 * @elapsed_ns: 244 * 245 * Records the amount of time where jobs from this entity were active 246 * on the GPU. 247 */ 248 uint64_t elapsed_ns; 249 }; 250 251 /** 252 * struct drm_sched_rq - queue of entities to be scheduled. 253 * 254 * @lock: to modify the entities list. 255 * @sched: the scheduler to which this rq belongs to. 256 * @entities: list of the entities to be scheduled. 257 * @current_entity: the entity which is to be scheduled. 258 * @rb_tree_root: root of time based priory queue of entities for FIFO scheduling 259 * 260 * Run queue is a set of entities scheduling command submissions for 261 * one specific ring. It implements the scheduling policy that selects 262 * the next entity to emit commands from. 263 */ 264 struct drm_sched_rq { 265 spinlock_t lock; 266 struct drm_gpu_scheduler *sched; 267 struct list_head entities; 268 struct drm_sched_entity *current_entity; 269 struct rb_root_cached rb_tree_root; 270 }; 271 272 /** 273 * struct drm_sched_fence - fences corresponding to the scheduling of a job. 274 */ 275 struct drm_sched_fence { 276 /** 277 * @scheduled: this fence is what will be signaled by the scheduler 278 * when the job is scheduled. 279 */ 280 struct dma_fence scheduled; 281 282 /** 283 * @finished: this fence is what will be signaled by the scheduler 284 * when the job is completed. 285 * 286 * When setting up an out fence for the job, you should use 287 * this, since it's available immediately upon 288 * drm_sched_job_init(), and the fence returned by the driver 289 * from run_job() won't be created until the dependencies have 290 * resolved. 291 */ 292 struct dma_fence finished; 293 294 /** 295 * @deadline: deadline set on &drm_sched_fence.finished which 296 * potentially needs to be propagated to &drm_sched_fence.parent 297 */ 298 ktime_t deadline; 299 300 /** 301 * @parent: the fence returned by &drm_sched_backend_ops.run_job 302 * when scheduling the job on hardware. We signal the 303 * &drm_sched_fence.finished fence once parent is signalled. 304 */ 305 struct dma_fence *parent; 306 /** 307 * @sched: the scheduler instance to which the job having this struct 308 * belongs to. 309 */ 310 struct drm_gpu_scheduler *sched; 311 /** 312 * @lock: the lock used by the scheduled and the finished fences. 313 */ 314 spinlock_t lock; 315 /** 316 * @owner: job owner for debugging 317 */ 318 void *owner; 319 }; 320 321 struct drm_sched_fence *to_drm_sched_fence(struct dma_fence *f); 322 323 /** 324 * struct drm_sched_job - A job to be run by an entity. 325 * 326 * @queue_node: used to append this struct to the queue of jobs in an entity. 327 * @list: a job participates in a "pending" and "done" lists. 328 * @sched: the scheduler instance on which this job is scheduled. 329 * @s_fence: contains the fences for the scheduling of job. 330 * @finish_cb: the callback for the finished fence. 331 * @work: Helper to reschdeule job kill to different context. 332 * @id: a unique id assigned to each job scheduled on the scheduler. 333 * @karma: increment on every hang caused by this job. If this exceeds the hang 334 * limit of the scheduler then the job is marked guilty and will not 335 * be scheduled further. 336 * @s_priority: the priority of the job. 337 * @entity: the entity to which this job belongs. 338 * @cb: the callback for the parent fence in s_fence. 339 * 340 * A job is created by the driver using drm_sched_job_init(), and 341 * should call drm_sched_entity_push_job() once it wants the scheduler 342 * to schedule the job. 343 */ 344 struct drm_sched_job { 345 struct spsc_node queue_node; 346 struct list_head list; 347 struct drm_gpu_scheduler *sched; 348 struct drm_sched_fence *s_fence; 349 350 /* 351 * work is used only after finish_cb has been used and will not be 352 * accessed anymore. 353 */ 354 union { 355 struct dma_fence_cb finish_cb; 356 struct work_struct work; 357 }; 358 359 uint64_t id; 360 atomic_t karma; 361 enum drm_sched_priority s_priority; 362 struct drm_sched_entity *entity; 363 struct dma_fence_cb cb; 364 /** 365 * @dependencies: 366 * 367 * Contains the dependencies as struct dma_fence for this job, see 368 * drm_sched_job_add_dependency() and 369 * drm_sched_job_add_implicit_dependencies(). 370 */ 371 struct xarray dependencies; 372 373 /** @last_dependency: tracks @dependencies as they signal */ 374 unsigned long last_dependency; 375 376 /** 377 * @submit_ts: 378 * 379 * When the job was pushed into the entity queue. 380 */ 381 ktime_t submit_ts; 382 }; 383 384 static inline bool drm_sched_invalidate_job(struct drm_sched_job *s_job, 385 int threshold) 386 { 387 return s_job && atomic_inc_return(&s_job->karma) > threshold; 388 } 389 390 enum drm_gpu_sched_stat { 391 DRM_GPU_SCHED_STAT_NONE, /* Reserve 0 */ 392 DRM_GPU_SCHED_STAT_NOMINAL, 393 DRM_GPU_SCHED_STAT_ENODEV, 394 }; 395 396 /** 397 * struct drm_sched_backend_ops - Define the backend operations 398 * called by the scheduler 399 * 400 * These functions should be implemented in the driver side. 401 */ 402 struct drm_sched_backend_ops { 403 /** 404 * @prepare_job: 405 * 406 * Called when the scheduler is considering scheduling this job next, to 407 * get another struct dma_fence for this job to block on. Once it 408 * returns NULL, run_job() may be called. 409 * 410 * Can be NULL if no additional preparation to the dependencies are 411 * necessary. Skipped when jobs are killed instead of run. 412 */ 413 struct dma_fence *(*prepare_job)(struct drm_sched_job *sched_job, 414 struct drm_sched_entity *s_entity); 415 416 /** 417 * @run_job: Called to execute the job once all of the dependencies 418 * have been resolved. This may be called multiple times, if 419 * timedout_job() has happened and drm_sched_job_recovery() 420 * decides to try it again. 421 */ 422 struct dma_fence *(*run_job)(struct drm_sched_job *sched_job); 423 424 /** 425 * @timedout_job: Called when a job has taken too long to execute, 426 * to trigger GPU recovery. 427 * 428 * This method is called in a workqueue context. 429 * 430 * Drivers typically issue a reset to recover from GPU hangs, and this 431 * procedure usually follows the following workflow: 432 * 433 * 1. Stop the scheduler using drm_sched_stop(). This will park the 434 * scheduler thread and cancel the timeout work, guaranteeing that 435 * nothing is queued while we reset the hardware queue 436 * 2. Try to gracefully stop non-faulty jobs (optional) 437 * 3. Issue a GPU reset (driver-specific) 438 * 4. Re-submit jobs using drm_sched_resubmit_jobs() 439 * 5. Restart the scheduler using drm_sched_start(). At that point, new 440 * jobs can be queued, and the scheduler thread is unblocked 441 * 442 * Note that some GPUs have distinct hardware queues but need to reset 443 * the GPU globally, which requires extra synchronization between the 444 * timeout handler of the different &drm_gpu_scheduler. One way to 445 * achieve this synchronization is to create an ordered workqueue 446 * (using alloc_ordered_workqueue()) at the driver level, and pass this 447 * queue to drm_sched_init(), to guarantee that timeout handlers are 448 * executed sequentially. The above workflow needs to be slightly 449 * adjusted in that case: 450 * 451 * 1. Stop all schedulers impacted by the reset using drm_sched_stop() 452 * 2. Try to gracefully stop non-faulty jobs on all queues impacted by 453 * the reset (optional) 454 * 3. Issue a GPU reset on all faulty queues (driver-specific) 455 * 4. Re-submit jobs on all schedulers impacted by the reset using 456 * drm_sched_resubmit_jobs() 457 * 5. Restart all schedulers that were stopped in step #1 using 458 * drm_sched_start() 459 * 460 * Return DRM_GPU_SCHED_STAT_NOMINAL, when all is normal, 461 * and the underlying driver has started or completed recovery. 462 * 463 * Return DRM_GPU_SCHED_STAT_ENODEV, if the device is no longer 464 * available, i.e. has been unplugged. 465 */ 466 enum drm_gpu_sched_stat (*timedout_job)(struct drm_sched_job *sched_job); 467 468 /** 469 * @free_job: Called once the job's finished fence has been signaled 470 * and it's time to clean it up. 471 */ 472 void (*free_job)(struct drm_sched_job *sched_job); 473 }; 474 475 /** 476 * struct drm_gpu_scheduler - scheduler instance-specific data 477 * 478 * @ops: backend operations provided by the driver. 479 * @hw_submission_limit: the max size of the hardware queue. 480 * @timeout: the time after which a job is removed from the scheduler. 481 * @name: name of the ring for which this scheduler is being used. 482 * @sched_rq: priority wise array of run queues. 483 * @wake_up_worker: the wait queue on which the scheduler sleeps until a job 484 * is ready to be scheduled. 485 * @job_scheduled: once @drm_sched_entity_do_release is called the scheduler 486 * waits on this wait queue until all the scheduled jobs are 487 * finished. 488 * @hw_rq_count: the number of jobs currently in the hardware queue. 489 * @job_id_count: used to assign unique id to the each job. 490 * @timeout_wq: workqueue used to queue @work_tdr 491 * @work_tdr: schedules a delayed call to @drm_sched_job_timedout after the 492 * timeout interval is over. 493 * @thread: the kthread on which the scheduler which run. 494 * @pending_list: the list of jobs which are currently in the job queue. 495 * @job_list_lock: lock to protect the pending_list. 496 * @hang_limit: once the hangs by a job crosses this limit then it is marked 497 * guilty and it will no longer be considered for scheduling. 498 * @score: score to help loadbalancer pick a idle sched 499 * @_score: score used when the driver doesn't provide one 500 * @ready: marks if the underlying HW is ready to work 501 * @free_guilty: A hit to time out handler to free the guilty job. 502 * @dev: system &struct device 503 * 504 * One scheduler is implemented for each hardware ring. 505 */ 506 struct drm_gpu_scheduler { 507 const struct drm_sched_backend_ops *ops; 508 uint32_t hw_submission_limit; 509 long timeout; 510 const char *name; 511 struct drm_sched_rq sched_rq[DRM_SCHED_PRIORITY_COUNT]; 512 wait_queue_head_t wake_up_worker; 513 wait_queue_head_t job_scheduled; 514 atomic_t hw_rq_count; 515 atomic64_t job_id_count; 516 struct workqueue_struct *timeout_wq; 517 struct delayed_work work_tdr; 518 struct task_struct *thread; 519 struct list_head pending_list; 520 spinlock_t job_list_lock; 521 int hang_limit; 522 atomic_t *score; 523 atomic_t _score; 524 bool ready; 525 bool free_guilty; 526 struct device *dev; 527 }; 528 529 int drm_sched_init(struct drm_gpu_scheduler *sched, 530 const struct drm_sched_backend_ops *ops, 531 uint32_t hw_submission, unsigned hang_limit, 532 long timeout, struct workqueue_struct *timeout_wq, 533 atomic_t *score, const char *name, struct device *dev); 534 535 void drm_sched_fini(struct drm_gpu_scheduler *sched); 536 int drm_sched_job_init(struct drm_sched_job *job, 537 struct drm_sched_entity *entity, 538 void *owner); 539 void drm_sched_job_arm(struct drm_sched_job *job); 540 int drm_sched_job_add_dependency(struct drm_sched_job *job, 541 struct dma_fence *fence); 542 int drm_sched_job_add_syncobj_dependency(struct drm_sched_job *job, 543 struct drm_file *file, 544 u32 handle, 545 u32 point); 546 int drm_sched_job_add_resv_dependencies(struct drm_sched_job *job, 547 struct dma_resv *resv, 548 enum dma_resv_usage usage); 549 int drm_sched_job_add_implicit_dependencies(struct drm_sched_job *job, 550 struct drm_gem_object *obj, 551 bool write); 552 553 554 void drm_sched_entity_modify_sched(struct drm_sched_entity *entity, 555 struct drm_gpu_scheduler **sched_list, 556 unsigned int num_sched_list); 557 558 void drm_sched_job_cleanup(struct drm_sched_job *job); 559 void drm_sched_wakeup(struct drm_gpu_scheduler *sched); 560 void drm_sched_stop(struct drm_gpu_scheduler *sched, struct drm_sched_job *bad); 561 void drm_sched_start(struct drm_gpu_scheduler *sched, bool full_recovery); 562 void drm_sched_resubmit_jobs(struct drm_gpu_scheduler *sched); 563 void drm_sched_increase_karma(struct drm_sched_job *bad); 564 void drm_sched_reset_karma(struct drm_sched_job *bad); 565 void drm_sched_increase_karma_ext(struct drm_sched_job *bad, int type); 566 bool drm_sched_dependency_optimized(struct dma_fence* fence, 567 struct drm_sched_entity *entity); 568 void drm_sched_fault(struct drm_gpu_scheduler *sched); 569 570 void drm_sched_rq_add_entity(struct drm_sched_rq *rq, 571 struct drm_sched_entity *entity); 572 void drm_sched_rq_remove_entity(struct drm_sched_rq *rq, 573 struct drm_sched_entity *entity); 574 575 void drm_sched_rq_update_fifo(struct drm_sched_entity *entity, ktime_t ts); 576 577 int drm_sched_entity_init(struct drm_sched_entity *entity, 578 enum drm_sched_priority priority, 579 struct drm_gpu_scheduler **sched_list, 580 unsigned int num_sched_list, 581 atomic_t *guilty); 582 long drm_sched_entity_flush(struct drm_sched_entity *entity, long timeout); 583 void drm_sched_entity_fini(struct drm_sched_entity *entity); 584 void drm_sched_entity_destroy(struct drm_sched_entity *entity); 585 void drm_sched_entity_select_rq(struct drm_sched_entity *entity); 586 struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity); 587 void drm_sched_entity_push_job(struct drm_sched_job *sched_job); 588 void drm_sched_entity_set_priority(struct drm_sched_entity *entity, 589 enum drm_sched_priority priority); 590 bool drm_sched_entity_is_ready(struct drm_sched_entity *entity); 591 592 void drm_sched_fence_set_parent(struct drm_sched_fence *s_fence, 593 struct dma_fence *fence); 594 struct drm_sched_fence *drm_sched_fence_alloc( 595 struct drm_sched_entity *s_entity, void *owner); 596 void drm_sched_fence_init(struct drm_sched_fence *fence, 597 struct drm_sched_entity *entity); 598 void drm_sched_fence_free(struct drm_sched_fence *fence); 599 600 void drm_sched_fence_scheduled(struct drm_sched_fence *fence); 601 void drm_sched_fence_finished(struct drm_sched_fence *fence); 602 603 unsigned long drm_sched_suspend_timeout(struct drm_gpu_scheduler *sched); 604 void drm_sched_resume_timeout(struct drm_gpu_scheduler *sched, 605 unsigned long remaining); 606 struct drm_gpu_scheduler * 607 drm_sched_pick_best(struct drm_gpu_scheduler **sched_list, 608 unsigned int num_sched_list); 609 610 #endif 611