1 /* 2 * Copyright © 2007-2008 Intel Corporation 3 * Jesse Barnes <jesse.barnes@intel.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef __DRM_EDID_H__ 24 #define __DRM_EDID_H__ 25 26 #include <linux/types.h> 27 #include <linux/hdmi.h> 28 #include <drm/drm_mode.h> 29 30 struct drm_device; 31 struct drm_edid; 32 struct i2c_adapter; 33 34 #define EDID_LENGTH 128 35 #define DDC_ADDR 0x50 36 #define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */ 37 38 #define CEA_EXT 0x02 39 #define VTB_EXT 0x10 40 #define DI_EXT 0x40 41 #define LS_EXT 0x50 42 #define MI_EXT 0x60 43 #define DISPLAYID_EXT 0x70 44 45 struct est_timings { 46 u8 t1; 47 u8 t2; 48 u8 mfg_rsvd; 49 } __attribute__((packed)); 50 51 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ 52 #define EDID_TIMING_ASPECT_SHIFT 6 53 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) 54 55 /* need to add 60 */ 56 #define EDID_TIMING_VFREQ_SHIFT 0 57 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) 58 59 struct std_timing { 60 u8 hsize; /* need to multiply by 8 then add 248 */ 61 u8 vfreq_aspect; 62 } __attribute__((packed)); 63 64 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) 65 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 66 #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) 67 #define DRM_EDID_PT_STEREO (1 << 5) 68 #define DRM_EDID_PT_INTERLACED (1 << 7) 69 70 /* If detailed data is pixel timing */ 71 struct detailed_pixel_timing { 72 u8 hactive_lo; 73 u8 hblank_lo; 74 u8 hactive_hblank_hi; 75 u8 vactive_lo; 76 u8 vblank_lo; 77 u8 vactive_vblank_hi; 78 u8 hsync_offset_lo; 79 u8 hsync_pulse_width_lo; 80 u8 vsync_offset_pulse_width_lo; 81 u8 hsync_vsync_offset_pulse_width_hi; 82 u8 width_mm_lo; 83 u8 height_mm_lo; 84 u8 width_height_mm_hi; 85 u8 hborder; 86 u8 vborder; 87 u8 misc; 88 } __attribute__((packed)); 89 90 /* If it's not pixel timing, it'll be one of the below */ 91 struct detailed_data_string { 92 u8 str[13]; 93 } __attribute__((packed)); 94 95 #define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG 0x00 96 #define DRM_EDID_RANGE_LIMITS_ONLY_FLAG 0x01 97 #define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x02 98 #define DRM_EDID_CVT_SUPPORT_FLAG 0x04 99 100 struct detailed_data_monitor_range { 101 u8 min_vfreq; 102 u8 max_vfreq; 103 u8 min_hfreq_khz; 104 u8 max_hfreq_khz; 105 u8 pixel_clock_mhz; /* need to multiply by 10 */ 106 u8 flags; 107 union { 108 struct { 109 u8 reserved; 110 u8 hfreq_start_khz; /* need to multiply by 2 */ 111 u8 c; /* need to divide by 2 */ 112 __le16 m; 113 u8 k; 114 u8 j; /* need to divide by 2 */ 115 } __attribute__((packed)) gtf2; 116 struct { 117 u8 version; 118 u8 data1; /* high 6 bits: extra clock resolution */ 119 u8 data2; /* plus low 2 of above: max hactive */ 120 u8 supported_aspects; 121 u8 flags; /* preferred aspect and blanking support */ 122 u8 supported_scalings; 123 u8 preferred_refresh; 124 } __attribute__((packed)) cvt; 125 } __attribute__((packed)) formula; 126 } __attribute__((packed)); 127 128 struct detailed_data_wpindex { 129 u8 white_yx_lo; /* Lower 2 bits each */ 130 u8 white_x_hi; 131 u8 white_y_hi; 132 u8 gamma; /* need to divide by 100 then add 1 */ 133 } __attribute__((packed)); 134 135 struct detailed_data_color_point { 136 u8 windex1; 137 u8 wpindex1[3]; 138 u8 windex2; 139 u8 wpindex2[3]; 140 } __attribute__((packed)); 141 142 struct cvt_timing { 143 u8 code[3]; 144 } __attribute__((packed)); 145 146 struct detailed_non_pixel { 147 u8 pad1; 148 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name 149 fb=color point data, fa=standard timing data, 150 f9=undefined, f8=mfg. reserved */ 151 u8 pad2; 152 union { 153 struct detailed_data_string str; 154 struct detailed_data_monitor_range range; 155 struct detailed_data_wpindex color; 156 struct std_timing timings[6]; 157 struct cvt_timing cvt[4]; 158 } __attribute__((packed)) data; 159 } __attribute__((packed)); 160 161 #define EDID_DETAIL_EST_TIMINGS 0xf7 162 #define EDID_DETAIL_CVT_3BYTE 0xf8 163 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 164 #define EDID_DETAIL_STD_MODES 0xfa 165 #define EDID_DETAIL_MONITOR_CPDATA 0xfb 166 #define EDID_DETAIL_MONITOR_NAME 0xfc 167 #define EDID_DETAIL_MONITOR_RANGE 0xfd 168 #define EDID_DETAIL_MONITOR_STRING 0xfe 169 #define EDID_DETAIL_MONITOR_SERIAL 0xff 170 171 struct detailed_timing { 172 __le16 pixel_clock; /* need to multiply by 10 KHz */ 173 union { 174 struct detailed_pixel_timing pixel_data; 175 struct detailed_non_pixel other_data; 176 } __attribute__((packed)) data; 177 } __attribute__((packed)); 178 179 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) 180 #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) 181 #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) 182 #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) 183 #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) 184 #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) 185 #define DRM_EDID_INPUT_DIGITAL (1 << 7) 186 #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) /* 1.4 */ 187 #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) /* 1.4 */ 188 #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) /* 1.4 */ 189 #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) /* 1.4 */ 190 #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) /* 1.4 */ 191 #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) /* 1.4 */ 192 #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) /* 1.4 */ 193 #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) /* 1.4 */ 194 #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) /* 1.4 */ 195 #define DRM_EDID_DIGITAL_TYPE_MASK (7 << 0) /* 1.4 */ 196 #define DRM_EDID_DIGITAL_TYPE_UNDEF (0 << 0) /* 1.4 */ 197 #define DRM_EDID_DIGITAL_TYPE_DVI (1 << 0) /* 1.4 */ 198 #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2 << 0) /* 1.4 */ 199 #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3 << 0) /* 1.4 */ 200 #define DRM_EDID_DIGITAL_TYPE_MDDI (4 << 0) /* 1.4 */ 201 #define DRM_EDID_DIGITAL_TYPE_DP (5 << 0) /* 1.4 */ 202 #define DRM_EDID_DIGITAL_DFP_1_X (1 << 0) /* 1.3 */ 203 204 #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) 205 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) 206 #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) 207 /* If analog */ 208 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ 209 /* If digital */ 210 #define DRM_EDID_FEATURE_COLOR_MASK (3 << 3) 211 #define DRM_EDID_FEATURE_RGB (0 << 3) 212 #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3) 213 #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3) 214 #define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */ 215 216 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) 217 #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) 218 #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) 219 220 #define DRM_EDID_HDMI_DC_48 (1 << 6) 221 #define DRM_EDID_HDMI_DC_36 (1 << 5) 222 #define DRM_EDID_HDMI_DC_30 (1 << 4) 223 #define DRM_EDID_HDMI_DC_Y444 (1 << 3) 224 225 /* YCBCR 420 deep color modes */ 226 #define DRM_EDID_YCBCR420_DC_48 (1 << 2) 227 #define DRM_EDID_YCBCR420_DC_36 (1 << 1) 228 #define DRM_EDID_YCBCR420_DC_30 (1 << 0) 229 #define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \ 230 DRM_EDID_YCBCR420_DC_36 | \ 231 DRM_EDID_YCBCR420_DC_30) 232 233 /* HDMI 2.1 additional fields */ 234 #define DRM_EDID_MAX_FRL_RATE_MASK 0xf0 235 #define DRM_EDID_FAPA_START_LOCATION (1 << 0) 236 #define DRM_EDID_ALLM (1 << 1) 237 #define DRM_EDID_FVA (1 << 2) 238 239 /* Deep Color specific */ 240 #define DRM_EDID_DC_30BIT_420 (1 << 0) 241 #define DRM_EDID_DC_36BIT_420 (1 << 1) 242 #define DRM_EDID_DC_48BIT_420 (1 << 2) 243 244 /* VRR specific */ 245 #define DRM_EDID_CNMVRR (1 << 3) 246 #define DRM_EDID_CINEMA_VRR (1 << 4) 247 #define DRM_EDID_MDELTA (1 << 5) 248 #define DRM_EDID_VRR_MAX_UPPER_MASK 0xc0 249 #define DRM_EDID_VRR_MAX_LOWER_MASK 0xff 250 #define DRM_EDID_VRR_MIN_MASK 0x3f 251 252 /* DSC specific */ 253 #define DRM_EDID_DSC_10BPC (1 << 0) 254 #define DRM_EDID_DSC_12BPC (1 << 1) 255 #define DRM_EDID_DSC_16BPC (1 << 2) 256 #define DRM_EDID_DSC_ALL_BPP (1 << 3) 257 #define DRM_EDID_DSC_NATIVE_420 (1 << 6) 258 #define DRM_EDID_DSC_1P2 (1 << 7) 259 #define DRM_EDID_DSC_MAX_FRL_RATE_MASK 0xf0 260 #define DRM_EDID_DSC_MAX_SLICES 0xf 261 #define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 0x3f 262 263 /* ELD Header Block */ 264 #define DRM_ELD_HEADER_BLOCK_SIZE 4 265 266 #define DRM_ELD_VER 0 267 # define DRM_ELD_VER_SHIFT 3 268 # define DRM_ELD_VER_MASK (0x1f << 3) 269 # define DRM_ELD_VER_CEA861D (2 << 3) /* supports 861D or below */ 270 # define DRM_ELD_VER_CANNED (0x1f << 3) 271 272 #define DRM_ELD_BASELINE_ELD_LEN 2 /* in dwords! */ 273 274 /* ELD Baseline Block for ELD_Ver == 2 */ 275 #define DRM_ELD_CEA_EDID_VER_MNL 4 276 # define DRM_ELD_CEA_EDID_VER_SHIFT 5 277 # define DRM_ELD_CEA_EDID_VER_MASK (7 << 5) 278 # define DRM_ELD_CEA_EDID_VER_NONE (0 << 5) 279 # define DRM_ELD_CEA_EDID_VER_CEA861 (1 << 5) 280 # define DRM_ELD_CEA_EDID_VER_CEA861A (2 << 5) 281 # define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5) 282 # define DRM_ELD_MNL_SHIFT 0 283 # define DRM_ELD_MNL_MASK (0x1f << 0) 284 285 #define DRM_ELD_SAD_COUNT_CONN_TYPE 5 286 # define DRM_ELD_SAD_COUNT_SHIFT 4 287 # define DRM_ELD_SAD_COUNT_MASK (0xf << 4) 288 # define DRM_ELD_CONN_TYPE_SHIFT 2 289 # define DRM_ELD_CONN_TYPE_MASK (3 << 2) 290 # define DRM_ELD_CONN_TYPE_HDMI (0 << 2) 291 # define DRM_ELD_CONN_TYPE_DP (1 << 2) 292 # define DRM_ELD_SUPPORTS_AI (1 << 1) 293 # define DRM_ELD_SUPPORTS_HDCP (1 << 0) 294 295 #define DRM_ELD_AUD_SYNCH_DELAY 6 /* in units of 2 ms */ 296 # define DRM_ELD_AUD_SYNCH_DELAY_MAX 0xfa /* 500 ms */ 297 298 #define DRM_ELD_SPEAKER 7 299 # define DRM_ELD_SPEAKER_MASK 0x7f 300 # define DRM_ELD_SPEAKER_RLRC (1 << 6) 301 # define DRM_ELD_SPEAKER_FLRC (1 << 5) 302 # define DRM_ELD_SPEAKER_RC (1 << 4) 303 # define DRM_ELD_SPEAKER_RLR (1 << 3) 304 # define DRM_ELD_SPEAKER_FC (1 << 2) 305 # define DRM_ELD_SPEAKER_LFE (1 << 1) 306 # define DRM_ELD_SPEAKER_FLR (1 << 0) 307 308 #define DRM_ELD_PORT_ID 8 /* offsets 8..15 inclusive */ 309 # define DRM_ELD_PORT_ID_LEN 8 310 311 #define DRM_ELD_MANUFACTURER_NAME0 16 312 #define DRM_ELD_MANUFACTURER_NAME1 17 313 314 #define DRM_ELD_PRODUCT_CODE0 18 315 #define DRM_ELD_PRODUCT_CODE1 19 316 317 #define DRM_ELD_MONITOR_NAME_STRING 20 /* offsets 20..(20+mnl-1) inclusive */ 318 319 #define DRM_ELD_CEA_SAD(mnl, sad) (20 + (mnl) + 3 * (sad)) 320 321 struct edid { 322 u8 header[8]; 323 /* Vendor & product info */ 324 u8 mfg_id[2]; 325 u8 prod_code[2]; 326 u32 serial; /* FIXME: byte order */ 327 u8 mfg_week; 328 u8 mfg_year; 329 /* EDID version */ 330 u8 version; 331 u8 revision; 332 /* Display info: */ 333 u8 input; 334 u8 width_cm; 335 u8 height_cm; 336 u8 gamma; 337 u8 features; 338 /* Color characteristics */ 339 u8 red_green_lo; 340 u8 blue_white_lo; 341 u8 red_x; 342 u8 red_y; 343 u8 green_x; 344 u8 green_y; 345 u8 blue_x; 346 u8 blue_y; 347 u8 white_x; 348 u8 white_y; 349 /* Est. timings and mfg rsvd timings*/ 350 struct est_timings established_timings; 351 /* Standard timings 1-8*/ 352 struct std_timing standard_timings[8]; 353 /* Detailing timings 1-4 */ 354 struct detailed_timing detailed_timings[4]; 355 /* Number of 128 byte ext. blocks */ 356 u8 extensions; 357 /* Checksum */ 358 u8 checksum; 359 } __attribute__((packed)); 360 361 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 362 363 /* Short Audio Descriptor */ 364 struct cea_sad { 365 u8 format; 366 u8 channels; /* max number of channels - 1 */ 367 u8 freq; 368 u8 byte2; /* meaning depends on format */ 369 }; 370 371 struct drm_encoder; 372 struct drm_connector; 373 struct drm_connector_state; 374 struct drm_display_mode; 375 376 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads); 377 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb); 378 int drm_av_sync_delay(struct drm_connector *connector, 379 const struct drm_display_mode *mode); 380 381 #ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE 382 struct edid *drm_load_edid_firmware(struct drm_connector *connector); 383 int __drm_set_edid_firmware_path(const char *path); 384 int __drm_get_edid_firmware_path(char *buf, size_t bufsize); 385 #else 386 static inline struct edid * 387 drm_load_edid_firmware(struct drm_connector *connector) 388 { 389 return ERR_PTR(-ENOENT); 390 } 391 #endif 392 393 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2); 394 395 int 396 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 397 const struct drm_connector *connector, 398 const struct drm_display_mode *mode); 399 int 400 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 401 const struct drm_connector *connector, 402 const struct drm_display_mode *mode); 403 404 void 405 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 406 const struct drm_connector *connector, 407 const struct drm_display_mode *mode, 408 enum hdmi_quantization_range rgb_quant_range); 409 410 /** 411 * drm_eld_mnl - Get ELD monitor name length in bytes. 412 * @eld: pointer to an eld memory structure with mnl set 413 */ 414 static inline int drm_eld_mnl(const uint8_t *eld) 415 { 416 return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT; 417 } 418 419 /** 420 * drm_eld_sad - Get ELD SAD structures. 421 * @eld: pointer to an eld memory structure with sad_count set 422 */ 423 static inline const uint8_t *drm_eld_sad(const uint8_t *eld) 424 { 425 unsigned int ver, mnl; 426 427 ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT; 428 if (ver != 2 && ver != 31) 429 return NULL; 430 431 mnl = drm_eld_mnl(eld); 432 if (mnl > 16) 433 return NULL; 434 435 return eld + DRM_ELD_CEA_SAD(mnl, 0); 436 } 437 438 /** 439 * drm_eld_sad_count - Get ELD SAD count. 440 * @eld: pointer to an eld memory structure with sad_count set 441 */ 442 static inline int drm_eld_sad_count(const uint8_t *eld) 443 { 444 return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >> 445 DRM_ELD_SAD_COUNT_SHIFT; 446 } 447 448 /** 449 * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes 450 * @eld: pointer to an eld memory structure with mnl and sad_count set 451 * 452 * This is a helper for determining the payload size of the baseline block, in 453 * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block. 454 */ 455 static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld) 456 { 457 return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE + 458 drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3; 459 } 460 461 /** 462 * drm_eld_size - Get ELD size in bytes 463 * @eld: pointer to a complete eld memory structure 464 * 465 * The returned value does not include the vendor block. It's vendor specific, 466 * and comprises of the remaining bytes in the ELD memory buffer after 467 * drm_eld_size() bytes of header and baseline block. 468 * 469 * The returned value is guaranteed to be a multiple of 4. 470 */ 471 static inline int drm_eld_size(const uint8_t *eld) 472 { 473 return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4; 474 } 475 476 /** 477 * drm_eld_get_spk_alloc - Get speaker allocation 478 * @eld: pointer to an ELD memory structure 479 * 480 * The returned value is the speakers mask. User has to use %DRM_ELD_SPEAKER 481 * field definitions to identify speakers. 482 */ 483 static inline u8 drm_eld_get_spk_alloc(const uint8_t *eld) 484 { 485 return eld[DRM_ELD_SPEAKER] & DRM_ELD_SPEAKER_MASK; 486 } 487 488 /** 489 * drm_eld_get_conn_type - Get device type hdmi/dp connected 490 * @eld: pointer to an ELD memory structure 491 * 492 * The caller need to use %DRM_ELD_CONN_TYPE_HDMI or %DRM_ELD_CONN_TYPE_DP to 493 * identify the display type connected. 494 */ 495 static inline u8 drm_eld_get_conn_type(const uint8_t *eld) 496 { 497 return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK; 498 } 499 500 /** 501 * drm_edid_decode_mfg_id - Decode the manufacturer ID 502 * @mfg_id: The manufacturer ID 503 * @vend: A 4-byte buffer to store the 3-letter vendor string plus a '\0' 504 * termination 505 */ 506 static inline const char *drm_edid_decode_mfg_id(u16 mfg_id, char vend[4]) 507 { 508 vend[0] = '@' + ((mfg_id >> 10) & 0x1f); 509 vend[1] = '@' + ((mfg_id >> 5) & 0x1f); 510 vend[2] = '@' + ((mfg_id >> 0) & 0x1f); 511 vend[3] = '\0'; 512 513 return vend; 514 } 515 516 /** 517 * drm_edid_encode_panel_id - Encode an ID for matching against drm_edid_get_panel_id() 518 * @vend_chr_0: First character of the vendor string. 519 * @vend_chr_1: Second character of the vendor string. 520 * @vend_chr_2: Third character of the vendor string. 521 * @product_id: The 16-bit product ID. 522 * 523 * This is a macro so that it can be calculated at compile time and used 524 * as an initializer. 525 * 526 * For instance: 527 * drm_edid_encode_panel_id('B', 'O', 'E', 0x2d08) => 0x09e52d08 528 * 529 * Return: a 32-bit ID per panel. 530 */ 531 #define drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, product_id) \ 532 ((((u32)(vend_chr_0) - '@') & 0x1f) << 26 | \ 533 (((u32)(vend_chr_1) - '@') & 0x1f) << 21 | \ 534 (((u32)(vend_chr_2) - '@') & 0x1f) << 16 | \ 535 ((product_id) & 0xffff)) 536 537 /** 538 * drm_edid_decode_panel_id - Decode a panel ID from drm_edid_encode_panel_id() 539 * @panel_id: The panel ID to decode. 540 * @vend: A 4-byte buffer to store the 3-letter vendor string plus a '\0' 541 * termination 542 * @product_id: The product ID will be returned here. 543 * 544 * For instance, after: 545 * drm_edid_decode_panel_id(0x09e52d08, vend, &product_id) 546 * These will be true: 547 * vend[0] = 'B' 548 * vend[1] = 'O' 549 * vend[2] = 'E' 550 * vend[3] = '\0' 551 * product_id = 0x2d08 552 */ 553 static inline void drm_edid_decode_panel_id(u32 panel_id, char vend[4], u16 *product_id) 554 { 555 *product_id = (u16)(panel_id & 0xffff); 556 drm_edid_decode_mfg_id(panel_id >> 16, vend); 557 } 558 559 bool drm_probe_ddc(struct i2c_adapter *adapter); 560 struct edid *drm_do_get_edid(struct drm_connector *connector, 561 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 562 size_t len), 563 void *data); 564 struct edid *drm_get_edid(struct drm_connector *connector, 565 struct i2c_adapter *adapter); 566 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter); 567 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 568 struct i2c_adapter *adapter); 569 struct edid *drm_edid_duplicate(const struct edid *edid); 570 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid); 571 int drm_add_override_edid_modes(struct drm_connector *connector); 572 573 u8 drm_match_cea_mode(const struct drm_display_mode *to_match); 574 bool drm_detect_hdmi_monitor(const struct edid *edid); 575 bool drm_detect_monitor_audio(const struct edid *edid); 576 enum hdmi_quantization_range 577 drm_default_rgb_quant_range(const struct drm_display_mode *mode); 578 int drm_add_modes_noedid(struct drm_connector *connector, 579 int hdisplay, int vdisplay); 580 void drm_set_preferred_mode(struct drm_connector *connector, 581 int hpref, int vpref); 582 583 int drm_edid_header_is_valid(const void *edid); 584 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 585 bool *edid_corrupt); 586 bool drm_edid_is_valid(struct edid *edid); 587 void drm_edid_get_monitor_name(const struct edid *edid, char *name, 588 int buflen); 589 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 590 int hsize, int vsize, int fresh, 591 bool rb); 592 struct drm_display_mode * 593 drm_display_mode_from_cea_vic(struct drm_device *dev, 594 u8 video_code); 595 596 /* Interface based on struct drm_edid */ 597 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size); 598 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid); 599 void drm_edid_free(const struct drm_edid *drm_edid); 600 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid); 601 const struct drm_edid *drm_edid_read(struct drm_connector *connector); 602 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, 603 struct i2c_adapter *adapter); 604 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, 605 int (*read_block)(void *context, u8 *buf, unsigned int block, size_t len), 606 void *context); 607 int drm_edid_connector_update(struct drm_connector *connector, 608 const struct drm_edid *edid); 609 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid, 610 int ext_id, int *ext_index); 611 612 #endif /* __DRM_EDID_H__ */ 613