1 /* 2 * Copyright © 2007-2008 Intel Corporation 3 * Jesse Barnes <jesse.barnes@intel.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef __DRM_EDID_H__ 24 #define __DRM_EDID_H__ 25 26 #include <linux/types.h> 27 #include <linux/hdmi.h> 28 #include <drm/drm_mode.h> 29 30 struct drm_device; 31 struct i2c_adapter; 32 33 #define EDID_LENGTH 128 34 #define DDC_ADDR 0x50 35 #define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */ 36 37 #define CEA_EXT 0x02 38 #define VTB_EXT 0x10 39 #define DI_EXT 0x40 40 #define LS_EXT 0x50 41 #define MI_EXT 0x60 42 #define DISPLAYID_EXT 0x70 43 44 struct est_timings { 45 u8 t1; 46 u8 t2; 47 u8 mfg_rsvd; 48 } __attribute__((packed)); 49 50 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ 51 #define EDID_TIMING_ASPECT_SHIFT 6 52 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) 53 54 /* need to add 60 */ 55 #define EDID_TIMING_VFREQ_SHIFT 0 56 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) 57 58 struct std_timing { 59 u8 hsize; /* need to multiply by 8 then add 248 */ 60 u8 vfreq_aspect; 61 } __attribute__((packed)); 62 63 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) 64 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 65 #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) 66 #define DRM_EDID_PT_STEREO (1 << 5) 67 #define DRM_EDID_PT_INTERLACED (1 << 7) 68 69 /* If detailed data is pixel timing */ 70 struct detailed_pixel_timing { 71 u8 hactive_lo; 72 u8 hblank_lo; 73 u8 hactive_hblank_hi; 74 u8 vactive_lo; 75 u8 vblank_lo; 76 u8 vactive_vblank_hi; 77 u8 hsync_offset_lo; 78 u8 hsync_pulse_width_lo; 79 u8 vsync_offset_pulse_width_lo; 80 u8 hsync_vsync_offset_pulse_width_hi; 81 u8 width_mm_lo; 82 u8 height_mm_lo; 83 u8 width_height_mm_hi; 84 u8 hborder; 85 u8 vborder; 86 u8 misc; 87 } __attribute__((packed)); 88 89 /* If it's not pixel timing, it'll be one of the below */ 90 struct detailed_data_string { 91 u8 str[13]; 92 } __attribute__((packed)); 93 94 struct detailed_data_monitor_range { 95 u8 min_vfreq; 96 u8 max_vfreq; 97 u8 min_hfreq_khz; 98 u8 max_hfreq_khz; 99 u8 pixel_clock_mhz; /* need to multiply by 10 */ 100 u8 flags; 101 union { 102 struct { 103 u8 reserved; 104 u8 hfreq_start_khz; /* need to multiply by 2 */ 105 u8 c; /* need to divide by 2 */ 106 __le16 m; 107 u8 k; 108 u8 j; /* need to divide by 2 */ 109 } __attribute__((packed)) gtf2; 110 struct { 111 u8 version; 112 u8 data1; /* high 6 bits: extra clock resolution */ 113 u8 data2; /* plus low 2 of above: max hactive */ 114 u8 supported_aspects; 115 u8 flags; /* preferred aspect and blanking support */ 116 u8 supported_scalings; 117 u8 preferred_refresh; 118 } __attribute__((packed)) cvt; 119 } formula; 120 } __attribute__((packed)); 121 122 struct detailed_data_wpindex { 123 u8 white_yx_lo; /* Lower 2 bits each */ 124 u8 white_x_hi; 125 u8 white_y_hi; 126 u8 gamma; /* need to divide by 100 then add 1 */ 127 } __attribute__((packed)); 128 129 struct detailed_data_color_point { 130 u8 windex1; 131 u8 wpindex1[3]; 132 u8 windex2; 133 u8 wpindex2[3]; 134 } __attribute__((packed)); 135 136 struct cvt_timing { 137 u8 code[3]; 138 } __attribute__((packed)); 139 140 struct detailed_non_pixel { 141 u8 pad1; 142 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name 143 fb=color point data, fa=standard timing data, 144 f9=undefined, f8=mfg. reserved */ 145 u8 pad2; 146 union { 147 struct detailed_data_string str; 148 struct detailed_data_monitor_range range; 149 struct detailed_data_wpindex color; 150 struct std_timing timings[6]; 151 struct cvt_timing cvt[4]; 152 } data; 153 } __attribute__((packed)); 154 155 #define EDID_DETAIL_EST_TIMINGS 0xf7 156 #define EDID_DETAIL_CVT_3BYTE 0xf8 157 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 158 #define EDID_DETAIL_STD_MODES 0xfa 159 #define EDID_DETAIL_MONITOR_CPDATA 0xfb 160 #define EDID_DETAIL_MONITOR_NAME 0xfc 161 #define EDID_DETAIL_MONITOR_RANGE 0xfd 162 #define EDID_DETAIL_MONITOR_STRING 0xfe 163 #define EDID_DETAIL_MONITOR_SERIAL 0xff 164 165 struct detailed_timing { 166 __le16 pixel_clock; /* need to multiply by 10 KHz */ 167 union { 168 struct detailed_pixel_timing pixel_data; 169 struct detailed_non_pixel other_data; 170 } data; 171 } __attribute__((packed)); 172 173 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) 174 #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) 175 #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) 176 #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) 177 #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) 178 #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) 179 #define DRM_EDID_INPUT_DIGITAL (1 << 7) 180 #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) /* 1.4 */ 181 #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) /* 1.4 */ 182 #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) /* 1.4 */ 183 #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) /* 1.4 */ 184 #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) /* 1.4 */ 185 #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) /* 1.4 */ 186 #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) /* 1.4 */ 187 #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) /* 1.4 */ 188 #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) /* 1.4 */ 189 #define DRM_EDID_DIGITAL_TYPE_MASK (7 << 0) /* 1.4 */ 190 #define DRM_EDID_DIGITAL_TYPE_UNDEF (0 << 0) /* 1.4 */ 191 #define DRM_EDID_DIGITAL_TYPE_DVI (1 << 0) /* 1.4 */ 192 #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2 << 0) /* 1.4 */ 193 #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3 << 0) /* 1.4 */ 194 #define DRM_EDID_DIGITAL_TYPE_MDDI (4 << 0) /* 1.4 */ 195 #define DRM_EDID_DIGITAL_TYPE_DP (5 << 0) /* 1.4 */ 196 #define DRM_EDID_DIGITAL_DFP_1_X (1 << 0) /* 1.3 */ 197 198 #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) 199 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) 200 #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) 201 /* If analog */ 202 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ 203 /* If digital */ 204 #define DRM_EDID_FEATURE_COLOR_MASK (3 << 3) 205 #define DRM_EDID_FEATURE_RGB (0 << 3) 206 #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3) 207 #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3) 208 #define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */ 209 210 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) 211 #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) 212 #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) 213 214 #define DRM_EDID_HDMI_DC_48 (1 << 6) 215 #define DRM_EDID_HDMI_DC_36 (1 << 5) 216 #define DRM_EDID_HDMI_DC_30 (1 << 4) 217 #define DRM_EDID_HDMI_DC_Y444 (1 << 3) 218 219 /* YCBCR 420 deep color modes */ 220 #define DRM_EDID_YCBCR420_DC_48 (1 << 2) 221 #define DRM_EDID_YCBCR420_DC_36 (1 << 1) 222 #define DRM_EDID_YCBCR420_DC_30 (1 << 0) 223 #define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \ 224 DRM_EDID_YCBCR420_DC_36 | \ 225 DRM_EDID_YCBCR420_DC_30) 226 227 /* ELD Header Block */ 228 #define DRM_ELD_HEADER_BLOCK_SIZE 4 229 230 #define DRM_ELD_VER 0 231 # define DRM_ELD_VER_SHIFT 3 232 # define DRM_ELD_VER_MASK (0x1f << 3) 233 # define DRM_ELD_VER_CEA861D (2 << 3) /* supports 861D or below */ 234 # define DRM_ELD_VER_CANNED (0x1f << 3) 235 236 #define DRM_ELD_BASELINE_ELD_LEN 2 /* in dwords! */ 237 238 /* ELD Baseline Block for ELD_Ver == 2 */ 239 #define DRM_ELD_CEA_EDID_VER_MNL 4 240 # define DRM_ELD_CEA_EDID_VER_SHIFT 5 241 # define DRM_ELD_CEA_EDID_VER_MASK (7 << 5) 242 # define DRM_ELD_CEA_EDID_VER_NONE (0 << 5) 243 # define DRM_ELD_CEA_EDID_VER_CEA861 (1 << 5) 244 # define DRM_ELD_CEA_EDID_VER_CEA861A (2 << 5) 245 # define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5) 246 # define DRM_ELD_MNL_SHIFT 0 247 # define DRM_ELD_MNL_MASK (0x1f << 0) 248 249 #define DRM_ELD_SAD_COUNT_CONN_TYPE 5 250 # define DRM_ELD_SAD_COUNT_SHIFT 4 251 # define DRM_ELD_SAD_COUNT_MASK (0xf << 4) 252 # define DRM_ELD_CONN_TYPE_SHIFT 2 253 # define DRM_ELD_CONN_TYPE_MASK (3 << 2) 254 # define DRM_ELD_CONN_TYPE_HDMI (0 << 2) 255 # define DRM_ELD_CONN_TYPE_DP (1 << 2) 256 # define DRM_ELD_SUPPORTS_AI (1 << 1) 257 # define DRM_ELD_SUPPORTS_HDCP (1 << 0) 258 259 #define DRM_ELD_AUD_SYNCH_DELAY 6 /* in units of 2 ms */ 260 # define DRM_ELD_AUD_SYNCH_DELAY_MAX 0xfa /* 500 ms */ 261 262 #define DRM_ELD_SPEAKER 7 263 # define DRM_ELD_SPEAKER_MASK 0x7f 264 # define DRM_ELD_SPEAKER_RLRC (1 << 6) 265 # define DRM_ELD_SPEAKER_FLRC (1 << 5) 266 # define DRM_ELD_SPEAKER_RC (1 << 4) 267 # define DRM_ELD_SPEAKER_RLR (1 << 3) 268 # define DRM_ELD_SPEAKER_FC (1 << 2) 269 # define DRM_ELD_SPEAKER_LFE (1 << 1) 270 # define DRM_ELD_SPEAKER_FLR (1 << 0) 271 272 #define DRM_ELD_PORT_ID 8 /* offsets 8..15 inclusive */ 273 # define DRM_ELD_PORT_ID_LEN 8 274 275 #define DRM_ELD_MANUFACTURER_NAME0 16 276 #define DRM_ELD_MANUFACTURER_NAME1 17 277 278 #define DRM_ELD_PRODUCT_CODE0 18 279 #define DRM_ELD_PRODUCT_CODE1 19 280 281 #define DRM_ELD_MONITOR_NAME_STRING 20 /* offsets 20..(20+mnl-1) inclusive */ 282 283 #define DRM_ELD_CEA_SAD(mnl, sad) (20 + (mnl) + 3 * (sad)) 284 285 struct edid { 286 u8 header[8]; 287 /* Vendor & product info */ 288 u8 mfg_id[2]; 289 u8 prod_code[2]; 290 u32 serial; /* FIXME: byte order */ 291 u8 mfg_week; 292 u8 mfg_year; 293 /* EDID version */ 294 u8 version; 295 u8 revision; 296 /* Display info: */ 297 u8 input; 298 u8 width_cm; 299 u8 height_cm; 300 u8 gamma; 301 u8 features; 302 /* Color characteristics */ 303 u8 red_green_lo; 304 u8 black_white_lo; 305 u8 red_x; 306 u8 red_y; 307 u8 green_x; 308 u8 green_y; 309 u8 blue_x; 310 u8 blue_y; 311 u8 white_x; 312 u8 white_y; 313 /* Est. timings and mfg rsvd timings*/ 314 struct est_timings established_timings; 315 /* Standard timings 1-8*/ 316 struct std_timing standard_timings[8]; 317 /* Detailing timings 1-4 */ 318 struct detailed_timing detailed_timings[4]; 319 /* Number of 128 byte ext. blocks */ 320 u8 extensions; 321 /* Checksum */ 322 u8 checksum; 323 } __attribute__((packed)); 324 325 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 326 327 /* Short Audio Descriptor */ 328 struct cea_sad { 329 u8 format; 330 u8 channels; /* max number of channels - 1 */ 331 u8 freq; 332 u8 byte2; /* meaning depends on format */ 333 }; 334 335 struct drm_encoder; 336 struct drm_connector; 337 struct drm_connector_state; 338 struct drm_display_mode; 339 340 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads); 341 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb); 342 int drm_av_sync_delay(struct drm_connector *connector, 343 const struct drm_display_mode *mode); 344 345 #ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE 346 struct edid *drm_load_edid_firmware(struct drm_connector *connector); 347 int __drm_set_edid_firmware_path(const char *path); 348 int __drm_get_edid_firmware_path(char *buf, size_t bufsize); 349 #else 350 static inline struct edid * 351 drm_load_edid_firmware(struct drm_connector *connector) 352 { 353 return ERR_PTR(-ENOENT); 354 } 355 #endif 356 357 int 358 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 359 struct drm_connector *connector, 360 const struct drm_display_mode *mode); 361 int 362 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 363 struct drm_connector *connector, 364 const struct drm_display_mode *mode); 365 366 void 367 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 368 const struct drm_connector_state *conn_state); 369 370 void 371 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 372 struct drm_connector *connector, 373 const struct drm_display_mode *mode, 374 enum hdmi_quantization_range rgb_quant_range); 375 376 int 377 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 378 const struct drm_connector_state *conn_state); 379 380 /** 381 * drm_eld_mnl - Get ELD monitor name length in bytes. 382 * @eld: pointer to an eld memory structure with mnl set 383 */ 384 static inline int drm_eld_mnl(const uint8_t *eld) 385 { 386 return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT; 387 } 388 389 /** 390 * drm_eld_sad - Get ELD SAD structures. 391 * @eld: pointer to an eld memory structure with sad_count set 392 */ 393 static inline const uint8_t *drm_eld_sad(const uint8_t *eld) 394 { 395 unsigned int ver, mnl; 396 397 ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT; 398 if (ver != 2 && ver != 31) 399 return NULL; 400 401 mnl = drm_eld_mnl(eld); 402 if (mnl > 16) 403 return NULL; 404 405 return eld + DRM_ELD_CEA_SAD(mnl, 0); 406 } 407 408 /** 409 * drm_eld_sad_count - Get ELD SAD count. 410 * @eld: pointer to an eld memory structure with sad_count set 411 */ 412 static inline int drm_eld_sad_count(const uint8_t *eld) 413 { 414 return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >> 415 DRM_ELD_SAD_COUNT_SHIFT; 416 } 417 418 /** 419 * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes 420 * @eld: pointer to an eld memory structure with mnl and sad_count set 421 * 422 * This is a helper for determining the payload size of the baseline block, in 423 * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block. 424 */ 425 static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld) 426 { 427 return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE + 428 drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3; 429 } 430 431 /** 432 * drm_eld_size - Get ELD size in bytes 433 * @eld: pointer to a complete eld memory structure 434 * 435 * The returned value does not include the vendor block. It's vendor specific, 436 * and comprises of the remaining bytes in the ELD memory buffer after 437 * drm_eld_size() bytes of header and baseline block. 438 * 439 * The returned value is guaranteed to be a multiple of 4. 440 */ 441 static inline int drm_eld_size(const uint8_t *eld) 442 { 443 return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4; 444 } 445 446 /** 447 * drm_eld_get_spk_alloc - Get speaker allocation 448 * @eld: pointer to an ELD memory structure 449 * 450 * The returned value is the speakers mask. User has to use %DRM_ELD_SPEAKER 451 * field definitions to identify speakers. 452 */ 453 static inline u8 drm_eld_get_spk_alloc(const uint8_t *eld) 454 { 455 return eld[DRM_ELD_SPEAKER] & DRM_ELD_SPEAKER_MASK; 456 } 457 458 /** 459 * drm_eld_get_conn_type - Get device type hdmi/dp connected 460 * @eld: pointer to an ELD memory structure 461 * 462 * The caller need to use %DRM_ELD_CONN_TYPE_HDMI or %DRM_ELD_CONN_TYPE_DP to 463 * identify the display type connected. 464 */ 465 static inline u8 drm_eld_get_conn_type(const uint8_t *eld) 466 { 467 return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK; 468 } 469 470 bool drm_probe_ddc(struct i2c_adapter *adapter); 471 struct edid *drm_do_get_edid(struct drm_connector *connector, 472 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 473 size_t len), 474 void *data); 475 struct edid *drm_get_edid(struct drm_connector *connector, 476 struct i2c_adapter *adapter); 477 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 478 struct i2c_adapter *adapter); 479 struct edid *drm_edid_duplicate(const struct edid *edid); 480 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid); 481 int drm_add_override_edid_modes(struct drm_connector *connector); 482 483 u8 drm_match_cea_mode(const struct drm_display_mode *to_match); 484 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code); 485 bool drm_detect_hdmi_monitor(struct edid *edid); 486 bool drm_detect_monitor_audio(struct edid *edid); 487 enum hdmi_quantization_range 488 drm_default_rgb_quant_range(const struct drm_display_mode *mode); 489 int drm_add_modes_noedid(struct drm_connector *connector, 490 int hdisplay, int vdisplay); 491 void drm_set_preferred_mode(struct drm_connector *connector, 492 int hpref, int vpref); 493 494 int drm_edid_header_is_valid(const u8 *raw_edid); 495 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 496 bool *edid_corrupt); 497 bool drm_edid_is_valid(struct edid *edid); 498 void drm_edid_get_monitor_name(struct edid *edid, char *name, 499 int buflen); 500 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 501 int hsize, int vsize, int fresh, 502 bool rb); 503 #endif /* __DRM_EDID_H__ */ 504