xref: /openbmc/linux/include/drm/drm_cache.h (revision bcda5fd3)
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3  * Copyright 2009 Red Hat Inc.
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28 /*
29  * Authors:
30  * Dave Airlie <airlied@redhat.com>
31  */
32 
33 #ifndef _DRM_CACHE_H_
34 #define _DRM_CACHE_H_
35 
36 #include <linux/scatterlist.h>
37 
38 struct dma_buf_map;
39 
40 void drm_clflush_pages(struct page *pages[], unsigned long num_pages);
41 void drm_clflush_sg(struct sg_table *st);
42 void drm_clflush_virt_range(void *addr, unsigned long length);
43 bool drm_need_swiotlb(int dma_bits);
44 
45 
46 static inline bool drm_arch_can_wc_memory(void)
47 {
48 #if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE)
49 	return false;
50 #elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON64)
51 	return false;
52 #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64)
53 	/*
54 	 * The DRM driver stack is designed to work with cache coherent devices
55 	 * only, but permits an optimization to be enabled in some cases, where
56 	 * for some buffers, both the CPU and the GPU use uncached mappings,
57 	 * removing the need for DMA snooping and allocation in the CPU caches.
58 	 *
59 	 * The use of uncached GPU mappings relies on the correct implementation
60 	 * of the PCIe NoSnoop TLP attribute by the platform, otherwise the GPU
61 	 * will use cached mappings nonetheless. On x86 platforms, this does not
62 	 * seem to matter, as uncached CPU mappings will snoop the caches in any
63 	 * case. However, on ARM and arm64, enabling this optimization on a
64 	 * platform where NoSnoop is ignored results in loss of coherency, which
65 	 * breaks correct operation of the device. Since we have no way of
66 	 * detecting whether NoSnoop works or not, just disable this
67 	 * optimization entirely for ARM and arm64.
68 	 */
69 	return false;
70 #else
71 	return true;
72 #endif
73 }
74 
75 void drm_memcpy_init_early(void);
76 
77 void drm_memcpy_from_wc(struct dma_buf_map *dst,
78 			const struct dma_buf_map *src,
79 			unsigned long len);
80 #endif
81