1 /* 2 * Copyright © 2008 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #ifndef _DRM_DP_HELPER_H_ 24 #define _DRM_DP_HELPER_H_ 25 26 #include <linux/delay.h> 27 #include <linux/i2c.h> 28 29 #include <drm/display/drm_dp.h> 30 #include <drm/drm_connector.h> 31 32 struct drm_device; 33 struct drm_dp_aux; 34 struct drm_panel; 35 36 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 37 int lane_count); 38 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 39 int lane_count); 40 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 41 int lane); 42 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 43 int lane); 44 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], 45 int lane); 46 47 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 48 enum drm_dp_phy dp_phy, bool uhbr); 49 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 50 enum drm_dp_phy dp_phy, bool uhbr); 51 52 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, 53 const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 54 void drm_dp_lttpr_link_train_clock_recovery_delay(void); 55 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 56 const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 57 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 58 const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 59 60 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux); 61 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE], 62 int lane_count); 63 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE], 64 int lane_count); 65 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); 66 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); 67 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]); 68 69 u8 drm_dp_link_rate_to_bw_code(int link_rate); 70 int drm_dp_bw_code_to_link_rate(u8 link_bw); 71 72 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy); 73 74 /** 75 * struct drm_dp_vsc_sdp - drm DP VSC SDP 76 * 77 * This structure represents a DP VSC SDP of drm 78 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and 79 * [Table 2-117: VSC SDP Payload for DB16 through DB18] 80 * 81 * @sdp_type: secondary-data packet type 82 * @revision: revision number 83 * @length: number of valid data bytes 84 * @pixelformat: pixel encoding format 85 * @colorimetry: colorimetry format 86 * @bpc: bit per color 87 * @dynamic_range: dynamic range information 88 * @content_type: CTA-861-G defines content types and expected processing by a sink device 89 */ 90 struct drm_dp_vsc_sdp { 91 unsigned char sdp_type; 92 unsigned char revision; 93 unsigned char length; 94 enum dp_pixelformat pixelformat; 95 enum dp_colorimetry colorimetry; 96 int bpc; 97 enum dp_dynamic_range dynamic_range; 98 enum dp_content_type content_type; 99 }; 100 101 void drm_dp_vsc_sdp_log(const char *level, struct device *dev, 102 const struct drm_dp_vsc_sdp *vsc); 103 104 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]); 105 106 static inline int 107 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 108 { 109 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); 110 } 111 112 static inline u8 113 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 114 { 115 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 116 } 117 118 static inline bool 119 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 120 { 121 return dpcd[DP_DPCD_REV] >= 0x11 && 122 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); 123 } 124 125 static inline bool 126 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 127 { 128 return dpcd[DP_DPCD_REV] >= 0x11 && 129 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING); 130 } 131 132 static inline bool 133 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 134 { 135 return dpcd[DP_DPCD_REV] >= 0x12 && 136 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; 137 } 138 139 static inline bool 140 drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 141 { 142 return dpcd[DP_DPCD_REV] >= 0x11 || 143 dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5; 144 } 145 146 static inline bool 147 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 148 { 149 return dpcd[DP_DPCD_REV] >= 0x14 && 150 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED; 151 } 152 153 static inline u8 154 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 155 { 156 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : 157 DP_TRAINING_PATTERN_MASK; 158 } 159 160 static inline bool 161 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 162 { 163 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; 164 } 165 166 /* DP/eDP DSC support */ 167 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 168 bool is_edp); 169 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); 170 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], 171 u8 dsc_bpc[3]); 172 173 static inline bool 174 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 175 { 176 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & 177 DP_DSC_DECOMPRESSION_IS_SUPPORTED; 178 } 179 180 static inline u16 181 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 182 { 183 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | 184 (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & 185 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK << 186 DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT); 187 } 188 189 static inline u32 190 drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 191 { 192 /* Max Slicewidth = Number of Pixels * 320 */ 193 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * 194 DP_DSC_SLICE_WIDTH_MULTIPLIER; 195 } 196 197 /** 198 * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format 199 * @dsc_dpcd : DSC-capability DPCDs of the sink 200 * @output_format: output_format which is to be checked 201 * 202 * Returns true if the sink supports DSC with the given output_format, false otherwise. 203 */ 204 static inline bool 205 drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format) 206 { 207 return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format; 208 } 209 210 /* Forward Error Correction Support on DP 1.4 */ 211 static inline bool 212 drm_dp_sink_supports_fec(const u8 fec_capable) 213 { 214 return fec_capable & DP_FEC_CAPABLE; 215 } 216 217 static inline bool 218 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 219 { 220 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B; 221 } 222 223 static inline bool 224 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 225 { 226 return dpcd[DP_EDP_CONFIGURATION_CAP] & 227 DP_ALTERNATE_SCRAMBLER_RESET_CAP; 228 } 229 230 /* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ 231 static inline bool 232 drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 233 { 234 return dpcd[DP_DOWN_STREAM_PORT_COUNT] & 235 DP_MSA_TIMING_PAR_IGNORED; 236 } 237 238 /** 239 * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support 240 * @edp_dpcd: The DPCD to check 241 * 242 * Note that currently this function will return %false for panels which support various DPCD 243 * backlight features but which require the brightness be set through PWM, and don't support setting 244 * the brightness level via the DPCD. 245 * 246 * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false 247 * otherwise 248 */ 249 static inline bool 250 drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) 251 { 252 return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP); 253 } 254 255 /* 256 * DisplayPort AUX channel 257 */ 258 259 /** 260 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction 261 * @address: address of the (first) register to access 262 * @request: contains the type of transaction (see DP_AUX_* macros) 263 * @reply: upon completion, contains the reply type of the transaction 264 * @buffer: pointer to a transmission or reception buffer 265 * @size: size of @buffer 266 */ 267 struct drm_dp_aux_msg { 268 unsigned int address; 269 u8 request; 270 u8 reply; 271 void *buffer; 272 size_t size; 273 }; 274 275 struct cec_adapter; 276 struct edid; 277 struct drm_connector; 278 279 /** 280 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX 281 * @lock: mutex protecting this struct 282 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support. 283 * @connector: the connector this CEC adapter is associated with 284 * @unregister_work: unregister the CEC adapter 285 */ 286 struct drm_dp_aux_cec { 287 struct mutex lock; 288 struct cec_adapter *adap; 289 struct drm_connector *connector; 290 struct delayed_work unregister_work; 291 }; 292 293 /** 294 * struct drm_dp_aux - DisplayPort AUX channel 295 * 296 * An AUX channel can also be used to transport I2C messages to a sink. A 297 * typical application of that is to access an EDID that's present in the sink 298 * device. The @transfer() function can also be used to execute such 299 * transactions. The drm_dp_aux_register() function registers an I2C adapter 300 * that can be passed to drm_probe_ddc(). Upon removal, drivers should call 301 * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long 302 * transfers by default; if a partial response is received, the adapter will 303 * drop down to the size given by the partial response for this transaction 304 * only. 305 */ 306 struct drm_dp_aux { 307 /** 308 * @name: user-visible name of this AUX channel and the 309 * I2C-over-AUX adapter. 310 * 311 * It's also used to specify the name of the I2C adapter. If set 312 * to %NULL, dev_name() of @dev will be used. 313 */ 314 const char *name; 315 316 /** 317 * @ddc: I2C adapter that can be used for I2C-over-AUX 318 * communication 319 */ 320 struct i2c_adapter ddc; 321 322 /** 323 * @dev: pointer to struct device that is the parent for this 324 * AUX channel. 325 */ 326 struct device *dev; 327 328 /** 329 * @drm_dev: pointer to the &drm_device that owns this AUX channel. 330 * Beware, this may be %NULL before drm_dp_aux_register() has been 331 * called. 332 * 333 * It should be set to the &drm_device that will be using this AUX 334 * channel as early as possible. For many graphics drivers this should 335 * happen before drm_dp_aux_init(), however it's perfectly fine to set 336 * this field later so long as it's assigned before calling 337 * drm_dp_aux_register(). 338 */ 339 struct drm_device *drm_dev; 340 341 /** 342 * @crtc: backpointer to the crtc that is currently using this 343 * AUX channel 344 */ 345 struct drm_crtc *crtc; 346 347 /** 348 * @hw_mutex: internal mutex used for locking transfers. 349 * 350 * Note that if the underlying hardware is shared among multiple 351 * channels, the driver needs to do additional locking to 352 * prevent concurrent access. 353 */ 354 struct mutex hw_mutex; 355 356 /** 357 * @crc_work: worker that captures CRCs for each frame 358 */ 359 struct work_struct crc_work; 360 361 /** 362 * @crc_count: counter of captured frame CRCs 363 */ 364 u8 crc_count; 365 366 /** 367 * @transfer: transfers a message representing a single AUX 368 * transaction. 369 * 370 * This is a hardware-specific implementation of how 371 * transactions are executed that the drivers must provide. 372 * 373 * A pointer to a &drm_dp_aux_msg structure describing the 374 * transaction is passed into this function. Upon success, the 375 * implementation should return the number of payload bytes that 376 * were transferred, or a negative error-code on failure. 377 * 378 * Helpers will propagate these errors, with the exception of 379 * the %-EBUSY error, which causes a transaction to be retried. 380 * On a short, helpers will return %-EPROTO to make it simpler 381 * to check for failure. 382 * 383 * The @transfer() function must only modify the reply field of 384 * the &drm_dp_aux_msg structure. The retry logic and i2c 385 * helpers assume this is the case. 386 * 387 * Also note that this callback can be called no matter the 388 * state @dev is in and also no matter what state the panel is 389 * in. It's expected: 390 * 391 * - If the @dev providing the AUX bus is currently unpowered then 392 * it will power itself up for the transfer. 393 * 394 * - If we're on eDP (using a drm_panel) and the panel is not in a 395 * state where it can respond (it's not powered or it's in a 396 * low power state) then this function may return an error, but 397 * not crash. It's up to the caller of this code to make sure that 398 * the panel is powered on if getting an error back is not OK. If a 399 * drm_panel driver is initiating a DP AUX transfer it may power 400 * itself up however it wants. All other code should ensure that 401 * the pre_enable() bridge chain (which eventually calls the 402 * drm_panel prepare function) has powered the panel. 403 */ 404 ssize_t (*transfer)(struct drm_dp_aux *aux, 405 struct drm_dp_aux_msg *msg); 406 407 /** 408 * @wait_hpd_asserted: wait for HPD to be asserted 409 * 410 * This is mainly useful for eDP panels drivers to wait for an eDP 411 * panel to finish powering on. This is an optional function. 412 * 413 * This function will efficiently wait for the HPD signal to be 414 * asserted. The `wait_us` parameter that is passed in says that we 415 * know that the HPD signal is expected to be asserted within `wait_us` 416 * microseconds. This function could wait for longer than `wait_us` if 417 * the logic in the DP controller has a long debouncing time. The 418 * important thing is that if this function returns success that the 419 * DP controller is ready to send AUX transactions. 420 * 421 * This function returns 0 if HPD was asserted or -ETIMEDOUT if time 422 * expired and HPD wasn't asserted. This function should not print 423 * timeout errors to the log. 424 * 425 * The semantics of this function are designed to match the 426 * readx_poll_timeout() function. That means a `wait_us` of 0 means 427 * to wait forever. Like readx_poll_timeout(), this function may sleep. 428 * 429 * NOTE: this function specifically reports the state of the HPD pin 430 * that's associated with the DP AUX channel. This is different from 431 * the HPD concept in much of the rest of DRM which is more about 432 * physical presence of a display. For eDP, for instance, a display is 433 * assumed always present even if the HPD pin is deasserted. 434 */ 435 int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us); 436 437 /** 438 * @i2c_nack_count: Counts I2C NACKs, used for DP validation. 439 */ 440 unsigned i2c_nack_count; 441 /** 442 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation. 443 */ 444 unsigned i2c_defer_count; 445 /** 446 * @cec: struct containing fields used for CEC-Tunneling-over-AUX. 447 */ 448 struct drm_dp_aux_cec cec; 449 /** 450 * @is_remote: Is this AUX CH actually using sideband messaging. 451 */ 452 bool is_remote; 453 }; 454 455 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset); 456 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 457 void *buffer, size_t size); 458 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 459 void *buffer, size_t size); 460 461 /** 462 * drm_dp_dpcd_readb() - read a single byte from the DPCD 463 * @aux: DisplayPort AUX channel 464 * @offset: address of the register to read 465 * @valuep: location where the value of the register will be stored 466 * 467 * Returns the number of bytes transferred (1) on success, or a negative 468 * error code on failure. 469 */ 470 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, 471 unsigned int offset, u8 *valuep) 472 { 473 return drm_dp_dpcd_read(aux, offset, valuep, 1); 474 } 475 476 /** 477 * drm_dp_dpcd_writeb() - write a single byte to the DPCD 478 * @aux: DisplayPort AUX channel 479 * @offset: address of the register to write 480 * @value: value to write to the register 481 * 482 * Returns the number of bytes transferred (1) on success, or a negative 483 * error code on failure. 484 */ 485 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, 486 unsigned int offset, u8 value) 487 { 488 return drm_dp_dpcd_write(aux, offset, &value, 1); 489 } 490 491 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, 492 u8 dpcd[DP_RECEIVER_CAP_SIZE]); 493 494 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 495 u8 status[DP_LINK_STATUS_SIZE]); 496 497 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, 498 enum drm_dp_phy dp_phy, 499 u8 link_status[DP_LINK_STATUS_SIZE]); 500 501 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, 502 u8 real_edid_checksum); 503 504 int drm_dp_read_downstream_info(struct drm_dp_aux *aux, 505 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 506 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]); 507 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 508 const u8 port_cap[4], u8 type); 509 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 510 const u8 port_cap[4], 511 const struct edid *edid); 512 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 513 const u8 port_cap[4]); 514 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 515 const u8 port_cap[4], 516 const struct edid *edid); 517 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 518 const u8 port_cap[4], 519 const struct edid *edid); 520 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 521 const u8 port_cap[4], 522 const struct edid *edid); 523 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 524 const u8 port_cap[4]); 525 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 526 const u8 port_cap[4]); 527 struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev, 528 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 529 const u8 port_cap[4]); 530 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]); 531 void drm_dp_downstream_debug(struct seq_file *m, 532 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 533 const u8 port_cap[4], 534 const struct edid *edid, 535 struct drm_dp_aux *aux); 536 enum drm_mode_subconnector 537 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 538 const u8 port_cap[4]); 539 void drm_dp_set_subconnector_property(struct drm_connector *connector, 540 enum drm_connector_status status, 541 const u8 *dpcd, 542 const u8 port_cap[4]); 543 544 struct drm_dp_desc; 545 bool drm_dp_read_sink_count_cap(struct drm_connector *connector, 546 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 547 const struct drm_dp_desc *desc); 548 int drm_dp_read_sink_count(struct drm_dp_aux *aux); 549 550 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, 551 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 552 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 553 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, 554 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 555 enum drm_dp_phy dp_phy, 556 u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 557 int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]); 558 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 559 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 560 bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 561 bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 562 563 void drm_dp_remote_aux_init(struct drm_dp_aux *aux); 564 void drm_dp_aux_init(struct drm_dp_aux *aux); 565 int drm_dp_aux_register(struct drm_dp_aux *aux); 566 void drm_dp_aux_unregister(struct drm_dp_aux *aux); 567 568 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc); 569 int drm_dp_stop_crc(struct drm_dp_aux *aux); 570 571 struct drm_dp_dpcd_ident { 572 u8 oui[3]; 573 u8 device_id[6]; 574 u8 hw_rev; 575 u8 sw_major_rev; 576 u8 sw_minor_rev; 577 } __packed; 578 579 /** 580 * struct drm_dp_desc - DP branch/sink device descriptor 581 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch). 582 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks. 583 */ 584 struct drm_dp_desc { 585 struct drm_dp_dpcd_ident ident; 586 u32 quirks; 587 }; 588 589 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, 590 bool is_branch); 591 592 /** 593 * enum drm_dp_quirk - Display Port sink/branch device specific quirks 594 * 595 * Display Port sink and branch devices in the wild have a variety of bugs, try 596 * to collect them here. The quirks are shared, but it's up to the drivers to 597 * implement workarounds for them. 598 */ 599 enum drm_dp_quirk { 600 /** 601 * @DP_DPCD_QUIRK_CONSTANT_N: 602 * 603 * The device requires main link attributes Mvid and Nvid to be limited 604 * to 16 bits. So will give a constant value (0x8000) for compatability. 605 */ 606 DP_DPCD_QUIRK_CONSTANT_N, 607 /** 608 * @DP_DPCD_QUIRK_NO_PSR: 609 * 610 * The device does not support PSR even if reports that it supports or 611 * driver still need to implement proper handling for such device. 612 */ 613 DP_DPCD_QUIRK_NO_PSR, 614 /** 615 * @DP_DPCD_QUIRK_NO_SINK_COUNT: 616 * 617 * The device does not set SINK_COUNT to a non-zero value. 618 * The driver should ignore SINK_COUNT during detection. Note that 619 * drm_dp_read_sink_count_cap() automatically checks for this quirk. 620 */ 621 DP_DPCD_QUIRK_NO_SINK_COUNT, 622 /** 623 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD: 624 * 625 * The device supports MST DSC despite not supporting Virtual DPCD. 626 * The DSC caps can be read from the physical aux instead. 627 */ 628 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD, 629 /** 630 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS: 631 * 632 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite 633 * the DP_MAX_LINK_RATE register reporting a lower max multiplier. 634 */ 635 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS, 636 }; 637 638 /** 639 * drm_dp_has_quirk() - does the DP device have a specific quirk 640 * @desc: Device descriptor filled by drm_dp_read_desc() 641 * @quirk: Quirk to query for 642 * 643 * Return true if DP device identified by @desc has @quirk. 644 */ 645 static inline bool 646 drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk) 647 { 648 return desc->quirks & BIT(quirk); 649 } 650 651 /** 652 * struct drm_edp_backlight_info - Probed eDP backlight info struct 653 * @pwmgen_bit_count: The pwmgen bit count 654 * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any 655 * @max: The maximum backlight level that may be set 656 * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register? 657 * @aux_enable: Does the panel support the AUX enable cap? 658 * @aux_set: Does the panel support setting the brightness through AUX? 659 * 660 * This structure contains various data about an eDP backlight, which can be populated by using 661 * drm_edp_backlight_init(). 662 */ 663 struct drm_edp_backlight_info { 664 u8 pwmgen_bit_count; 665 u8 pwm_freq_pre_divider; 666 u16 max; 667 668 bool lsb_reg_used : 1; 669 bool aux_enable : 1; 670 bool aux_set : 1; 671 }; 672 673 int 674 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 675 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE], 676 u16 *current_level, u8 *current_mode); 677 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 678 u16 level); 679 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 680 u16 level); 681 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl); 682 683 #if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ 684 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE))) 685 686 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux); 687 688 #else 689 690 static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel, 691 struct drm_dp_aux *aux) 692 { 693 return 0; 694 } 695 696 #endif 697 698 #ifdef CONFIG_DRM_DP_CEC 699 void drm_dp_cec_irq(struct drm_dp_aux *aux); 700 void drm_dp_cec_register_connector(struct drm_dp_aux *aux, 701 struct drm_connector *connector); 702 void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux); 703 void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid); 704 void drm_dp_cec_unset_edid(struct drm_dp_aux *aux); 705 #else 706 static inline void drm_dp_cec_irq(struct drm_dp_aux *aux) 707 { 708 } 709 710 static inline void 711 drm_dp_cec_register_connector(struct drm_dp_aux *aux, 712 struct drm_connector *connector) 713 { 714 } 715 716 static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux) 717 { 718 } 719 720 static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux, 721 const struct edid *edid) 722 { 723 } 724 725 static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux) 726 { 727 } 728 729 #endif 730 731 /** 732 * struct drm_dp_phy_test_params - DP Phy Compliance parameters 733 * @link_rate: Requested Link rate from DPCD 0x219 734 * @num_lanes: Number of lanes requested by sing through DPCD 0x220 735 * @phy_pattern: DP Phy test pattern from DPCD 0x248 736 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B 737 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259 738 * @enhanced_frame_cap: flag for enhanced frame capability. 739 */ 740 struct drm_dp_phy_test_params { 741 int link_rate; 742 u8 num_lanes; 743 u8 phy_pattern; 744 u8 hbr2_reset[2]; 745 u8 custom80[10]; 746 bool enhanced_frame_cap; 747 }; 748 749 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, 750 struct drm_dp_phy_test_params *data); 751 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, 752 struct drm_dp_phy_test_params *data, u8 dp_rev); 753 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 754 const u8 port_cap[4]); 755 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); 756 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); 757 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, 758 u8 frl_mode); 759 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, 760 u8 frl_type); 761 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); 762 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); 763 764 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux); 765 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask); 766 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, 767 struct drm_connector *connector); 768 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 769 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 770 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 771 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 772 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux); 773 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]); 774 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]); 775 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 776 const u8 port_cap[4], u8 color_spc); 777 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc); 778 779 #endif /* _DRM_DP_HELPER_H_ */ 780