1 /* 2 * Defines for Mobile High-Definition Link (MHL) interface 3 * 4 * Copyright (C) 2015, Samsung Electronics, Co., Ltd. 5 * Andrzej Hajda <a.hajda@samsung.com> 6 * 7 * Based on MHL driver for Android devices. 8 * Copyright (C) 2013-2014 Silicon Image, Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #ifndef __MHL_H__ 16 #define __MHL_H__ 17 18 /* Device Capabilities Registers */ 19 enum { 20 MHL_DCAP_DEV_STATE, 21 MHL_DCAP_MHL_VERSION, 22 MHL_DCAP_CAT, 23 MHL_DCAP_ADOPTER_ID_H, 24 MHL_DCAP_ADOPTER_ID_L, 25 MHL_DCAP_VID_LINK_MODE, 26 MHL_DCAP_AUD_LINK_MODE, 27 MHL_DCAP_VIDEO_TYPE, 28 MHL_DCAP_LOG_DEV_MAP, 29 MHL_DCAP_BANDWIDTH, 30 MHL_DCAP_FEATURE_FLAG, 31 MHL_DCAP_DEVICE_ID_H, 32 MHL_DCAP_DEVICE_ID_L, 33 MHL_DCAP_SCRATCHPAD_SIZE, 34 MHL_DCAP_INT_STAT_SIZE, 35 MHL_DCAP_RESERVED, 36 MHL_DCAP_SIZE 37 }; 38 39 #define MHL_DCAP_CAT_SINK 0x01 40 #define MHL_DCAP_CAT_SOURCE 0x02 41 #define MHL_DCAP_CAT_POWER 0x10 42 #define MHL_DCAP_CAT_PLIM(x) ((x) << 5) 43 44 #define MHL_DCAP_VID_LINK_RGB444 0x01 45 #define MHL_DCAP_VID_LINK_YCBCR444 0x02 46 #define MHL_DCAP_VID_LINK_YCBCR422 0x04 47 #define MHL_DCAP_VID_LINK_PPIXEL 0x08 48 #define MHL_DCAP_VID_LINK_ISLANDS 0x10 49 #define MHL_DCAP_VID_LINK_VGA 0x20 50 #define MHL_DCAP_VID_LINK_16BPP 0x40 51 52 #define MHL_DCAP_AUD_LINK_2CH 0x01 53 #define MHL_DCAP_AUD_LINK_8CH 0x02 54 55 #define MHL_DCAP_VT_GRAPHICS 0x00 56 #define MHL_DCAP_VT_PHOTO 0x02 57 #define MHL_DCAP_VT_CINEMA 0x04 58 #define MHL_DCAP_VT_GAMES 0x08 59 #define MHL_DCAP_SUPP_VT 0x80 60 61 #define MHL_DCAP_LD_DISPLAY 0x01 62 #define MHL_DCAP_LD_VIDEO 0x02 63 #define MHL_DCAP_LD_AUDIO 0x04 64 #define MHL_DCAP_LD_MEDIA 0x08 65 #define MHL_DCAP_LD_TUNER 0x10 66 #define MHL_DCAP_LD_RECORD 0x20 67 #define MHL_DCAP_LD_SPEAKER 0x40 68 #define MHL_DCAP_LD_GUI 0x80 69 #define MHL_DCAP_LD_ALL 0xFF 70 71 #define MHL_DCAP_FEATURE_RCP_SUPPORT 0x01 72 #define MHL_DCAP_FEATURE_RAP_SUPPORT 0x02 73 #define MHL_DCAP_FEATURE_SP_SUPPORT 0x04 74 #define MHL_DCAP_FEATURE_UCP_SEND_SUPPOR 0x08 75 #define MHL_DCAP_FEATURE_UCP_RECV_SUPPORT 0x10 76 #define MHL_DCAP_FEATURE_RBP_SUPPORT 0x40 77 78 /* Extended Device Capabilities Registers */ 79 enum { 80 MHL_XDC_ECBUS_SPEEDS, 81 MHL_XDC_TMDS_SPEEDS, 82 MHL_XDC_ECBUS_ROLES, 83 MHL_XDC_LOG_DEV_MAPX, 84 MHL_XDC_SIZE 85 }; 86 87 #define MHL_XDC_ECBUS_S_075 0x01 88 #define MHL_XDC_ECBUS_S_8BIT 0x02 89 #define MHL_XDC_ECBUS_S_12BIT 0x04 90 #define MHL_XDC_ECBUS_D_150 0x10 91 #define MHL_XDC_ECBUS_D_8BIT 0x20 92 93 #define MHL_XDC_TMDS_000 0x00 94 #define MHL_XDC_TMDS_150 0x01 95 #define MHL_XDC_TMDS_300 0x02 96 #define MHL_XDC_TMDS_600 0x04 97 98 /* MHL_XDC_ECBUS_ROLES flags */ 99 #define MHL_XDC_DEV_HOST 0x01 100 #define MHL_XDC_DEV_DEVICE 0x02 101 #define MHL_XDC_DEV_CHARGER 0x04 102 #define MHL_XDC_HID_HOST 0x08 103 #define MHL_XDC_HID_DEVICE 0x10 104 105 /* MHL_XDC_LOG_DEV_MAPX flags */ 106 #define MHL_XDC_LD_PHONE 0x01 107 108 /* Device Status Registers */ 109 enum { 110 MHL_DST_CONNECTED_RDY, 111 MHL_DST_LINK_MODE, 112 MHL_DST_VERSION, 113 MHL_DST_SIZE 114 }; 115 116 /* Offset of DEVSTAT registers */ 117 #define MHL_DST_OFFSET 0x30 118 #define MHL_DST_REG(name) (MHL_DST_OFFSET + MHL_DST_##name) 119 120 #define MHL_DST_CONN_DCAP_RDY 0x01 121 #define MHL_DST_CONN_XDEVCAPP_SUPP 0x02 122 #define MHL_DST_CONN_POW_STAT 0x04 123 #define MHL_DST_CONN_PLIM_STAT_MASK 0x38 124 125 #define MHL_DST_LM_CLK_MODE_MASK 0x07 126 #define MHL_DST_LM_CLK_MODE_PACKED_PIXEL 0x02 127 #define MHL_DST_LM_CLK_MODE_NORMAL 0x03 128 #define MHL_DST_LM_PATH_EN_MASK 0x08 129 #define MHL_DST_LM_PATH_ENABLED 0x08 130 #define MHL_DST_LM_PATH_DISABLED 0x00 131 #define MHL_DST_LM_MUTED_MASK 0x10 132 133 /* Extended Device Status Registers */ 134 enum { 135 MHL_XDS_CURR_ECBUS_MODE, 136 MHL_XDS_AVLINK_MODE_STATUS, 137 MHL_XDS_AVLINK_MODE_CONTROL, 138 MHL_XDS_MULTI_SINK_STATUS, 139 MHL_XDS_SIZE 140 }; 141 142 /* Offset of XDEVSTAT registers */ 143 #define MHL_XDS_OFFSET 0x90 144 #define MHL_XDS_REG(name) (MHL_XDS_OFFSET + MHL_XDS_##name) 145 146 /* MHL_XDS_REG_CURR_ECBUS_MODE flags */ 147 #define MHL_XDS_SLOT_MODE_8BIT 0x00 148 #define MHL_XDS_SLOT_MODE_6BIT 0x01 149 #define MHL_XDS_ECBUS_S 0x04 150 #define MHL_XDS_ECBUS_D 0x08 151 152 #define MHL_XDS_LINK_CLOCK_75MHZ 0x00 153 #define MHL_XDS_LINK_CLOCK_150MHZ 0x10 154 #define MHL_XDS_LINK_CLOCK_300MHZ 0x20 155 #define MHL_XDS_LINK_CLOCK_600MHZ 0x30 156 157 #define MHL_XDS_LINK_STATUS_NO_SIGNAL 0x00 158 #define MHL_XDS_LINK_STATUS_CRU_LOCKED 0x01 159 #define MHL_XDS_LINK_STATUS_TMDS_NORMAL 0x02 160 #define MHL_XDS_LINK_STATUS_TMDS_RESERVED 0x03 161 162 #define MHL_XDS_LINK_RATE_1_5_GBPS 0x00 163 #define MHL_XDS_LINK_RATE_3_0_GBPS 0x01 164 #define MHL_XDS_LINK_RATE_6_0_GBPS 0x02 165 #define MHL_XDS_ATT_CAPABLE 0x08 166 167 #define MHL_XDS_SINK_STATUS_1_HPD_LOW 0x00 168 #define MHL_XDS_SINK_STATUS_1_HPD_HIGH 0x01 169 #define MHL_XDS_SINK_STATUS_2_HPD_LOW 0x00 170 #define MHL_XDS_SINK_STATUS_2_HPD_HIGH 0x04 171 #define MHL_XDS_SINK_STATUS_3_HPD_LOW 0x00 172 #define MHL_XDS_SINK_STATUS_3_HPD_HIGH 0x10 173 #define MHL_XDS_SINK_STATUS_4_HPD_LOW 0x00 174 #define MHL_XDS_SINK_STATUS_4_HPD_HIGH 0x40 175 176 /* Interrupt Registers */ 177 enum { 178 MHL_INT_RCHANGE, 179 MHL_INT_DCHANGE, 180 MHL_INT_SIZE 181 }; 182 183 /* Offset of DEVSTAT registers */ 184 #define MHL_INT_OFFSET 0x20 185 #define MHL_INT_REG(name) (MHL_INT_OFFSET + MHL_INT_##name) 186 187 #define MHL_INT_RC_DCAP_CHG 0x01 188 #define MHL_INT_RC_DSCR_CHG 0x02 189 #define MHL_INT_RC_REQ_WRT 0x04 190 #define MHL_INT_RC_GRT_WRT 0x08 191 #define MHL_INT_RC_3D_REQ 0x10 192 #define MHL_INT_RC_FEAT_REQ 0x20 193 #define MHL_INT_RC_FEAT_COMPLETE 0x40 194 195 #define MHL_INT_DC_EDID_CHG 0x02 196 197 enum { 198 MHL_ACK = 0x33, /* Command or Data byte acknowledge */ 199 MHL_NACK = 0x34, /* Command or Data byte not acknowledge */ 200 MHL_ABORT = 0x35, /* Transaction abort */ 201 MHL_WRITE_STAT = 0xe0, /* Write one status register */ 202 MHL_SET_INT = 0x60, /* Write one interrupt register */ 203 MHL_READ_DEVCAP_REG = 0x61, /* Read one register */ 204 MHL_GET_STATE = 0x62, /* Read CBUS revision level from follower */ 205 MHL_GET_VENDOR_ID = 0x63, /* Read vendor ID value from follower */ 206 MHL_SET_HPD = 0x64, /* Set Hot Plug Detect in follower */ 207 MHL_CLR_HPD = 0x65, /* Clear Hot Plug Detect in follower */ 208 MHL_SET_CAP_ID = 0x66, /* Set Capture ID for downstream device */ 209 MHL_GET_CAP_ID = 0x67, /* Get Capture ID from downstream device */ 210 MHL_MSC_MSG = 0x68, /* VS command to send RCP sub-commands */ 211 MHL_GET_SC1_ERRORCODE = 0x69, /* Get Vendor-Specific error code */ 212 MHL_GET_DDC_ERRORCODE = 0x6A, /* Get DDC channel command error code */ 213 MHL_GET_MSC_ERRORCODE = 0x6B, /* Get MSC command error code */ 214 MHL_WRITE_BURST = 0x6C, /* Write 1-16 bytes to responder's scratchpad */ 215 MHL_GET_SC3_ERRORCODE = 0x6D, /* Get channel 3 command error code */ 216 MHL_WRITE_XSTAT = 0x70, /* Write one extended status register */ 217 MHL_READ_XDEVCAP_REG = 0x71, /* Read one extended devcap register */ 218 /* let the rest of these float, they are software specific */ 219 MHL_READ_EDID_BLOCK, 220 MHL_SEND_3D_REQ_OR_FEAT_REQ, 221 MHL_READ_DEVCAP, 222 MHL_READ_XDEVCAP 223 }; 224 225 /* MSC message types */ 226 enum { 227 MHL_MSC_MSG_RCP = 0x10, /* RCP sub-command */ 228 MHL_MSC_MSG_RCPK = 0x11, /* RCP Acknowledge sub-command */ 229 MHL_MSC_MSG_RCPE = 0x12, /* RCP Error sub-command */ 230 MHL_MSC_MSG_RAP = 0x20, /* Mode Change Warning sub-command */ 231 MHL_MSC_MSG_RAPK = 0x21, /* MCW Acknowledge sub-command */ 232 MHL_MSC_MSG_RBP = 0x22, /* Remote Button Protocol sub-command */ 233 MHL_MSC_MSG_RBPK = 0x23, /* RBP Acknowledge sub-command */ 234 MHL_MSC_MSG_RBPE = 0x24, /* RBP Error sub-command */ 235 MHL_MSC_MSG_UCP = 0x30, /* UCP sub-command */ 236 MHL_MSC_MSG_UCPK = 0x31, /* UCP Acknowledge sub-command */ 237 MHL_MSC_MSG_UCPE = 0x32, /* UCP Error sub-command */ 238 MHL_MSC_MSG_RUSB = 0x40, /* Request USB host role */ 239 MHL_MSC_MSG_RUSBK = 0x41, /* Acknowledge request for USB host role */ 240 MHL_MSC_MSG_RHID = 0x42, /* Request HID host role */ 241 MHL_MSC_MSG_RHIDK = 0x43, /* Acknowledge request for HID host role */ 242 MHL_MSC_MSG_ATT = 0x50, /* Request attention sub-command */ 243 MHL_MSC_MSG_ATTK = 0x51, /* ATT Acknowledge sub-command */ 244 MHL_MSC_MSG_BIST_TRIGGER = 0x60, 245 MHL_MSC_MSG_BIST_REQUEST_STAT = 0x61, 246 MHL_MSC_MSG_BIST_READY = 0x62, 247 MHL_MSC_MSG_BIST_STOP = 0x63, 248 }; 249 250 /* RAP action codes */ 251 #define MHL_RAP_POLL 0x00 /* Just do an ack */ 252 #define MHL_RAP_CONTENT_ON 0x10 /* Turn content stream ON */ 253 #define MHL_RAP_CONTENT_OFF 0x11 /* Turn content stream OFF */ 254 #define MHL_RAP_CBUS_MODE_DOWN 0x20 255 #define MHL_RAP_CBUS_MODE_UP 0x21 256 257 /* RAPK status codes */ 258 #define MHL_RAPK_NO_ERR 0x00 /* RAP action recognized & supported */ 259 #define MHL_RAPK_UNRECOGNIZED 0x01 /* Unknown RAP action code received */ 260 #define MHL_RAPK_UNSUPPORTED 0x02 /* Rcvd RAP action code not supported */ 261 #define MHL_RAPK_BUSY 0x03 /* Responder too busy to respond */ 262 263 /* 264 * Error status codes for RCPE messages 265 */ 266 /* No error. (Not allowed in RCPE messages) */ 267 #define MHL_RCPE_STATUS_NO_ERROR 0x00 268 /* Unsupported/unrecognized key code */ 269 #define MHL_RCPE_STATUS_INEFFECTIVE_KEY_CODE 0x01 270 /* Responder busy. Initiator may retry message */ 271 #define MHL_RCPE_STATUS_BUSY 0x02 272 273 /* 274 * Error status codes for RBPE messages 275 */ 276 /* No error. (Not allowed in RBPE messages) */ 277 #define MHL_RBPE_STATUS_NO_ERROR 0x00 278 /* Unsupported/unrecognized button code */ 279 #define MHL_RBPE_STATUS_INEFFECTIVE_BUTTON_CODE 0x01 280 /* Responder busy. Initiator may retry message */ 281 #define MHL_RBPE_STATUS_BUSY 0x02 282 283 /* 284 * Error status codes for UCPE messages 285 */ 286 /* No error. (Not allowed in UCPE messages) */ 287 #define MHL_UCPE_STATUS_NO_ERROR 0x00 288 /* Unsupported/unrecognized key code */ 289 #define MHL_UCPE_STATUS_INEFFECTIVE_KEY_CODE 0x01 290 291 #endif /* __MHL_H__ */ 292