1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #ifndef __DW_HDMI__ 11 #define __DW_HDMI__ 12 13 struct drm_connector; 14 struct drm_display_mode; 15 struct drm_encoder; 16 struct dw_hdmi; 17 struct platform_device; 18 19 /** 20 * DOC: Supported input formats and encodings 21 * 22 * Depending on the Hardware configuration of the Controller IP, it supports 23 * a subset of the following input formats and encodings on its internal 24 * 48bit bus. 25 * 26 * +----------------------+----------------------------------+------------------------------+ 27 * | Format Name | Format Code | Encodings | 28 * +----------------------+----------------------------------+------------------------------+ 29 * | RGB 4:4:4 8bit | ``MEDIA_BUS_FMT_RGB888_1X24`` | ``V4L2_YCBCR_ENC_DEFAULT`` | 30 * +----------------------+----------------------------------+------------------------------+ 31 * | RGB 4:4:4 10bits | ``MEDIA_BUS_FMT_RGB101010_1X30`` | ``V4L2_YCBCR_ENC_DEFAULT`` | 32 * +----------------------+----------------------------------+------------------------------+ 33 * | RGB 4:4:4 12bits | ``MEDIA_BUS_FMT_RGB121212_1X36`` | ``V4L2_YCBCR_ENC_DEFAULT`` | 34 * +----------------------+----------------------------------+------------------------------+ 35 * | RGB 4:4:4 16bits | ``MEDIA_BUS_FMT_RGB161616_1X48`` | ``V4L2_YCBCR_ENC_DEFAULT`` | 36 * +----------------------+----------------------------------+------------------------------+ 37 * | YCbCr 4:4:4 8bit | ``MEDIA_BUS_FMT_YUV8_1X24`` | ``V4L2_YCBCR_ENC_601`` | 38 * | | | or ``V4L2_YCBCR_ENC_709`` | 39 * | | | or ``V4L2_YCBCR_ENC_XV601`` | 40 * | | | or ``V4L2_YCBCR_ENC_XV709`` | 41 * +----------------------+----------------------------------+------------------------------+ 42 * | YCbCr 4:4:4 10bits | ``MEDIA_BUS_FMT_YUV10_1X30`` | ``V4L2_YCBCR_ENC_601`` | 43 * | | | or ``V4L2_YCBCR_ENC_709`` | 44 * | | | or ``V4L2_YCBCR_ENC_XV601`` | 45 * | | | or ``V4L2_YCBCR_ENC_XV709`` | 46 * +----------------------+----------------------------------+------------------------------+ 47 * | YCbCr 4:4:4 12bits | ``MEDIA_BUS_FMT_YUV12_1X36`` | ``V4L2_YCBCR_ENC_601`` | 48 * | | | or ``V4L2_YCBCR_ENC_709`` | 49 * | | | or ``V4L2_YCBCR_ENC_XV601`` | 50 * | | | or ``V4L2_YCBCR_ENC_XV709`` | 51 * +----------------------+----------------------------------+------------------------------+ 52 * | YCbCr 4:4:4 16bits | ``MEDIA_BUS_FMT_YUV16_1X48`` | ``V4L2_YCBCR_ENC_601`` | 53 * | | | or ``V4L2_YCBCR_ENC_709`` | 54 * | | | or ``V4L2_YCBCR_ENC_XV601`` | 55 * | | | or ``V4L2_YCBCR_ENC_XV709`` | 56 * +----------------------+----------------------------------+------------------------------+ 57 * | YCbCr 4:2:2 8bit | ``MEDIA_BUS_FMT_UYVY8_1X16`` | ``V4L2_YCBCR_ENC_601`` | 58 * | | | or ``V4L2_YCBCR_ENC_709`` | 59 * +----------------------+----------------------------------+------------------------------+ 60 * | YCbCr 4:2:2 10bits | ``MEDIA_BUS_FMT_UYVY10_1X20`` | ``V4L2_YCBCR_ENC_601`` | 61 * | | | or ``V4L2_YCBCR_ENC_709`` | 62 * +----------------------+----------------------------------+------------------------------+ 63 * | YCbCr 4:2:2 12bits | ``MEDIA_BUS_FMT_UYVY12_1X24`` | ``V4L2_YCBCR_ENC_601`` | 64 * | | | or ``V4L2_YCBCR_ENC_709`` | 65 * +----------------------+----------------------------------+------------------------------+ 66 * | YCbCr 4:2:0 8bit | ``MEDIA_BUS_FMT_UYYVYY8_0_5X24`` | ``V4L2_YCBCR_ENC_601`` | 67 * | | | or ``V4L2_YCBCR_ENC_709`` | 68 * +----------------------+----------------------------------+------------------------------+ 69 * | YCbCr 4:2:0 10bits | ``MEDIA_BUS_FMT_UYYVYY10_0_5X30``| ``V4L2_YCBCR_ENC_601`` | 70 * | | | or ``V4L2_YCBCR_ENC_709`` | 71 * +----------------------+----------------------------------+------------------------------+ 72 * | YCbCr 4:2:0 12bits | ``MEDIA_BUS_FMT_UYYVYY12_0_5X36``| ``V4L2_YCBCR_ENC_601`` | 73 * | | | or ``V4L2_YCBCR_ENC_709`` | 74 * +----------------------+----------------------------------+------------------------------+ 75 * | YCbCr 4:2:0 16bits | ``MEDIA_BUS_FMT_UYYVYY16_0_5X48``| ``V4L2_YCBCR_ENC_601`` | 76 * | | | or ``V4L2_YCBCR_ENC_709`` | 77 * +----------------------+----------------------------------+------------------------------+ 78 */ 79 80 enum { 81 DW_HDMI_RES_8, 82 DW_HDMI_RES_10, 83 DW_HDMI_RES_12, 84 DW_HDMI_RES_MAX, 85 }; 86 87 enum dw_hdmi_phy_type { 88 DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00, 89 DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2, 90 DW_HDMI_PHY_DWC_MHL_PHY = 0xc2, 91 DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC = 0xe2, 92 DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY = 0xf2, 93 DW_HDMI_PHY_DWC_HDMI20_TX_PHY = 0xf3, 94 DW_HDMI_PHY_VENDOR_PHY = 0xfe, 95 }; 96 97 struct dw_hdmi_mpll_config { 98 unsigned long mpixelclock; 99 struct { 100 u16 cpce; 101 u16 gmp; 102 } res[DW_HDMI_RES_MAX]; 103 }; 104 105 struct dw_hdmi_curr_ctrl { 106 unsigned long mpixelclock; 107 u16 curr[DW_HDMI_RES_MAX]; 108 }; 109 110 struct dw_hdmi_phy_config { 111 unsigned long mpixelclock; 112 u16 sym_ctr; /*clock symbol and transmitter control*/ 113 u16 term; /*transmission termination value*/ 114 u16 vlev_ctr; /* voltage level control */ 115 }; 116 117 struct dw_hdmi_phy_ops { 118 int (*init)(struct dw_hdmi *hdmi, void *data, 119 struct drm_display_mode *mode); 120 void (*disable)(struct dw_hdmi *hdmi, void *data); 121 enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi, void *data); 122 void (*update_hpd)(struct dw_hdmi *hdmi, void *data, 123 bool force, bool disabled, bool rxsense); 124 void (*setup_hpd)(struct dw_hdmi *hdmi, void *data); 125 }; 126 127 struct dw_hdmi_plat_data { 128 struct regmap *regm; 129 enum drm_mode_status (*mode_valid)(struct drm_connector *connector, 130 const struct drm_display_mode *mode); 131 unsigned long input_bus_format; 132 unsigned long input_bus_encoding; 133 134 /* Vendor PHY support */ 135 const struct dw_hdmi_phy_ops *phy_ops; 136 const char *phy_name; 137 void *phy_data; 138 unsigned int phy_force_vendor; 139 140 /* Synopsys PHY support */ 141 const struct dw_hdmi_mpll_config *mpll_cfg; 142 const struct dw_hdmi_curr_ctrl *cur_ctr; 143 const struct dw_hdmi_phy_config *phy_config; 144 int (*configure_phy)(struct dw_hdmi *hdmi, 145 const struct dw_hdmi_plat_data *pdata, 146 unsigned long mpixelclock); 147 }; 148 149 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, 150 const struct dw_hdmi_plat_data *plat_data); 151 void dw_hdmi_remove(struct dw_hdmi *hdmi); 152 void dw_hdmi_unbind(struct dw_hdmi *hdmi); 153 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, 154 struct drm_encoder *encoder, 155 const struct dw_hdmi_plat_data *plat_data); 156 157 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense); 158 159 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); 160 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); 161 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi); 162 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi); 163 164 /* PHY configuration */ 165 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address); 166 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 167 unsigned char addr); 168 169 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable); 170 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable); 171 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi); 172 173 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 174 void *data); 175 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, 176 bool force, bool disabled, bool rxsense); 177 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data); 178 179 #endif /* __IMX_HDMI_H__ */ 180