1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2011 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __DW_HDMI__ 7 #define __DW_HDMI__ 8 9 struct drm_connector; 10 struct drm_display_mode; 11 struct drm_encoder; 12 struct dw_hdmi; 13 struct platform_device; 14 15 /** 16 * DOC: Supported input formats and encodings 17 * 18 * Depending on the Hardware configuration of the Controller IP, it supports 19 * a subset of the following input formats and encodings on its internal 20 * 48bit bus. 21 * 22 * +----------------------+----------------------------------+------------------------------+ 23 * | Format Name | Format Code | Encodings | 24 * +----------------------+----------------------------------+------------------------------+ 25 * | RGB 4:4:4 8bit | ``MEDIA_BUS_FMT_RGB888_1X24`` | ``V4L2_YCBCR_ENC_DEFAULT`` | 26 * +----------------------+----------------------------------+------------------------------+ 27 * | RGB 4:4:4 10bits | ``MEDIA_BUS_FMT_RGB101010_1X30`` | ``V4L2_YCBCR_ENC_DEFAULT`` | 28 * +----------------------+----------------------------------+------------------------------+ 29 * | RGB 4:4:4 12bits | ``MEDIA_BUS_FMT_RGB121212_1X36`` | ``V4L2_YCBCR_ENC_DEFAULT`` | 30 * +----------------------+----------------------------------+------------------------------+ 31 * | RGB 4:4:4 16bits | ``MEDIA_BUS_FMT_RGB161616_1X48`` | ``V4L2_YCBCR_ENC_DEFAULT`` | 32 * +----------------------+----------------------------------+------------------------------+ 33 * | YCbCr 4:4:4 8bit | ``MEDIA_BUS_FMT_YUV8_1X24`` | ``V4L2_YCBCR_ENC_601`` | 34 * | | | or ``V4L2_YCBCR_ENC_709`` | 35 * | | | or ``V4L2_YCBCR_ENC_XV601`` | 36 * | | | or ``V4L2_YCBCR_ENC_XV709`` | 37 * +----------------------+----------------------------------+------------------------------+ 38 * | YCbCr 4:4:4 10bits | ``MEDIA_BUS_FMT_YUV10_1X30`` | ``V4L2_YCBCR_ENC_601`` | 39 * | | | or ``V4L2_YCBCR_ENC_709`` | 40 * | | | or ``V4L2_YCBCR_ENC_XV601`` | 41 * | | | or ``V4L2_YCBCR_ENC_XV709`` | 42 * +----------------------+----------------------------------+------------------------------+ 43 * | YCbCr 4:4:4 12bits | ``MEDIA_BUS_FMT_YUV12_1X36`` | ``V4L2_YCBCR_ENC_601`` | 44 * | | | or ``V4L2_YCBCR_ENC_709`` | 45 * | | | or ``V4L2_YCBCR_ENC_XV601`` | 46 * | | | or ``V4L2_YCBCR_ENC_XV709`` | 47 * +----------------------+----------------------------------+------------------------------+ 48 * | YCbCr 4:4:4 16bits | ``MEDIA_BUS_FMT_YUV16_1X48`` | ``V4L2_YCBCR_ENC_601`` | 49 * | | | or ``V4L2_YCBCR_ENC_709`` | 50 * | | | or ``V4L2_YCBCR_ENC_XV601`` | 51 * | | | or ``V4L2_YCBCR_ENC_XV709`` | 52 * +----------------------+----------------------------------+------------------------------+ 53 * | YCbCr 4:2:2 8bit | ``MEDIA_BUS_FMT_UYVY8_1X16`` | ``V4L2_YCBCR_ENC_601`` | 54 * | | | or ``V4L2_YCBCR_ENC_709`` | 55 * +----------------------+----------------------------------+------------------------------+ 56 * | YCbCr 4:2:2 10bits | ``MEDIA_BUS_FMT_UYVY10_1X20`` | ``V4L2_YCBCR_ENC_601`` | 57 * | | | or ``V4L2_YCBCR_ENC_709`` | 58 * +----------------------+----------------------------------+------------------------------+ 59 * | YCbCr 4:2:2 12bits | ``MEDIA_BUS_FMT_UYVY12_1X24`` | ``V4L2_YCBCR_ENC_601`` | 60 * | | | or ``V4L2_YCBCR_ENC_709`` | 61 * +----------------------+----------------------------------+------------------------------+ 62 * | YCbCr 4:2:0 8bit | ``MEDIA_BUS_FMT_UYYVYY8_0_5X24`` | ``V4L2_YCBCR_ENC_601`` | 63 * | | | or ``V4L2_YCBCR_ENC_709`` | 64 * +----------------------+----------------------------------+------------------------------+ 65 * | YCbCr 4:2:0 10bits | ``MEDIA_BUS_FMT_UYYVYY10_0_5X30``| ``V4L2_YCBCR_ENC_601`` | 66 * | | | or ``V4L2_YCBCR_ENC_709`` | 67 * +----------------------+----------------------------------+------------------------------+ 68 * | YCbCr 4:2:0 12bits | ``MEDIA_BUS_FMT_UYYVYY12_0_5X36``| ``V4L2_YCBCR_ENC_601`` | 69 * | | | or ``V4L2_YCBCR_ENC_709`` | 70 * +----------------------+----------------------------------+------------------------------+ 71 * | YCbCr 4:2:0 16bits | ``MEDIA_BUS_FMT_UYYVYY16_0_5X48``| ``V4L2_YCBCR_ENC_601`` | 72 * | | | or ``V4L2_YCBCR_ENC_709`` | 73 * +----------------------+----------------------------------+------------------------------+ 74 */ 75 76 enum { 77 DW_HDMI_RES_8, 78 DW_HDMI_RES_10, 79 DW_HDMI_RES_12, 80 DW_HDMI_RES_MAX, 81 }; 82 83 enum dw_hdmi_phy_type { 84 DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00, 85 DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2, 86 DW_HDMI_PHY_DWC_MHL_PHY = 0xc2, 87 DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC = 0xe2, 88 DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY = 0xf2, 89 DW_HDMI_PHY_DWC_HDMI20_TX_PHY = 0xf3, 90 DW_HDMI_PHY_VENDOR_PHY = 0xfe, 91 }; 92 93 struct dw_hdmi_mpll_config { 94 unsigned long mpixelclock; 95 struct { 96 u16 cpce; 97 u16 gmp; 98 } res[DW_HDMI_RES_MAX]; 99 }; 100 101 struct dw_hdmi_curr_ctrl { 102 unsigned long mpixelclock; 103 u16 curr[DW_HDMI_RES_MAX]; 104 }; 105 106 struct dw_hdmi_phy_config { 107 unsigned long mpixelclock; 108 u16 sym_ctr; /*clock symbol and transmitter control*/ 109 u16 term; /*transmission termination value*/ 110 u16 vlev_ctr; /* voltage level control */ 111 }; 112 113 struct dw_hdmi_phy_ops { 114 int (*init)(struct dw_hdmi *hdmi, void *data, 115 struct drm_display_mode *mode); 116 void (*disable)(struct dw_hdmi *hdmi, void *data); 117 enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi, void *data); 118 void (*update_hpd)(struct dw_hdmi *hdmi, void *data, 119 bool force, bool disabled, bool rxsense); 120 void (*setup_hpd)(struct dw_hdmi *hdmi, void *data); 121 }; 122 123 struct dw_hdmi_plat_data { 124 struct regmap *regm; 125 enum drm_mode_status (*mode_valid)(struct drm_connector *connector, 126 const struct drm_display_mode *mode); 127 unsigned long input_bus_format; 128 unsigned long input_bus_encoding; 129 130 /* Vendor PHY support */ 131 const struct dw_hdmi_phy_ops *phy_ops; 132 const char *phy_name; 133 void *phy_data; 134 unsigned int phy_force_vendor; 135 136 /* Synopsys PHY support */ 137 const struct dw_hdmi_mpll_config *mpll_cfg; 138 const struct dw_hdmi_curr_ctrl *cur_ctr; 139 const struct dw_hdmi_phy_config *phy_config; 140 int (*configure_phy)(struct dw_hdmi *hdmi, 141 const struct dw_hdmi_plat_data *pdata, 142 unsigned long mpixelclock); 143 }; 144 145 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, 146 const struct dw_hdmi_plat_data *plat_data); 147 void dw_hdmi_remove(struct dw_hdmi *hdmi); 148 void dw_hdmi_unbind(struct dw_hdmi *hdmi); 149 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, 150 struct drm_encoder *encoder, 151 const struct dw_hdmi_plat_data *plat_data); 152 153 void dw_hdmi_resume(struct dw_hdmi *hdmi); 154 155 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense); 156 157 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); 158 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt); 159 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca); 160 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); 161 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi); 162 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi); 163 164 /* PHY configuration */ 165 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address); 166 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 167 unsigned char addr); 168 169 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable); 170 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable); 171 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi); 172 173 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 174 void *data); 175 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, 176 bool force, bool disabled, bool rxsense); 177 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data); 178 179 #endif /* __IMX_HDMI_H__ */ 180