15ca467c4SKeerthy /* 25ca467c4SKeerthy * OMAP Dual-Mode Timers 35ca467c4SKeerthy * 47f317d34SAlexander A. Klimov * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ 55ca467c4SKeerthy * Tarun Kanti DebBarma <tarun.kanti@ti.com> 65ca467c4SKeerthy * Thara Gopinath <thara@ti.com> 75ca467c4SKeerthy * 85ca467c4SKeerthy * Platform device conversion and hwmod support. 95ca467c4SKeerthy * 105ca467c4SKeerthy * Copyright (C) 2005 Nokia Corporation 115ca467c4SKeerthy * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com> 125ca467c4SKeerthy * PWM and clock framwork support by Timo Teras. 135ca467c4SKeerthy * 145ca467c4SKeerthy * This program is free software; you can redistribute it and/or modify it 155ca467c4SKeerthy * under the terms of the GNU General Public License as published by the 165ca467c4SKeerthy * Free Software Foundation; either version 2 of the License, or (at your 175ca467c4SKeerthy * option) any later version. 185ca467c4SKeerthy * 195ca467c4SKeerthy * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 205ca467c4SKeerthy * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 215ca467c4SKeerthy * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 225ca467c4SKeerthy * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 235ca467c4SKeerthy * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 245ca467c4SKeerthy * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255ca467c4SKeerthy * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 265ca467c4SKeerthy * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275ca467c4SKeerthy * 285ca467c4SKeerthy * You should have received a copy of the GNU General Public License along 295ca467c4SKeerthy * with this program; if not, write to the Free Software Foundation, Inc., 305ca467c4SKeerthy * 675 Mass Ave, Cambridge, MA 02139, USA. 315ca467c4SKeerthy */ 325ca467c4SKeerthy 335ca467c4SKeerthy #include <linux/delay.h> 345ca467c4SKeerthy #include <linux/io.h> 355ca467c4SKeerthy #include <linux/platform_device.h> 365ca467c4SKeerthy 37f7bda9eeSKeerthy #ifndef __CLOCKSOURCE_DMTIMER_H 38f7bda9eeSKeerthy #define __CLOCKSOURCE_DMTIMER_H 395ca467c4SKeerthy 405ca467c4SKeerthy /* clock sources */ 415ca467c4SKeerthy #define OMAP_TIMER_SRC_SYS_CLK 0x00 425ca467c4SKeerthy #define OMAP_TIMER_SRC_32_KHZ 0x01 435ca467c4SKeerthy #define OMAP_TIMER_SRC_EXT_CLK 0x02 445ca467c4SKeerthy 455ca467c4SKeerthy /* timer interrupt enable bits */ 465ca467c4SKeerthy #define OMAP_TIMER_INT_CAPTURE (1 << 2) 475ca467c4SKeerthy #define OMAP_TIMER_INT_OVERFLOW (1 << 1) 485ca467c4SKeerthy #define OMAP_TIMER_INT_MATCH (1 << 0) 495ca467c4SKeerthy 505ca467c4SKeerthy /* trigger types */ 515ca467c4SKeerthy #define OMAP_TIMER_TRIGGER_NONE 0x00 525ca467c4SKeerthy #define OMAP_TIMER_TRIGGER_OVERFLOW 0x01 535ca467c4SKeerthy #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 545ca467c4SKeerthy 555ca467c4SKeerthy /* timer capabilities used in hwmod database */ 565ca467c4SKeerthy #define OMAP_TIMER_SECURE 0x80000000 575ca467c4SKeerthy #define OMAP_TIMER_ALWON 0x40000000 585ca467c4SKeerthy #define OMAP_TIMER_HAS_PWM 0x20000000 595ca467c4SKeerthy #define OMAP_TIMER_NEEDS_RESET 0x10000000 605ca467c4SKeerthy #define OMAP_TIMER_HAS_DSP_IRQ 0x08000000 615ca467c4SKeerthy 625ca467c4SKeerthy struct omap_dm_timer { 635ca467c4SKeerthy }; 645ca467c4SKeerthy 655ca467c4SKeerthy u32 omap_dm_timer_modify_idlect_mask(u32 inputmask); 665ca467c4SKeerthy 675ca467c4SKeerthy /* 685ca467c4SKeerthy * Do not use the defines below, they are not needed. They should be only 695ca467c4SKeerthy * used by dmtimer.c and sys_timer related code. 705ca467c4SKeerthy */ 715ca467c4SKeerthy 725ca467c4SKeerthy /* 735ca467c4SKeerthy * The interrupt registers are different between v1 and v2 ip. 745ca467c4SKeerthy * These registers are offsets from timer->iobase. 755ca467c4SKeerthy */ 765ca467c4SKeerthy #define OMAP_TIMER_ID_OFFSET 0x00 775ca467c4SKeerthy #define OMAP_TIMER_OCP_CFG_OFFSET 0x10 785ca467c4SKeerthy 795ca467c4SKeerthy #define OMAP_TIMER_V1_SYS_STAT_OFFSET 0x14 805ca467c4SKeerthy #define OMAP_TIMER_V1_STAT_OFFSET 0x18 815ca467c4SKeerthy #define OMAP_TIMER_V1_INT_EN_OFFSET 0x1c 825ca467c4SKeerthy 835ca467c4SKeerthy #define OMAP_TIMER_V2_IRQSTATUS_RAW 0x24 845ca467c4SKeerthy #define OMAP_TIMER_V2_IRQSTATUS 0x28 855ca467c4SKeerthy #define OMAP_TIMER_V2_IRQENABLE_SET 0x2c 865ca467c4SKeerthy #define OMAP_TIMER_V2_IRQENABLE_CLR 0x30 875ca467c4SKeerthy 885ca467c4SKeerthy /* 895ca467c4SKeerthy * The functional registers have a different base on v1 and v2 ip. 905ca467c4SKeerthy * These registers are offsets from timer->func_base. The func_base 915ca467c4SKeerthy * is samae as io_base for v1 and io_base + 0x14 for v2 ip. 925ca467c4SKeerthy * 935ca467c4SKeerthy */ 945ca467c4SKeerthy #define OMAP_TIMER_V2_FUNC_OFFSET 0x14 955ca467c4SKeerthy 965ca467c4SKeerthy #define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20 975ca467c4SKeerthy #define _OMAP_TIMER_CTRL_OFFSET 0x24 985ca467c4SKeerthy #define OMAP_TIMER_CTRL_GPOCFG (1 << 14) 995ca467c4SKeerthy #define OMAP_TIMER_CTRL_CAPTMODE (1 << 13) 1005ca467c4SKeerthy #define OMAP_TIMER_CTRL_PT (1 << 12) 1015ca467c4SKeerthy #define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8) 1025ca467c4SKeerthy #define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8) 1035ca467c4SKeerthy #define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8) 1045ca467c4SKeerthy #define OMAP_TIMER_CTRL_SCPWM (1 << 7) 1055ca467c4SKeerthy #define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */ 1065ca467c4SKeerthy #define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */ 1075ca467c4SKeerthy #define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */ 1085ca467c4SKeerthy #define OMAP_TIMER_CTRL_POSTED (1 << 2) 1095ca467c4SKeerthy #define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */ 1105ca467c4SKeerthy #define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */ 1115ca467c4SKeerthy #define _OMAP_TIMER_COUNTER_OFFSET 0x28 1125ca467c4SKeerthy #define _OMAP_TIMER_LOAD_OFFSET 0x2c 1135ca467c4SKeerthy #define _OMAP_TIMER_TRIGGER_OFFSET 0x30 1145ca467c4SKeerthy #define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34 1155ca467c4SKeerthy #define WP_NONE 0 /* no write pending bit */ 1165ca467c4SKeerthy #define WP_TCLR (1 << 0) 1175ca467c4SKeerthy #define WP_TCRR (1 << 1) 1185ca467c4SKeerthy #define WP_TLDR (1 << 2) 1195ca467c4SKeerthy #define WP_TTGR (1 << 3) 1205ca467c4SKeerthy #define WP_TMAR (1 << 4) 1215ca467c4SKeerthy #define WP_TPIR (1 << 5) 1225ca467c4SKeerthy #define WP_TNIR (1 << 6) 1235ca467c4SKeerthy #define WP_TCVR (1 << 7) 1245ca467c4SKeerthy #define WP_TOCR (1 << 8) 1255ca467c4SKeerthy #define WP_TOWR (1 << 9) 1265ca467c4SKeerthy #define _OMAP_TIMER_MATCH_OFFSET 0x38 1275ca467c4SKeerthy #define _OMAP_TIMER_CAPTURE_OFFSET 0x3c 1285ca467c4SKeerthy #define _OMAP_TIMER_IF_CTRL_OFFSET 0x40 1295ca467c4SKeerthy #define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */ 1305ca467c4SKeerthy #define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */ 1315ca467c4SKeerthy #define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */ 1325ca467c4SKeerthy #define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */ 1335ca467c4SKeerthy #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */ 1345ca467c4SKeerthy #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */ 1355ca467c4SKeerthy 136f7bda9eeSKeerthy #endif /* __CLOCKSOURCE_DMTIMER_H */ 137