1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2*1bce1112SPeter Zijlstra
3*1bce1112SPeter Zijlstra /*
4*1bce1112SPeter Zijlstra * 'Generic' ticket-lock implementation.
5*1bce1112SPeter Zijlstra *
6*1bce1112SPeter Zijlstra * It relies on atomic_fetch_add() having well defined forward progress
7*1bce1112SPeter Zijlstra * guarantees under contention. If your architecture cannot provide this, stick
8*1bce1112SPeter Zijlstra * to a test-and-set lock.
9*1bce1112SPeter Zijlstra *
10*1bce1112SPeter Zijlstra * It also relies on atomic_fetch_add() being safe vs smp_store_release() on a
11*1bce1112SPeter Zijlstra * sub-word of the value. This is generally true for anything LL/SC although
12*1bce1112SPeter Zijlstra * you'd be hard pressed to find anything useful in architecture specifications
13*1bce1112SPeter Zijlstra * about this. If your architecture cannot do this you might be better off with
14*1bce1112SPeter Zijlstra * a test-and-set.
15*1bce1112SPeter Zijlstra *
16*1bce1112SPeter Zijlstra * It further assumes atomic_*_release() + atomic_*_acquire() is RCpc and hence
17*1bce1112SPeter Zijlstra * uses atomic_fetch_add() which is RCsc to create an RCsc hot path, along with
18*1bce1112SPeter Zijlstra * a full fence after the spin to upgrade the otherwise-RCpc
19*1bce1112SPeter Zijlstra * atomic_cond_read_acquire().
20*1bce1112SPeter Zijlstra *
21*1bce1112SPeter Zijlstra * The implementation uses smp_cond_load_acquire() to spin, so if the
22*1bce1112SPeter Zijlstra * architecture has WFE like instructions to sleep instead of poll for word
23*1bce1112SPeter Zijlstra * modifications be sure to implement that (see ARM64 for example).
24*1bce1112SPeter Zijlstra *
25*1bce1112SPeter Zijlstra */
26*1bce1112SPeter Zijlstra
27aafe4dbeSArnd Bergmann #ifndef __ASM_GENERIC_SPINLOCK_H
28aafe4dbeSArnd Bergmann #define __ASM_GENERIC_SPINLOCK_H
29*1bce1112SPeter Zijlstra
30*1bce1112SPeter Zijlstra #include <linux/atomic.h>
31*1bce1112SPeter Zijlstra #include <asm-generic/spinlock_types.h>
32*1bce1112SPeter Zijlstra
arch_spin_lock(arch_spinlock_t * lock)33*1bce1112SPeter Zijlstra static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
34*1bce1112SPeter Zijlstra {
35*1bce1112SPeter Zijlstra u32 val = atomic_fetch_add(1<<16, lock);
36*1bce1112SPeter Zijlstra u16 ticket = val >> 16;
37*1bce1112SPeter Zijlstra
38*1bce1112SPeter Zijlstra if (ticket == (u16)val)
39*1bce1112SPeter Zijlstra return;
40*1bce1112SPeter Zijlstra
41aafe4dbeSArnd Bergmann /*
42*1bce1112SPeter Zijlstra * atomic_cond_read_acquire() is RCpc, but rather than defining a
43*1bce1112SPeter Zijlstra * custom cond_read_rcsc() here we just emit a full fence. We only
44*1bce1112SPeter Zijlstra * need the prior reads before subsequent writes ordering from
45*1bce1112SPeter Zijlstra * smb_mb(), but as atomic_cond_read_acquire() just emits reads and we
46*1bce1112SPeter Zijlstra * have no outstanding writes due to the atomic_fetch_add() the extra
47*1bce1112SPeter Zijlstra * orderings are free.
48aafe4dbeSArnd Bergmann */
49*1bce1112SPeter Zijlstra atomic_cond_read_acquire(lock, ticket == (u16)VAL);
50*1bce1112SPeter Zijlstra smp_mb();
51*1bce1112SPeter Zijlstra }
52*1bce1112SPeter Zijlstra
arch_spin_trylock(arch_spinlock_t * lock)53*1bce1112SPeter Zijlstra static __always_inline bool arch_spin_trylock(arch_spinlock_t *lock)
54*1bce1112SPeter Zijlstra {
55*1bce1112SPeter Zijlstra u32 old = atomic_read(lock);
56*1bce1112SPeter Zijlstra
57*1bce1112SPeter Zijlstra if ((old >> 16) != (old & 0xffff))
58*1bce1112SPeter Zijlstra return false;
59*1bce1112SPeter Zijlstra
60*1bce1112SPeter Zijlstra return atomic_try_cmpxchg(lock, &old, old + (1<<16)); /* SC, for RCsc */
61*1bce1112SPeter Zijlstra }
62*1bce1112SPeter Zijlstra
arch_spin_unlock(arch_spinlock_t * lock)63*1bce1112SPeter Zijlstra static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
64*1bce1112SPeter Zijlstra {
65*1bce1112SPeter Zijlstra u16 *ptr = (u16 *)lock + IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
66*1bce1112SPeter Zijlstra u32 val = atomic_read(lock);
67*1bce1112SPeter Zijlstra
68*1bce1112SPeter Zijlstra smp_store_release(ptr, (u16)val + 1);
69*1bce1112SPeter Zijlstra }
70*1bce1112SPeter Zijlstra
arch_spin_is_locked(arch_spinlock_t * lock)71*1bce1112SPeter Zijlstra static __always_inline int arch_spin_is_locked(arch_spinlock_t *lock)
72*1bce1112SPeter Zijlstra {
73*1bce1112SPeter Zijlstra u32 val = atomic_read(lock);
74*1bce1112SPeter Zijlstra
75*1bce1112SPeter Zijlstra return ((val >> 16) != (val & 0xffff));
76*1bce1112SPeter Zijlstra }
77*1bce1112SPeter Zijlstra
arch_spin_is_contended(arch_spinlock_t * lock)78*1bce1112SPeter Zijlstra static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock)
79*1bce1112SPeter Zijlstra {
80*1bce1112SPeter Zijlstra u32 val = atomic_read(lock);
81*1bce1112SPeter Zijlstra
82*1bce1112SPeter Zijlstra return (s16)((val >> 16) - (val & 0xffff)) > 1;
83*1bce1112SPeter Zijlstra }
84*1bce1112SPeter Zijlstra
arch_spin_value_unlocked(arch_spinlock_t lock)85*1bce1112SPeter Zijlstra static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
86*1bce1112SPeter Zijlstra {
87*1bce1112SPeter Zijlstra return !arch_spin_is_locked(&lock);
88*1bce1112SPeter Zijlstra }
89*1bce1112SPeter Zijlstra
90*1bce1112SPeter Zijlstra #include <asm/qrwlock.h>
91aafe4dbeSArnd Bergmann
92aafe4dbeSArnd Bergmann #endif /* __ASM_GENERIC_SPINLOCK_H */
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