1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Name: actbl2.h - ACPI Table Definitions (tables not in ACPI spec) 5 * 6 * Copyright (C) 2000 - 2021, Intel Corp. 7 * 8 *****************************************************************************/ 9 10 #ifndef __ACTBL2_H__ 11 #define __ACTBL2_H__ 12 13 /******************************************************************************* 14 * 15 * Additional ACPI Tables (2) 16 * 17 * These tables are not consumed directly by the ACPICA subsystem, but are 18 * included here to support device drivers and the AML disassembler. 19 * 20 ******************************************************************************/ 21 22 /* 23 * Values for description table header signatures for tables defined in this 24 * file. Useful because they make it more difficult to inadvertently type in 25 * the wrong signature. 26 */ 27 #define ACPI_SIG_IORT "IORT" /* IO Remapping Table */ 28 #define ACPI_SIG_IVRS "IVRS" /* I/O Virtualization Reporting Structure */ 29 #define ACPI_SIG_LPIT "LPIT" /* Low Power Idle Table */ 30 #define ACPI_SIG_MADT "APIC" /* Multiple APIC Description Table */ 31 #define ACPI_SIG_MCFG "MCFG" /* PCI Memory Mapped Configuration table */ 32 #define ACPI_SIG_MCHI "MCHI" /* Management Controller Host Interface table */ 33 #define ACPI_SIG_MPST "MPST" /* Memory Power State Table */ 34 #define ACPI_SIG_MSCT "MSCT" /* Maximum System Characteristics Table */ 35 #define ACPI_SIG_MSDM "MSDM" /* Microsoft Data Management Table */ 36 #define ACPI_SIG_NFIT "NFIT" /* NVDIMM Firmware Interface Table */ 37 #define ACPI_SIG_PCCT "PCCT" /* Platform Communications Channel Table */ 38 #define ACPI_SIG_PDTT "PDTT" /* Platform Debug Trigger Table */ 39 #define ACPI_SIG_PHAT "PHAT" /* Platform Health Assessment Table */ 40 #define ACPI_SIG_PMTT "PMTT" /* Platform Memory Topology Table */ 41 #define ACPI_SIG_PPTT "PPTT" /* Processor Properties Topology Table */ 42 #define ACPI_SIG_RASF "RASF" /* RAS Feature table */ 43 #define ACPI_SIG_SBST "SBST" /* Smart Battery Specification Table */ 44 #define ACPI_SIG_SDEI "SDEI" /* Software Delegated Exception Interface Table */ 45 #define ACPI_SIG_SDEV "SDEV" /* Secure Devices table */ 46 #define ACPI_SIG_NHLT "NHLT" /* Non-HDAudio Link Table */ 47 48 /* 49 * All tables must be byte-packed to match the ACPI specification, since 50 * the tables are provided by the system BIOS. 51 */ 52 #pragma pack(1) 53 54 /* 55 * Note: C bitfields are not used for this reason: 56 * 57 * "Bitfields are great and easy to read, but unfortunately the C language 58 * does not specify the layout of bitfields in memory, which means they are 59 * essentially useless for dealing with packed data in on-disk formats or 60 * binary wire protocols." (Or ACPI tables and buffers.) "If you ask me, 61 * this decision was a design error in C. Ritchie could have picked an order 62 * and stuck with it." Norman Ramsey. 63 * See http://stackoverflow.com/a/1053662/41661 64 */ 65 66 /******************************************************************************* 67 * 68 * IORT - IO Remapping Table 69 * 70 * Conforms to "IO Remapping Table System Software on ARM Platforms", 71 * Document number: ARM DEN 0049E.b, Feb 2021 72 * 73 ******************************************************************************/ 74 75 struct acpi_table_iort { 76 struct acpi_table_header header; 77 u32 node_count; 78 u32 node_offset; 79 u32 reserved; 80 }; 81 82 /* 83 * IORT subtables 84 */ 85 struct acpi_iort_node { 86 u8 type; 87 u16 length; 88 u8 revision; 89 u32 identifier; 90 u32 mapping_count; 91 u32 mapping_offset; 92 char node_data[1]; 93 }; 94 95 /* Values for subtable Type above */ 96 97 enum acpi_iort_node_type { 98 ACPI_IORT_NODE_ITS_GROUP = 0x00, 99 ACPI_IORT_NODE_NAMED_COMPONENT = 0x01, 100 ACPI_IORT_NODE_PCI_ROOT_COMPLEX = 0x02, 101 ACPI_IORT_NODE_SMMU = 0x03, 102 ACPI_IORT_NODE_SMMU_V3 = 0x04, 103 ACPI_IORT_NODE_PMCG = 0x05, 104 ACPI_IORT_NODE_RMR = 0x06, 105 }; 106 107 struct acpi_iort_id_mapping { 108 u32 input_base; /* Lowest value in input range */ 109 u32 id_count; /* Number of IDs */ 110 u32 output_base; /* Lowest value in output range */ 111 u32 output_reference; /* A reference to the output node */ 112 u32 flags; 113 }; 114 115 /* Masks for Flags field above for IORT subtable */ 116 117 #define ACPI_IORT_ID_SINGLE_MAPPING (1) 118 119 struct acpi_iort_memory_access { 120 u32 cache_coherency; 121 u8 hints; 122 u16 reserved; 123 u8 memory_flags; 124 }; 125 126 /* Values for cache_coherency field above */ 127 128 #define ACPI_IORT_NODE_COHERENT 0x00000001 /* The device node is fully coherent */ 129 #define ACPI_IORT_NODE_NOT_COHERENT 0x00000000 /* The device node is not coherent */ 130 131 /* Masks for Hints field above */ 132 133 #define ACPI_IORT_HT_TRANSIENT (1) 134 #define ACPI_IORT_HT_WRITE (1<<1) 135 #define ACPI_IORT_HT_READ (1<<2) 136 #define ACPI_IORT_HT_OVERRIDE (1<<3) 137 138 /* Masks for memory_flags field above */ 139 140 #define ACPI_IORT_MF_COHERENCY (1) 141 #define ACPI_IORT_MF_ATTRIBUTES (1<<1) 142 143 /* 144 * IORT node specific subtables 145 */ 146 struct acpi_iort_its_group { 147 u32 its_count; 148 u32 identifiers[1]; /* GIC ITS identifier array */ 149 }; 150 151 struct acpi_iort_named_component { 152 u32 node_flags; 153 u64 memory_properties; /* Memory access properties */ 154 u8 memory_address_limit; /* Memory address size limit */ 155 char device_name[1]; /* Path of namespace object */ 156 }; 157 158 /* Masks for Flags field above */ 159 160 #define ACPI_IORT_NC_STALL_SUPPORTED (1) 161 #define ACPI_IORT_NC_PASID_BITS (31<<1) 162 163 struct acpi_iort_root_complex { 164 u64 memory_properties; /* Memory access properties */ 165 u32 ats_attribute; 166 u32 pci_segment_number; 167 u8 memory_address_limit; /* Memory address size limit */ 168 u8 reserved[3]; /* Reserved, must be zero */ 169 }; 170 171 /* Masks for ats_attribute field above */ 172 173 #define ACPI_IORT_ATS_SUPPORTED (1) /* The root complex ATS support */ 174 #define ACPI_IORT_PRI_SUPPORTED (1<<1) /* The root complex PRI support */ 175 #define ACPI_IORT_PASID_FWD_SUPPORTED (1<<2) /* The root complex PASID forward support */ 176 177 struct acpi_iort_smmu { 178 u64 base_address; /* SMMU base address */ 179 u64 span; /* Length of memory range */ 180 u32 model; 181 u32 flags; 182 u32 global_interrupt_offset; 183 u32 context_interrupt_count; 184 u32 context_interrupt_offset; 185 u32 pmu_interrupt_count; 186 u32 pmu_interrupt_offset; 187 u64 interrupts[1]; /* Interrupt array */ 188 }; 189 190 /* Values for Model field above */ 191 192 #define ACPI_IORT_SMMU_V1 0x00000000 /* Generic SMMUv1 */ 193 #define ACPI_IORT_SMMU_V2 0x00000001 /* Generic SMMUv2 */ 194 #define ACPI_IORT_SMMU_CORELINK_MMU400 0x00000002 /* ARM Corelink MMU-400 */ 195 #define ACPI_IORT_SMMU_CORELINK_MMU500 0x00000003 /* ARM Corelink MMU-500 */ 196 #define ACPI_IORT_SMMU_CORELINK_MMU401 0x00000004 /* ARM Corelink MMU-401 */ 197 #define ACPI_IORT_SMMU_CAVIUM_THUNDERX 0x00000005 /* Cavium thunder_x SMMUv2 */ 198 199 /* Masks for Flags field above */ 200 201 #define ACPI_IORT_SMMU_DVM_SUPPORTED (1) 202 #define ACPI_IORT_SMMU_COHERENT_WALK (1<<1) 203 204 /* Global interrupt format */ 205 206 struct acpi_iort_smmu_gsi { 207 u32 nsg_irpt; 208 u32 nsg_irpt_flags; 209 u32 nsg_cfg_irpt; 210 u32 nsg_cfg_irpt_flags; 211 }; 212 213 struct acpi_iort_smmu_v3 { 214 u64 base_address; /* SMMUv3 base address */ 215 u32 flags; 216 u32 reserved; 217 u64 vatos_address; 218 u32 model; 219 u32 event_gsiv; 220 u32 pri_gsiv; 221 u32 gerr_gsiv; 222 u32 sync_gsiv; 223 u32 pxm; 224 u32 id_mapping_index; 225 }; 226 227 /* Values for Model field above */ 228 229 #define ACPI_IORT_SMMU_V3_GENERIC 0x00000000 /* Generic SMMUv3 */ 230 #define ACPI_IORT_SMMU_V3_HISILICON_HI161X 0x00000001 /* hi_silicon Hi161x SMMUv3 */ 231 #define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x00000002 /* Cavium CN99xx SMMUv3 */ 232 233 /* Masks for Flags field above */ 234 235 #define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE (1) 236 #define ACPI_IORT_SMMU_V3_HTTU_OVERRIDE (3<<1) 237 #define ACPI_IORT_SMMU_V3_PXM_VALID (1<<3) 238 239 struct acpi_iort_pmcg { 240 u64 page0_base_address; 241 u32 overflow_gsiv; 242 u32 node_reference; 243 u64 page1_base_address; 244 }; 245 246 struct acpi_iort_rmr { 247 u32 flags; 248 u32 rmr_count; 249 u32 rmr_offset; 250 }; 251 252 struct acpi_iort_rmr_desc { 253 u64 base_address; 254 u64 length; 255 u32 reserved; 256 }; 257 258 /******************************************************************************* 259 * 260 * IVRS - I/O Virtualization Reporting Structure 261 * Version 1 262 * 263 * Conforms to "AMD I/O Virtualization Technology (IOMMU) Specification", 264 * Revision 1.26, February 2009. 265 * 266 ******************************************************************************/ 267 268 struct acpi_table_ivrs { 269 struct acpi_table_header header; /* Common ACPI table header */ 270 u32 info; /* Common virtualization info */ 271 u64 reserved; 272 }; 273 274 /* Values for Info field above */ 275 276 #define ACPI_IVRS_PHYSICAL_SIZE 0x00007F00 /* 7 bits, physical address size */ 277 #define ACPI_IVRS_VIRTUAL_SIZE 0x003F8000 /* 7 bits, virtual address size */ 278 #define ACPI_IVRS_ATS_RESERVED 0x00400000 /* ATS address translation range reserved */ 279 280 /* IVRS subtable header */ 281 282 struct acpi_ivrs_header { 283 u8 type; /* Subtable type */ 284 u8 flags; 285 u16 length; /* Subtable length */ 286 u16 device_id; /* ID of IOMMU */ 287 }; 288 289 /* Values for subtable Type above */ 290 291 enum acpi_ivrs_type { 292 ACPI_IVRS_TYPE_HARDWARE1 = 0x10, 293 ACPI_IVRS_TYPE_HARDWARE2 = 0x11, 294 ACPI_IVRS_TYPE_HARDWARE3 = 0x40, 295 ACPI_IVRS_TYPE_MEMORY1 = 0x20, 296 ACPI_IVRS_TYPE_MEMORY2 = 0x21, 297 ACPI_IVRS_TYPE_MEMORY3 = 0x22 298 }; 299 300 /* Masks for Flags field above for IVHD subtable */ 301 302 #define ACPI_IVHD_TT_ENABLE (1) 303 #define ACPI_IVHD_PASS_PW (1<<1) 304 #define ACPI_IVHD_RES_PASS_PW (1<<2) 305 #define ACPI_IVHD_ISOC (1<<3) 306 #define ACPI_IVHD_IOTLB (1<<4) 307 308 /* Masks for Flags field above for IVMD subtable */ 309 310 #define ACPI_IVMD_UNITY (1) 311 #define ACPI_IVMD_READ (1<<1) 312 #define ACPI_IVMD_WRITE (1<<2) 313 #define ACPI_IVMD_EXCLUSION_RANGE (1<<3) 314 315 /* 316 * IVRS subtables, correspond to Type in struct acpi_ivrs_header 317 */ 318 319 /* 0x10: I/O Virtualization Hardware Definition Block (IVHD) */ 320 321 struct acpi_ivrs_hardware_10 { 322 struct acpi_ivrs_header header; 323 u16 capability_offset; /* Offset for IOMMU control fields */ 324 u64 base_address; /* IOMMU control registers */ 325 u16 pci_segment_group; 326 u16 info; /* MSI number and unit ID */ 327 u32 feature_reporting; 328 }; 329 330 /* 0x11: I/O Virtualization Hardware Definition Block (IVHD) */ 331 332 struct acpi_ivrs_hardware_11 { 333 struct acpi_ivrs_header header; 334 u16 capability_offset; /* Offset for IOMMU control fields */ 335 u64 base_address; /* IOMMU control registers */ 336 u16 pci_segment_group; 337 u16 info; /* MSI number and unit ID */ 338 u32 attributes; 339 u64 efr_register_image; 340 u64 reserved; 341 }; 342 343 /* Masks for Info field above */ 344 345 #define ACPI_IVHD_MSI_NUMBER_MASK 0x001F /* 5 bits, MSI message number */ 346 #define ACPI_IVHD_UNIT_ID_MASK 0x1F00 /* 5 bits, unit_ID */ 347 348 /* 349 * Device Entries for IVHD subtable, appear after struct acpi_ivrs_hardware structure. 350 * Upper two bits of the Type field are the (encoded) length of the structure. 351 * Currently, only 4 and 8 byte entries are defined. 16 and 32 byte entries 352 * are reserved for future use but not defined. 353 */ 354 struct acpi_ivrs_de_header { 355 u8 type; 356 u16 id; 357 u8 data_setting; 358 }; 359 360 /* Length of device entry is in the top two bits of Type field above */ 361 362 #define ACPI_IVHD_ENTRY_LENGTH 0xC0 363 364 /* Values for device entry Type field above */ 365 366 enum acpi_ivrs_device_entry_type { 367 /* 4-byte device entries, all use struct acpi_ivrs_device4 */ 368 369 ACPI_IVRS_TYPE_PAD4 = 0, 370 ACPI_IVRS_TYPE_ALL = 1, 371 ACPI_IVRS_TYPE_SELECT = 2, 372 ACPI_IVRS_TYPE_START = 3, 373 ACPI_IVRS_TYPE_END = 4, 374 375 /* 8-byte device entries */ 376 377 ACPI_IVRS_TYPE_PAD8 = 64, 378 ACPI_IVRS_TYPE_NOT_USED = 65, 379 ACPI_IVRS_TYPE_ALIAS_SELECT = 66, /* Uses struct acpi_ivrs_device8a */ 380 ACPI_IVRS_TYPE_ALIAS_START = 67, /* Uses struct acpi_ivrs_device8a */ 381 ACPI_IVRS_TYPE_EXT_SELECT = 70, /* Uses struct acpi_ivrs_device8b */ 382 ACPI_IVRS_TYPE_EXT_START = 71, /* Uses struct acpi_ivrs_device8b */ 383 ACPI_IVRS_TYPE_SPECIAL = 72, /* Uses struct acpi_ivrs_device8c */ 384 385 /* Variable-length device entries */ 386 387 ACPI_IVRS_TYPE_HID = 240 /* Uses ACPI_IVRS_DEVICE_HID */ 388 }; 389 390 /* Values for Data field above */ 391 392 #define ACPI_IVHD_INIT_PASS (1) 393 #define ACPI_IVHD_EINT_PASS (1<<1) 394 #define ACPI_IVHD_NMI_PASS (1<<2) 395 #define ACPI_IVHD_SYSTEM_MGMT (3<<4) 396 #define ACPI_IVHD_LINT0_PASS (1<<6) 397 #define ACPI_IVHD_LINT1_PASS (1<<7) 398 399 /* Types 0-4: 4-byte device entry */ 400 401 struct acpi_ivrs_device4 { 402 struct acpi_ivrs_de_header header; 403 }; 404 405 /* Types 66-67: 8-byte device entry */ 406 407 struct acpi_ivrs_device8a { 408 struct acpi_ivrs_de_header header; 409 u8 reserved1; 410 u16 used_id; 411 u8 reserved2; 412 }; 413 414 /* Types 70-71: 8-byte device entry */ 415 416 struct acpi_ivrs_device8b { 417 struct acpi_ivrs_de_header header; 418 u32 extended_data; 419 }; 420 421 /* Values for extended_data above */ 422 423 #define ACPI_IVHD_ATS_DISABLED (1<<31) 424 425 /* Type 72: 8-byte device entry */ 426 427 struct acpi_ivrs_device8c { 428 struct acpi_ivrs_de_header header; 429 u8 handle; 430 u16 used_id; 431 u8 variety; 432 }; 433 434 /* Values for Variety field above */ 435 436 #define ACPI_IVHD_IOAPIC 1 437 #define ACPI_IVHD_HPET 2 438 439 /* Type 240: variable-length device entry */ 440 441 struct acpi_ivrs_device_hid { 442 struct acpi_ivrs_de_header header; 443 u64 acpi_hid; 444 u64 acpi_cid; 445 u8 uid_type; 446 u8 uid_length; 447 }; 448 449 /* 0x20, 0x21, 0x22: I/O Virtualization Memory Definition Block (IVMD) */ 450 451 struct acpi_ivrs_memory { 452 struct acpi_ivrs_header header; 453 u16 aux_data; 454 u64 reserved; 455 u64 start_address; 456 u64 memory_length; 457 }; 458 459 /******************************************************************************* 460 * 461 * LPIT - Low Power Idle Table 462 * 463 * Conforms to "ACPI Low Power Idle Table (LPIT)" July 2014. 464 * 465 ******************************************************************************/ 466 467 struct acpi_table_lpit { 468 struct acpi_table_header header; /* Common ACPI table header */ 469 }; 470 471 /* LPIT subtable header */ 472 473 struct acpi_lpit_header { 474 u32 type; /* Subtable type */ 475 u32 length; /* Subtable length */ 476 u16 unique_id; 477 u16 reserved; 478 u32 flags; 479 }; 480 481 /* Values for subtable Type above */ 482 483 enum acpi_lpit_type { 484 ACPI_LPIT_TYPE_NATIVE_CSTATE = 0x00, 485 ACPI_LPIT_TYPE_RESERVED = 0x01 /* 1 and above are reserved */ 486 }; 487 488 /* Masks for Flags field above */ 489 490 #define ACPI_LPIT_STATE_DISABLED (1) 491 #define ACPI_LPIT_NO_COUNTER (1<<1) 492 493 /* 494 * LPIT subtables, correspond to Type in struct acpi_lpit_header 495 */ 496 497 /* 0x00: Native C-state instruction based LPI structure */ 498 499 struct acpi_lpit_native { 500 struct acpi_lpit_header header; 501 struct acpi_generic_address entry_trigger; 502 u32 residency; 503 u32 latency; 504 struct acpi_generic_address residency_counter; 505 u64 counter_frequency; 506 }; 507 508 /******************************************************************************* 509 * 510 * MADT - Multiple APIC Description Table 511 * Version 3 512 * 513 ******************************************************************************/ 514 515 struct acpi_table_madt { 516 struct acpi_table_header header; /* Common ACPI table header */ 517 u32 address; /* Physical address of local APIC */ 518 u32 flags; 519 }; 520 521 /* Masks for Flags field above */ 522 523 #define ACPI_MADT_PCAT_COMPAT (1) /* 00: System also has dual 8259s */ 524 525 /* Values for PCATCompat flag */ 526 527 #define ACPI_MADT_DUAL_PIC 1 528 #define ACPI_MADT_MULTIPLE_APIC 0 529 530 /* Values for MADT subtable type in struct acpi_subtable_header */ 531 532 enum acpi_madt_type { 533 ACPI_MADT_TYPE_LOCAL_APIC = 0, 534 ACPI_MADT_TYPE_IO_APIC = 1, 535 ACPI_MADT_TYPE_INTERRUPT_OVERRIDE = 2, 536 ACPI_MADT_TYPE_NMI_SOURCE = 3, 537 ACPI_MADT_TYPE_LOCAL_APIC_NMI = 4, 538 ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE = 5, 539 ACPI_MADT_TYPE_IO_SAPIC = 6, 540 ACPI_MADT_TYPE_LOCAL_SAPIC = 7, 541 ACPI_MADT_TYPE_INTERRUPT_SOURCE = 8, 542 ACPI_MADT_TYPE_LOCAL_X2APIC = 9, 543 ACPI_MADT_TYPE_LOCAL_X2APIC_NMI = 10, 544 ACPI_MADT_TYPE_GENERIC_INTERRUPT = 11, 545 ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR = 12, 546 ACPI_MADT_TYPE_GENERIC_MSI_FRAME = 13, 547 ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR = 14, 548 ACPI_MADT_TYPE_GENERIC_TRANSLATOR = 15, 549 ACPI_MADT_TYPE_MULTIPROC_WAKEUP = 16, 550 ACPI_MADT_TYPE_RESERVED = 17 /* 17 and greater are reserved */ 551 }; 552 553 /* 554 * MADT Subtables, correspond to Type in struct acpi_subtable_header 555 */ 556 557 /* 0: Processor Local APIC */ 558 559 struct acpi_madt_local_apic { 560 struct acpi_subtable_header header; 561 u8 processor_id; /* ACPI processor id */ 562 u8 id; /* Processor's local APIC id */ 563 u32 lapic_flags; 564 }; 565 566 /* 1: IO APIC */ 567 568 struct acpi_madt_io_apic { 569 struct acpi_subtable_header header; 570 u8 id; /* I/O APIC ID */ 571 u8 reserved; /* reserved - must be zero */ 572 u32 address; /* APIC physical address */ 573 u32 global_irq_base; /* Global system interrupt where INTI lines start */ 574 }; 575 576 /* 2: Interrupt Override */ 577 578 struct acpi_madt_interrupt_override { 579 struct acpi_subtable_header header; 580 u8 bus; /* 0 - ISA */ 581 u8 source_irq; /* Interrupt source (IRQ) */ 582 u32 global_irq; /* Global system interrupt */ 583 u16 inti_flags; 584 }; 585 586 /* 3: NMI Source */ 587 588 struct acpi_madt_nmi_source { 589 struct acpi_subtable_header header; 590 u16 inti_flags; 591 u32 global_irq; /* Global system interrupt */ 592 }; 593 594 /* 4: Local APIC NMI */ 595 596 struct acpi_madt_local_apic_nmi { 597 struct acpi_subtable_header header; 598 u8 processor_id; /* ACPI processor id */ 599 u16 inti_flags; 600 u8 lint; /* LINTn to which NMI is connected */ 601 }; 602 603 /* 5: Address Override */ 604 605 struct acpi_madt_local_apic_override { 606 struct acpi_subtable_header header; 607 u16 reserved; /* Reserved, must be zero */ 608 u64 address; /* APIC physical address */ 609 }; 610 611 /* 6: I/O Sapic */ 612 613 struct acpi_madt_io_sapic { 614 struct acpi_subtable_header header; 615 u8 id; /* I/O SAPIC ID */ 616 u8 reserved; /* Reserved, must be zero */ 617 u32 global_irq_base; /* Global interrupt for SAPIC start */ 618 u64 address; /* SAPIC physical address */ 619 }; 620 621 /* 7: Local Sapic */ 622 623 struct acpi_madt_local_sapic { 624 struct acpi_subtable_header header; 625 u8 processor_id; /* ACPI processor id */ 626 u8 id; /* SAPIC ID */ 627 u8 eid; /* SAPIC EID */ 628 u8 reserved[3]; /* Reserved, must be zero */ 629 u32 lapic_flags; 630 u32 uid; /* Numeric UID - ACPI 3.0 */ 631 char uid_string[1]; /* String UID - ACPI 3.0 */ 632 }; 633 634 /* 8: Platform Interrupt Source */ 635 636 struct acpi_madt_interrupt_source { 637 struct acpi_subtable_header header; 638 u16 inti_flags; 639 u8 type; /* 1=PMI, 2=INIT, 3=corrected */ 640 u8 id; /* Processor ID */ 641 u8 eid; /* Processor EID */ 642 u8 io_sapic_vector; /* Vector value for PMI interrupts */ 643 u32 global_irq; /* Global system interrupt */ 644 u32 flags; /* Interrupt Source Flags */ 645 }; 646 647 /* Masks for Flags field above */ 648 649 #define ACPI_MADT_CPEI_OVERRIDE (1) 650 651 /* 9: Processor Local X2APIC (ACPI 4.0) */ 652 653 struct acpi_madt_local_x2apic { 654 struct acpi_subtable_header header; 655 u16 reserved; /* reserved - must be zero */ 656 u32 local_apic_id; /* Processor x2APIC ID */ 657 u32 lapic_flags; 658 u32 uid; /* ACPI processor UID */ 659 }; 660 661 /* 10: Local X2APIC NMI (ACPI 4.0) */ 662 663 struct acpi_madt_local_x2apic_nmi { 664 struct acpi_subtable_header header; 665 u16 inti_flags; 666 u32 uid; /* ACPI processor UID */ 667 u8 lint; /* LINTn to which NMI is connected */ 668 u8 reserved[3]; /* reserved - must be zero */ 669 }; 670 671 /* 11: Generic interrupt - GICC (ACPI 5.0 + ACPI 6.0 + ACPI 6.3 changes) */ 672 673 struct acpi_madt_generic_interrupt { 674 struct acpi_subtable_header header; 675 u16 reserved; /* reserved - must be zero */ 676 u32 cpu_interface_number; 677 u32 uid; 678 u32 flags; 679 u32 parking_version; 680 u32 performance_interrupt; 681 u64 parked_address; 682 u64 base_address; 683 u64 gicv_base_address; 684 u64 gich_base_address; 685 u32 vgic_interrupt; 686 u64 gicr_base_address; 687 u64 arm_mpidr; 688 u8 efficiency_class; 689 u8 reserved2[1]; 690 u16 spe_interrupt; /* ACPI 6.3 */ 691 }; 692 693 /* Masks for Flags field above */ 694 695 /* ACPI_MADT_ENABLED (1) Processor is usable if set */ 696 #define ACPI_MADT_PERFORMANCE_IRQ_MODE (1<<1) /* 01: Performance Interrupt Mode */ 697 #define ACPI_MADT_VGIC_IRQ_MODE (1<<2) /* 02: VGIC Maintenance Interrupt mode */ 698 699 /* 12: Generic Distributor (ACPI 5.0 + ACPI 6.0 changes) */ 700 701 struct acpi_madt_generic_distributor { 702 struct acpi_subtable_header header; 703 u16 reserved; /* reserved - must be zero */ 704 u32 gic_id; 705 u64 base_address; 706 u32 global_irq_base; 707 u8 version; 708 u8 reserved2[3]; /* reserved - must be zero */ 709 }; 710 711 /* Values for Version field above */ 712 713 enum acpi_madt_gic_version { 714 ACPI_MADT_GIC_VERSION_NONE = 0, 715 ACPI_MADT_GIC_VERSION_V1 = 1, 716 ACPI_MADT_GIC_VERSION_V2 = 2, 717 ACPI_MADT_GIC_VERSION_V3 = 3, 718 ACPI_MADT_GIC_VERSION_V4 = 4, 719 ACPI_MADT_GIC_VERSION_RESERVED = 5 /* 5 and greater are reserved */ 720 }; 721 722 /* 13: Generic MSI Frame (ACPI 5.1) */ 723 724 struct acpi_madt_generic_msi_frame { 725 struct acpi_subtable_header header; 726 u16 reserved; /* reserved - must be zero */ 727 u32 msi_frame_id; 728 u64 base_address; 729 u32 flags; 730 u16 spi_count; 731 u16 spi_base; 732 }; 733 734 /* Masks for Flags field above */ 735 736 #define ACPI_MADT_OVERRIDE_SPI_VALUES (1) 737 738 /* 14: Generic Redistributor (ACPI 5.1) */ 739 740 struct acpi_madt_generic_redistributor { 741 struct acpi_subtable_header header; 742 u16 reserved; /* reserved - must be zero */ 743 u64 base_address; 744 u32 length; 745 }; 746 747 /* 15: Generic Translator (ACPI 6.0) */ 748 749 struct acpi_madt_generic_translator { 750 struct acpi_subtable_header header; 751 u16 reserved; /* reserved - must be zero */ 752 u32 translation_id; 753 u64 base_address; 754 u32 reserved2; 755 }; 756 757 /* 16: Multiprocessor wakeup (ACPI 6.4) */ 758 759 struct acpi_madt_multiproc_wakeup { 760 struct acpi_subtable_header header; 761 u16 mailbox_version; 762 u32 reserved; /* reserved - must be zero */ 763 u64 base_address; 764 }; 765 766 /* 767 * Common flags fields for MADT subtables 768 */ 769 770 /* MADT Local APIC flags */ 771 772 #define ACPI_MADT_ENABLED (1) /* 00: Processor is usable if set */ 773 774 /* MADT MPS INTI flags (inti_flags) */ 775 776 #define ACPI_MADT_POLARITY_MASK (3) /* 00-01: Polarity of APIC I/O input signals */ 777 #define ACPI_MADT_TRIGGER_MASK (3<<2) /* 02-03: Trigger mode of APIC input signals */ 778 779 /* Values for MPS INTI flags */ 780 781 #define ACPI_MADT_POLARITY_CONFORMS 0 782 #define ACPI_MADT_POLARITY_ACTIVE_HIGH 1 783 #define ACPI_MADT_POLARITY_RESERVED 2 784 #define ACPI_MADT_POLARITY_ACTIVE_LOW 3 785 786 #define ACPI_MADT_TRIGGER_CONFORMS (0) 787 #define ACPI_MADT_TRIGGER_EDGE (1<<2) 788 #define ACPI_MADT_TRIGGER_RESERVED (2<<2) 789 #define ACPI_MADT_TRIGGER_LEVEL (3<<2) 790 791 /******************************************************************************* 792 * 793 * MCFG - PCI Memory Mapped Configuration table and subtable 794 * Version 1 795 * 796 * Conforms to "PCI Firmware Specification", Revision 3.0, June 20, 2005 797 * 798 ******************************************************************************/ 799 800 struct acpi_table_mcfg { 801 struct acpi_table_header header; /* Common ACPI table header */ 802 u8 reserved[8]; 803 }; 804 805 /* Subtable */ 806 807 struct acpi_mcfg_allocation { 808 u64 address; /* Base address, processor-relative */ 809 u16 pci_segment; /* PCI segment group number */ 810 u8 start_bus_number; /* Starting PCI Bus number */ 811 u8 end_bus_number; /* Final PCI Bus number */ 812 u32 reserved; 813 }; 814 815 /******************************************************************************* 816 * 817 * MCHI - Management Controller Host Interface Table 818 * Version 1 819 * 820 * Conforms to "Management Component Transport Protocol (MCTP) Host 821 * Interface Specification", Revision 1.0.0a, October 13, 2009 822 * 823 ******************************************************************************/ 824 825 struct acpi_table_mchi { 826 struct acpi_table_header header; /* Common ACPI table header */ 827 u8 interface_type; 828 u8 protocol; 829 u64 protocol_data; 830 u8 interrupt_type; 831 u8 gpe; 832 u8 pci_device_flag; 833 u32 global_interrupt; 834 struct acpi_generic_address control_register; 835 u8 pci_segment; 836 u8 pci_bus; 837 u8 pci_device; 838 u8 pci_function; 839 }; 840 841 /******************************************************************************* 842 * 843 * MPST - Memory Power State Table (ACPI 5.0) 844 * Version 1 845 * 846 ******************************************************************************/ 847 848 #define ACPI_MPST_CHANNEL_INFO \ 849 u8 channel_id; \ 850 u8 reserved1[3]; \ 851 u16 power_node_count; \ 852 u16 reserved2; 853 854 /* Main table */ 855 856 struct acpi_table_mpst { 857 struct acpi_table_header header; /* Common ACPI table header */ 858 ACPI_MPST_CHANNEL_INFO /* Platform Communication Channel */ 859 }; 860 861 /* Memory Platform Communication Channel Info */ 862 863 struct acpi_mpst_channel { 864 ACPI_MPST_CHANNEL_INFO /* Platform Communication Channel */ 865 }; 866 867 /* Memory Power Node Structure */ 868 869 struct acpi_mpst_power_node { 870 u8 flags; 871 u8 reserved1; 872 u16 node_id; 873 u32 length; 874 u64 range_address; 875 u64 range_length; 876 u32 num_power_states; 877 u32 num_physical_components; 878 }; 879 880 /* Values for Flags field above */ 881 882 #define ACPI_MPST_ENABLED 1 883 #define ACPI_MPST_POWER_MANAGED 2 884 #define ACPI_MPST_HOT_PLUG_CAPABLE 4 885 886 /* Memory Power State Structure (follows POWER_NODE above) */ 887 888 struct acpi_mpst_power_state { 889 u8 power_state; 890 u8 info_index; 891 }; 892 893 /* Physical Component ID Structure (follows POWER_STATE above) */ 894 895 struct acpi_mpst_component { 896 u16 component_id; 897 }; 898 899 /* Memory Power State Characteristics Structure (follows all POWER_NODEs) */ 900 901 struct acpi_mpst_data_hdr { 902 u16 characteristics_count; 903 u16 reserved; 904 }; 905 906 struct acpi_mpst_power_data { 907 u8 structure_id; 908 u8 flags; 909 u16 reserved1; 910 u32 average_power; 911 u32 power_saving; 912 u64 exit_latency; 913 u64 reserved2; 914 }; 915 916 /* Values for Flags field above */ 917 918 #define ACPI_MPST_PRESERVE 1 919 #define ACPI_MPST_AUTOENTRY 2 920 #define ACPI_MPST_AUTOEXIT 4 921 922 /* Shared Memory Region (not part of an ACPI table) */ 923 924 struct acpi_mpst_shared { 925 u32 signature; 926 u16 pcc_command; 927 u16 pcc_status; 928 u32 command_register; 929 u32 status_register; 930 u32 power_state_id; 931 u32 power_node_id; 932 u64 energy_consumed; 933 u64 average_power; 934 }; 935 936 /******************************************************************************* 937 * 938 * MSCT - Maximum System Characteristics Table (ACPI 4.0) 939 * Version 1 940 * 941 ******************************************************************************/ 942 943 struct acpi_table_msct { 944 struct acpi_table_header header; /* Common ACPI table header */ 945 u32 proximity_offset; /* Location of proximity info struct(s) */ 946 u32 max_proximity_domains; /* Max number of proximity domains */ 947 u32 max_clock_domains; /* Max number of clock domains */ 948 u64 max_address; /* Max physical address in system */ 949 }; 950 951 /* subtable - Maximum Proximity Domain Information. Version 1 */ 952 953 struct acpi_msct_proximity { 954 u8 revision; 955 u8 length; 956 u32 range_start; /* Start of domain range */ 957 u32 range_end; /* End of domain range */ 958 u32 processor_capacity; 959 u64 memory_capacity; /* In bytes */ 960 }; 961 962 /******************************************************************************* 963 * 964 * MSDM - Microsoft Data Management table 965 * 966 * Conforms to "Microsoft Software Licensing Tables (SLIC and MSDM)", 967 * November 29, 2011. Copyright 2011 Microsoft 968 * 969 ******************************************************************************/ 970 971 /* Basic MSDM table is only the common ACPI header */ 972 973 struct acpi_table_msdm { 974 struct acpi_table_header header; /* Common ACPI table header */ 975 }; 976 977 /******************************************************************************* 978 * 979 * NFIT - NVDIMM Interface Table (ACPI 6.0+) 980 * Version 1 981 * 982 ******************************************************************************/ 983 984 struct acpi_table_nfit { 985 struct acpi_table_header header; /* Common ACPI table header */ 986 u32 reserved; /* Reserved, must be zero */ 987 }; 988 989 /* Subtable header for NFIT */ 990 991 struct acpi_nfit_header { 992 u16 type; 993 u16 length; 994 }; 995 996 /* Values for subtable type in struct acpi_nfit_header */ 997 998 enum acpi_nfit_type { 999 ACPI_NFIT_TYPE_SYSTEM_ADDRESS = 0, 1000 ACPI_NFIT_TYPE_MEMORY_MAP = 1, 1001 ACPI_NFIT_TYPE_INTERLEAVE = 2, 1002 ACPI_NFIT_TYPE_SMBIOS = 3, 1003 ACPI_NFIT_TYPE_CONTROL_REGION = 4, 1004 ACPI_NFIT_TYPE_DATA_REGION = 5, 1005 ACPI_NFIT_TYPE_FLUSH_ADDRESS = 6, 1006 ACPI_NFIT_TYPE_CAPABILITIES = 7, 1007 ACPI_NFIT_TYPE_RESERVED = 8 /* 8 and greater are reserved */ 1008 }; 1009 1010 /* 1011 * NFIT Subtables 1012 */ 1013 1014 /* 0: System Physical Address Range Structure */ 1015 1016 struct acpi_nfit_system_address { 1017 struct acpi_nfit_header header; 1018 u16 range_index; 1019 u16 flags; 1020 u32 reserved; /* Reserved, must be zero */ 1021 u32 proximity_domain; 1022 u8 range_guid[16]; 1023 u64 address; 1024 u64 length; 1025 u64 memory_mapping; 1026 u64 location_cookie; /* ACPI 6.4 */ 1027 }; 1028 1029 /* Flags */ 1030 1031 #define ACPI_NFIT_ADD_ONLINE_ONLY (1) /* 00: Add/Online Operation Only */ 1032 #define ACPI_NFIT_PROXIMITY_VALID (1<<1) /* 01: Proximity Domain Valid */ 1033 #define ACPI_NFIT_LOCATION_COOKIE_VALID (1<<2) /* 02: SPA location cookie valid (ACPI 6.4) */ 1034 1035 /* Range Type GUIDs appear in the include/acuuid.h file */ 1036 1037 /* 1: Memory Device to System Address Range Map Structure */ 1038 1039 struct acpi_nfit_memory_map { 1040 struct acpi_nfit_header header; 1041 u32 device_handle; 1042 u16 physical_id; 1043 u16 region_id; 1044 u16 range_index; 1045 u16 region_index; 1046 u64 region_size; 1047 u64 region_offset; 1048 u64 address; 1049 u16 interleave_index; 1050 u16 interleave_ways; 1051 u16 flags; 1052 u16 reserved; /* Reserved, must be zero */ 1053 }; 1054 1055 /* Flags */ 1056 1057 #define ACPI_NFIT_MEM_SAVE_FAILED (1) /* 00: Last SAVE to Memory Device failed */ 1058 #define ACPI_NFIT_MEM_RESTORE_FAILED (1<<1) /* 01: Last RESTORE from Memory Device failed */ 1059 #define ACPI_NFIT_MEM_FLUSH_FAILED (1<<2) /* 02: Platform flush failed */ 1060 #define ACPI_NFIT_MEM_NOT_ARMED (1<<3) /* 03: Memory Device is not armed */ 1061 #define ACPI_NFIT_MEM_HEALTH_OBSERVED (1<<4) /* 04: Memory Device observed SMART/health events */ 1062 #define ACPI_NFIT_MEM_HEALTH_ENABLED (1<<5) /* 05: SMART/health events enabled */ 1063 #define ACPI_NFIT_MEM_MAP_FAILED (1<<6) /* 06: Mapping to SPA failed */ 1064 1065 /* 2: Interleave Structure */ 1066 1067 struct acpi_nfit_interleave { 1068 struct acpi_nfit_header header; 1069 u16 interleave_index; 1070 u16 reserved; /* Reserved, must be zero */ 1071 u32 line_count; 1072 u32 line_size; 1073 u32 line_offset[1]; /* Variable length */ 1074 }; 1075 1076 /* 3: SMBIOS Management Information Structure */ 1077 1078 struct acpi_nfit_smbios { 1079 struct acpi_nfit_header header; 1080 u32 reserved; /* Reserved, must be zero */ 1081 u8 data[1]; /* Variable length */ 1082 }; 1083 1084 /* 4: NVDIMM Control Region Structure */ 1085 1086 struct acpi_nfit_control_region { 1087 struct acpi_nfit_header header; 1088 u16 region_index; 1089 u16 vendor_id; 1090 u16 device_id; 1091 u16 revision_id; 1092 u16 subsystem_vendor_id; 1093 u16 subsystem_device_id; 1094 u16 subsystem_revision_id; 1095 u8 valid_fields; 1096 u8 manufacturing_location; 1097 u16 manufacturing_date; 1098 u8 reserved[2]; /* Reserved, must be zero */ 1099 u32 serial_number; 1100 u16 code; 1101 u16 windows; 1102 u64 window_size; 1103 u64 command_offset; 1104 u64 command_size; 1105 u64 status_offset; 1106 u64 status_size; 1107 u16 flags; 1108 u8 reserved1[6]; /* Reserved, must be zero */ 1109 }; 1110 1111 /* Flags */ 1112 1113 #define ACPI_NFIT_CONTROL_BUFFERED (1) /* Block Data Windows implementation is buffered */ 1114 1115 /* valid_fields bits */ 1116 1117 #define ACPI_NFIT_CONTROL_MFG_INFO_VALID (1) /* Manufacturing fields are valid */ 1118 1119 /* 5: NVDIMM Block Data Window Region Structure */ 1120 1121 struct acpi_nfit_data_region { 1122 struct acpi_nfit_header header; 1123 u16 region_index; 1124 u16 windows; 1125 u64 offset; 1126 u64 size; 1127 u64 capacity; 1128 u64 start_address; 1129 }; 1130 1131 /* 6: Flush Hint Address Structure */ 1132 1133 struct acpi_nfit_flush_address { 1134 struct acpi_nfit_header header; 1135 u32 device_handle; 1136 u16 hint_count; 1137 u8 reserved[6]; /* Reserved, must be zero */ 1138 u64 hint_address[1]; /* Variable length */ 1139 }; 1140 1141 /* 7: Platform Capabilities Structure */ 1142 1143 struct acpi_nfit_capabilities { 1144 struct acpi_nfit_header header; 1145 u8 highest_capability; 1146 u8 reserved[3]; /* Reserved, must be zero */ 1147 u32 capabilities; 1148 u32 reserved2; 1149 }; 1150 1151 /* Capabilities Flags */ 1152 1153 #define ACPI_NFIT_CAPABILITY_CACHE_FLUSH (1) /* 00: Cache Flush to NVDIMM capable */ 1154 #define ACPI_NFIT_CAPABILITY_MEM_FLUSH (1<<1) /* 01: Memory Flush to NVDIMM capable */ 1155 #define ACPI_NFIT_CAPABILITY_MEM_MIRRORING (1<<2) /* 02: Memory Mirroring capable */ 1156 1157 /* 1158 * NFIT/DVDIMM device handle support - used as the _ADR for each NVDIMM 1159 */ 1160 struct nfit_device_handle { 1161 u32 handle; 1162 }; 1163 1164 /* Device handle construction and extraction macros */ 1165 1166 #define ACPI_NFIT_DIMM_NUMBER_MASK 0x0000000F 1167 #define ACPI_NFIT_CHANNEL_NUMBER_MASK 0x000000F0 1168 #define ACPI_NFIT_MEMORY_ID_MASK 0x00000F00 1169 #define ACPI_NFIT_SOCKET_ID_MASK 0x0000F000 1170 #define ACPI_NFIT_NODE_ID_MASK 0x0FFF0000 1171 1172 #define ACPI_NFIT_DIMM_NUMBER_OFFSET 0 1173 #define ACPI_NFIT_CHANNEL_NUMBER_OFFSET 4 1174 #define ACPI_NFIT_MEMORY_ID_OFFSET 8 1175 #define ACPI_NFIT_SOCKET_ID_OFFSET 12 1176 #define ACPI_NFIT_NODE_ID_OFFSET 16 1177 1178 /* Macro to construct a NFIT/NVDIMM device handle */ 1179 1180 #define ACPI_NFIT_BUILD_DEVICE_HANDLE(dimm, channel, memory, socket, node) \ 1181 ((dimm) | \ 1182 ((channel) << ACPI_NFIT_CHANNEL_NUMBER_OFFSET) | \ 1183 ((memory) << ACPI_NFIT_MEMORY_ID_OFFSET) | \ 1184 ((socket) << ACPI_NFIT_SOCKET_ID_OFFSET) | \ 1185 ((node) << ACPI_NFIT_NODE_ID_OFFSET)) 1186 1187 /* Macros to extract individual fields from a NFIT/NVDIMM device handle */ 1188 1189 #define ACPI_NFIT_GET_DIMM_NUMBER(handle) \ 1190 ((handle) & ACPI_NFIT_DIMM_NUMBER_MASK) 1191 1192 #define ACPI_NFIT_GET_CHANNEL_NUMBER(handle) \ 1193 (((handle) & ACPI_NFIT_CHANNEL_NUMBER_MASK) >> ACPI_NFIT_CHANNEL_NUMBER_OFFSET) 1194 1195 #define ACPI_NFIT_GET_MEMORY_ID(handle) \ 1196 (((handle) & ACPI_NFIT_MEMORY_ID_MASK) >> ACPI_NFIT_MEMORY_ID_OFFSET) 1197 1198 #define ACPI_NFIT_GET_SOCKET_ID(handle) \ 1199 (((handle) & ACPI_NFIT_SOCKET_ID_MASK) >> ACPI_NFIT_SOCKET_ID_OFFSET) 1200 1201 #define ACPI_NFIT_GET_NODE_ID(handle) \ 1202 (((handle) & ACPI_NFIT_NODE_ID_MASK) >> ACPI_NFIT_NODE_ID_OFFSET) 1203 1204 /******************************************************************************* 1205 * 1206 * PCCT - Platform Communications Channel Table (ACPI 5.0) 1207 * Version 2 (ACPI 6.2) 1208 * 1209 ******************************************************************************/ 1210 1211 struct acpi_table_pcct { 1212 struct acpi_table_header header; /* Common ACPI table header */ 1213 u32 flags; 1214 u64 reserved; 1215 }; 1216 1217 /* Values for Flags field above */ 1218 1219 #define ACPI_PCCT_DOORBELL 1 1220 1221 /* Values for subtable type in struct acpi_subtable_header */ 1222 1223 enum acpi_pcct_type { 1224 ACPI_PCCT_TYPE_GENERIC_SUBSPACE = 0, 1225 ACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE = 1, 1226 ACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE_TYPE2 = 2, /* ACPI 6.1 */ 1227 ACPI_PCCT_TYPE_EXT_PCC_MASTER_SUBSPACE = 3, /* ACPI 6.2 */ 1228 ACPI_PCCT_TYPE_EXT_PCC_SLAVE_SUBSPACE = 4, /* ACPI 6.2 */ 1229 ACPI_PCCT_TYPE_HW_REG_COMM_SUBSPACE = 5, /* ACPI 6.4 */ 1230 ACPI_PCCT_TYPE_RESERVED = 6 /* 6 and greater are reserved */ 1231 }; 1232 1233 /* 1234 * PCCT Subtables, correspond to Type in struct acpi_subtable_header 1235 */ 1236 1237 /* 0: Generic Communications Subspace */ 1238 1239 struct acpi_pcct_subspace { 1240 struct acpi_subtable_header header; 1241 u8 reserved[6]; 1242 u64 base_address; 1243 u64 length; 1244 struct acpi_generic_address doorbell_register; 1245 u64 preserve_mask; 1246 u64 write_mask; 1247 u32 latency; 1248 u32 max_access_rate; 1249 u16 min_turnaround_time; 1250 }; 1251 1252 /* 1: HW-reduced Communications Subspace (ACPI 5.1) */ 1253 1254 struct acpi_pcct_hw_reduced { 1255 struct acpi_subtable_header header; 1256 u32 platform_interrupt; 1257 u8 flags; 1258 u8 reserved; 1259 u64 base_address; 1260 u64 length; 1261 struct acpi_generic_address doorbell_register; 1262 u64 preserve_mask; 1263 u64 write_mask; 1264 u32 latency; 1265 u32 max_access_rate; 1266 u16 min_turnaround_time; 1267 }; 1268 1269 /* 2: HW-reduced Communications Subspace Type 2 (ACPI 6.1) */ 1270 1271 struct acpi_pcct_hw_reduced_type2 { 1272 struct acpi_subtable_header header; 1273 u32 platform_interrupt; 1274 u8 flags; 1275 u8 reserved; 1276 u64 base_address; 1277 u64 length; 1278 struct acpi_generic_address doorbell_register; 1279 u64 preserve_mask; 1280 u64 write_mask; 1281 u32 latency; 1282 u32 max_access_rate; 1283 u16 min_turnaround_time; 1284 struct acpi_generic_address platform_ack_register; 1285 u64 ack_preserve_mask; 1286 u64 ack_write_mask; 1287 }; 1288 1289 /* 3: Extended PCC Master Subspace Type 3 (ACPI 6.2) */ 1290 1291 struct acpi_pcct_ext_pcc_master { 1292 struct acpi_subtable_header header; 1293 u32 platform_interrupt; 1294 u8 flags; 1295 u8 reserved1; 1296 u64 base_address; 1297 u32 length; 1298 struct acpi_generic_address doorbell_register; 1299 u64 preserve_mask; 1300 u64 write_mask; 1301 u32 latency; 1302 u32 max_access_rate; 1303 u32 min_turnaround_time; 1304 struct acpi_generic_address platform_ack_register; 1305 u64 ack_preserve_mask; 1306 u64 ack_set_mask; 1307 u64 reserved2; 1308 struct acpi_generic_address cmd_complete_register; 1309 u64 cmd_complete_mask; 1310 struct acpi_generic_address cmd_update_register; 1311 u64 cmd_update_preserve_mask; 1312 u64 cmd_update_set_mask; 1313 struct acpi_generic_address error_status_register; 1314 u64 error_status_mask; 1315 }; 1316 1317 /* 4: Extended PCC Slave Subspace Type 4 (ACPI 6.2) */ 1318 1319 struct acpi_pcct_ext_pcc_slave { 1320 struct acpi_subtable_header header; 1321 u32 platform_interrupt; 1322 u8 flags; 1323 u8 reserved1; 1324 u64 base_address; 1325 u32 length; 1326 struct acpi_generic_address doorbell_register; 1327 u64 preserve_mask; 1328 u64 write_mask; 1329 u32 latency; 1330 u32 max_access_rate; 1331 u32 min_turnaround_time; 1332 struct acpi_generic_address platform_ack_register; 1333 u64 ack_preserve_mask; 1334 u64 ack_set_mask; 1335 u64 reserved2; 1336 struct acpi_generic_address cmd_complete_register; 1337 u64 cmd_complete_mask; 1338 struct acpi_generic_address cmd_update_register; 1339 u64 cmd_update_preserve_mask; 1340 u64 cmd_update_set_mask; 1341 struct acpi_generic_address error_status_register; 1342 u64 error_status_mask; 1343 }; 1344 1345 /* 5: HW Registers based Communications Subspace */ 1346 1347 struct acpi_pcct_hw_reg { 1348 struct acpi_subtable_header header; 1349 u16 version; 1350 u64 base_address; 1351 u64 length; 1352 struct acpi_generic_address doorbell_register; 1353 u64 doorbell_preserve; 1354 u64 doorbell_write; 1355 struct acpi_generic_address cmd_complete_register; 1356 u64 cmd_complete_mask; 1357 struct acpi_generic_address error_status_register; 1358 u64 error_status_mask; 1359 u32 nominal_latency; 1360 u32 min_turnaround_time; 1361 }; 1362 1363 /* Values for doorbell flags above */ 1364 1365 #define ACPI_PCCT_INTERRUPT_POLARITY (1) 1366 #define ACPI_PCCT_INTERRUPT_MODE (1<<1) 1367 1368 /* 1369 * PCC memory structures (not part of the ACPI table) 1370 */ 1371 1372 /* Shared Memory Region */ 1373 1374 struct acpi_pcct_shared_memory { 1375 u32 signature; 1376 u16 command; 1377 u16 status; 1378 }; 1379 1380 /* Extended PCC Subspace Shared Memory Region (ACPI 6.2) */ 1381 1382 struct acpi_pcct_ext_pcc_shared_memory { 1383 u32 signature; 1384 u32 flags; 1385 u32 length; 1386 u32 command; 1387 }; 1388 1389 /******************************************************************************* 1390 * 1391 * PDTT - Platform Debug Trigger Table (ACPI 6.2) 1392 * Version 0 1393 * 1394 ******************************************************************************/ 1395 1396 struct acpi_table_pdtt { 1397 struct acpi_table_header header; /* Common ACPI table header */ 1398 u8 trigger_count; 1399 u8 reserved[3]; 1400 u32 array_offset; 1401 }; 1402 1403 /* 1404 * PDTT Communication Channel Identifier Structure. 1405 * The number of these structures is defined by trigger_count above, 1406 * starting at array_offset. 1407 */ 1408 struct acpi_pdtt_channel { 1409 u8 subchannel_id; 1410 u8 flags; 1411 }; 1412 1413 /* Flags for above */ 1414 1415 #define ACPI_PDTT_RUNTIME_TRIGGER (1) 1416 #define ACPI_PDTT_WAIT_COMPLETION (1<<1) 1417 #define ACPI_PDTT_TRIGGER_ORDER (1<<2) 1418 1419 /******************************************************************************* 1420 * 1421 * PHAT - Platform Health Assessment Table (ACPI 6.4) 1422 * Version 1 1423 * 1424 ******************************************************************************/ 1425 1426 struct acpi_table_phat { 1427 struct acpi_table_header header; /* Common ACPI table header */ 1428 }; 1429 1430 /* Common header for PHAT subtables that follow main table */ 1431 1432 struct acpi_phat_header { 1433 u16 type; 1434 u16 length; 1435 u8 revision; 1436 }; 1437 1438 /* Values for Type field above */ 1439 1440 #define ACPI_PHAT_TYPE_FW_VERSION_DATA 0 1441 #define ACPI_PHAT_TYPE_FW_HEALTH_DATA 1 1442 #define ACPI_PHAT_TYPE_RESERVED 2 /* 0x02-0xFFFF are reserved */ 1443 1444 /* 1445 * PHAT subtables, correspond to Type in struct acpi_phat_header 1446 */ 1447 1448 /* 0: Firmware Version Data Record */ 1449 1450 struct acpi_phat_version_data { 1451 struct acpi_phat_header header; 1452 u8 reserved[3]; 1453 u32 element_count; 1454 }; 1455 1456 struct acpi_phat_version_element { 1457 u8 guid[16]; 1458 u64 version_value; 1459 u32 producer_id; 1460 }; 1461 1462 /* 1: Firmware Health Data Record */ 1463 1464 struct acpi_phat_health_data { 1465 struct acpi_phat_header header; 1466 u8 reserved[2]; 1467 u8 health; 1468 u8 device_guid[16]; 1469 u32 device_specific_offset; /* Zero if no Device-specific data */ 1470 }; 1471 1472 /* Values for Health field above */ 1473 1474 #define ACPI_PHAT_ERRORS_FOUND 0 1475 #define ACPI_PHAT_NO_ERRORS 1 1476 #define ACPI_PHAT_UNKNOWN_ERRORS 2 1477 #define ACPI_PHAT_ADVISORY 3 1478 1479 /******************************************************************************* 1480 * 1481 * PMTT - Platform Memory Topology Table (ACPI 5.0) 1482 * Version 1 1483 * 1484 ******************************************************************************/ 1485 1486 struct acpi_table_pmtt { 1487 struct acpi_table_header header; /* Common ACPI table header */ 1488 u32 memory_device_count; 1489 /* 1490 * Immediately followed by: 1491 * MEMORY_DEVICE memory_device_struct[memory_device_count]; 1492 */ 1493 }; 1494 1495 /* Common header for PMTT subtables that follow main table */ 1496 1497 struct acpi_pmtt_header { 1498 u8 type; 1499 u8 reserved1; 1500 u16 length; 1501 u16 flags; 1502 u16 reserved2; 1503 u32 memory_device_count; /* Zero means no memory device structs follow */ 1504 /* 1505 * Immediately followed by: 1506 * u8 type_specific_data[] 1507 * MEMORY_DEVICE memory_device_struct[memory_device_count]; 1508 */ 1509 }; 1510 1511 /* Values for Type field above */ 1512 1513 #define ACPI_PMTT_TYPE_SOCKET 0 1514 #define ACPI_PMTT_TYPE_CONTROLLER 1 1515 #define ACPI_PMTT_TYPE_DIMM 2 1516 #define ACPI_PMTT_TYPE_RESERVED 3 /* 0x03-0xFE are reserved */ 1517 #define ACPI_PMTT_TYPE_VENDOR 0xFF 1518 1519 /* Values for Flags field above */ 1520 1521 #define ACPI_PMTT_TOP_LEVEL 0x0001 1522 #define ACPI_PMTT_PHYSICAL 0x0002 1523 #define ACPI_PMTT_MEMORY_TYPE 0x000C 1524 1525 /* 1526 * PMTT subtables, correspond to Type in struct acpi_pmtt_header 1527 */ 1528 1529 /* 0: Socket Structure */ 1530 1531 struct acpi_pmtt_socket { 1532 struct acpi_pmtt_header header; 1533 u16 socket_id; 1534 u16 reserved; 1535 }; 1536 /* 1537 * Immediately followed by: 1538 * MEMORY_DEVICE memory_device_struct[memory_device_count]; 1539 */ 1540 1541 /* 1: Memory Controller subtable */ 1542 1543 struct acpi_pmtt_controller { 1544 struct acpi_pmtt_header header; 1545 u16 controller_id; 1546 u16 reserved; 1547 }; 1548 /* 1549 * Immediately followed by: 1550 * MEMORY_DEVICE memory_device_struct[memory_device_count]; 1551 */ 1552 1553 /* 2: Physical Component Identifier (DIMM) */ 1554 1555 struct acpi_pmtt_physical_component { 1556 struct acpi_pmtt_header header; 1557 u32 bios_handle; 1558 }; 1559 1560 /* 0xFF: Vendor Specific Data */ 1561 1562 struct acpi_pmtt_vendor_specific { 1563 struct acpi_pmtt_header header; 1564 u8 type_uuid[16]; 1565 u8 specific[]; 1566 /* 1567 * Immediately followed by: 1568 * u8 vendor_specific_data[]; 1569 * MEMORY_DEVICE memory_device_struct[memory_device_count]; 1570 */ 1571 }; 1572 1573 /******************************************************************************* 1574 * 1575 * PPTT - Processor Properties Topology Table (ACPI 6.2) 1576 * Version 1 1577 * 1578 ******************************************************************************/ 1579 1580 struct acpi_table_pptt { 1581 struct acpi_table_header header; /* Common ACPI table header */ 1582 }; 1583 1584 /* Values for Type field above */ 1585 1586 enum acpi_pptt_type { 1587 ACPI_PPTT_TYPE_PROCESSOR = 0, 1588 ACPI_PPTT_TYPE_CACHE = 1, 1589 ACPI_PPTT_TYPE_ID = 2, 1590 ACPI_PPTT_TYPE_RESERVED = 3 1591 }; 1592 1593 /* 0: Processor Hierarchy Node Structure */ 1594 1595 struct acpi_pptt_processor { 1596 struct acpi_subtable_header header; 1597 u16 reserved; 1598 u32 flags; 1599 u32 parent; 1600 u32 acpi_processor_id; 1601 u32 number_of_priv_resources; 1602 }; 1603 1604 /* Flags */ 1605 1606 #define ACPI_PPTT_PHYSICAL_PACKAGE (1) 1607 #define ACPI_PPTT_ACPI_PROCESSOR_ID_VALID (1<<1) 1608 #define ACPI_PPTT_ACPI_PROCESSOR_IS_THREAD (1<<2) /* ACPI 6.3 */ 1609 #define ACPI_PPTT_ACPI_LEAF_NODE (1<<3) /* ACPI 6.3 */ 1610 #define ACPI_PPTT_ACPI_IDENTICAL (1<<4) /* ACPI 6.3 */ 1611 1612 /* 1: Cache Type Structure */ 1613 1614 struct acpi_pptt_cache { 1615 struct acpi_subtable_header header; 1616 u16 reserved; 1617 u32 flags; 1618 u32 next_level_of_cache; 1619 u32 size; 1620 u32 number_of_sets; 1621 u8 associativity; 1622 u8 attributes; 1623 u16 line_size; 1624 }; 1625 1626 /* 1: Cache Type Structure for PPTT version 3 */ 1627 1628 struct acpi_pptt_cache_v1 { 1629 u32 cache_id; 1630 }; 1631 1632 /* Flags */ 1633 1634 #define ACPI_PPTT_SIZE_PROPERTY_VALID (1) /* Physical property valid */ 1635 #define ACPI_PPTT_NUMBER_OF_SETS_VALID (1<<1) /* Number of sets valid */ 1636 #define ACPI_PPTT_ASSOCIATIVITY_VALID (1<<2) /* Associativity valid */ 1637 #define ACPI_PPTT_ALLOCATION_TYPE_VALID (1<<3) /* Allocation type valid */ 1638 #define ACPI_PPTT_CACHE_TYPE_VALID (1<<4) /* Cache type valid */ 1639 #define ACPI_PPTT_WRITE_POLICY_VALID (1<<5) /* Write policy valid */ 1640 #define ACPI_PPTT_LINE_SIZE_VALID (1<<6) /* Line size valid */ 1641 #define ACPI_PPTT_CACHE_ID_VALID (1<<7) /* Cache ID valid */ 1642 1643 /* Masks for Attributes */ 1644 1645 #define ACPI_PPTT_MASK_ALLOCATION_TYPE (0x03) /* Allocation type */ 1646 #define ACPI_PPTT_MASK_CACHE_TYPE (0x0C) /* Cache type */ 1647 #define ACPI_PPTT_MASK_WRITE_POLICY (0x10) /* Write policy */ 1648 1649 /* Attributes describing cache */ 1650 #define ACPI_PPTT_CACHE_READ_ALLOCATE (0x0) /* Cache line is allocated on read */ 1651 #define ACPI_PPTT_CACHE_WRITE_ALLOCATE (0x01) /* Cache line is allocated on write */ 1652 #define ACPI_PPTT_CACHE_RW_ALLOCATE (0x02) /* Cache line is allocated on read and write */ 1653 #define ACPI_PPTT_CACHE_RW_ALLOCATE_ALT (0x03) /* Alternate representation of above */ 1654 1655 #define ACPI_PPTT_CACHE_TYPE_DATA (0x0) /* Data cache */ 1656 #define ACPI_PPTT_CACHE_TYPE_INSTR (1<<2) /* Instruction cache */ 1657 #define ACPI_PPTT_CACHE_TYPE_UNIFIED (2<<2) /* Unified I & D cache */ 1658 #define ACPI_PPTT_CACHE_TYPE_UNIFIED_ALT (3<<2) /* Alternate representation of above */ 1659 1660 #define ACPI_PPTT_CACHE_POLICY_WB (0x0) /* Cache is write back */ 1661 #define ACPI_PPTT_CACHE_POLICY_WT (1<<4) /* Cache is write through */ 1662 1663 /* 2: ID Structure */ 1664 1665 struct acpi_pptt_id { 1666 struct acpi_subtable_header header; 1667 u16 reserved; 1668 u32 vendor_id; 1669 u64 level1_id; 1670 u64 level2_id; 1671 u16 major_rev; 1672 u16 minor_rev; 1673 u16 spin_rev; 1674 }; 1675 1676 /******************************************************************************* 1677 * 1678 * RASF - RAS Feature Table (ACPI 5.0) 1679 * Version 1 1680 * 1681 ******************************************************************************/ 1682 1683 struct acpi_table_rasf { 1684 struct acpi_table_header header; /* Common ACPI table header */ 1685 u8 channel_id[12]; 1686 }; 1687 1688 /* RASF Platform Communication Channel Shared Memory Region */ 1689 1690 struct acpi_rasf_shared_memory { 1691 u32 signature; 1692 u16 command; 1693 u16 status; 1694 u16 version; 1695 u8 capabilities[16]; 1696 u8 set_capabilities[16]; 1697 u16 num_parameter_blocks; 1698 u32 set_capabilities_status; 1699 }; 1700 1701 /* RASF Parameter Block Structure Header */ 1702 1703 struct acpi_rasf_parameter_block { 1704 u16 type; 1705 u16 version; 1706 u16 length; 1707 }; 1708 1709 /* RASF Parameter Block Structure for PATROL_SCRUB */ 1710 1711 struct acpi_rasf_patrol_scrub_parameter { 1712 struct acpi_rasf_parameter_block header; 1713 u16 patrol_scrub_command; 1714 u64 requested_address_range[2]; 1715 u64 actual_address_range[2]; 1716 u16 flags; 1717 u8 requested_speed; 1718 }; 1719 1720 /* Masks for Flags and Speed fields above */ 1721 1722 #define ACPI_RASF_SCRUBBER_RUNNING 1 1723 #define ACPI_RASF_SPEED (7<<1) 1724 #define ACPI_RASF_SPEED_SLOW (0<<1) 1725 #define ACPI_RASF_SPEED_MEDIUM (4<<1) 1726 #define ACPI_RASF_SPEED_FAST (7<<1) 1727 1728 /* Channel Commands */ 1729 1730 enum acpi_rasf_commands { 1731 ACPI_RASF_EXECUTE_RASF_COMMAND = 1 1732 }; 1733 1734 /* Platform RAS Capabilities */ 1735 1736 enum acpi_rasf_capabiliities { 1737 ACPI_HW_PATROL_SCRUB_SUPPORTED = 0, 1738 ACPI_SW_PATROL_SCRUB_EXPOSED = 1 1739 }; 1740 1741 /* Patrol Scrub Commands */ 1742 1743 enum acpi_rasf_patrol_scrub_commands { 1744 ACPI_RASF_GET_PATROL_PARAMETERS = 1, 1745 ACPI_RASF_START_PATROL_SCRUBBER = 2, 1746 ACPI_RASF_STOP_PATROL_SCRUBBER = 3 1747 }; 1748 1749 /* Channel Command flags */ 1750 1751 #define ACPI_RASF_GENERATE_SCI (1<<15) 1752 1753 /* Status values */ 1754 1755 enum acpi_rasf_status { 1756 ACPI_RASF_SUCCESS = 0, 1757 ACPI_RASF_NOT_VALID = 1, 1758 ACPI_RASF_NOT_SUPPORTED = 2, 1759 ACPI_RASF_BUSY = 3, 1760 ACPI_RASF_FAILED = 4, 1761 ACPI_RASF_ABORTED = 5, 1762 ACPI_RASF_INVALID_DATA = 6 1763 }; 1764 1765 /* Status flags */ 1766 1767 #define ACPI_RASF_COMMAND_COMPLETE (1) 1768 #define ACPI_RASF_SCI_DOORBELL (1<<1) 1769 #define ACPI_RASF_ERROR (1<<2) 1770 #define ACPI_RASF_STATUS (0x1F<<3) 1771 1772 /******************************************************************************* 1773 * 1774 * SBST - Smart Battery Specification Table 1775 * Version 1 1776 * 1777 ******************************************************************************/ 1778 1779 struct acpi_table_sbst { 1780 struct acpi_table_header header; /* Common ACPI table header */ 1781 u32 warning_level; 1782 u32 low_level; 1783 u32 critical_level; 1784 }; 1785 1786 /******************************************************************************* 1787 * 1788 * SDEI - Software Delegated Exception Interface Descriptor Table 1789 * 1790 * Conforms to "Software Delegated Exception Interface (SDEI)" ARM DEN0054A, 1791 * May 8th, 2017. Copyright 2017 ARM Ltd. 1792 * 1793 ******************************************************************************/ 1794 1795 struct acpi_table_sdei { 1796 struct acpi_table_header header; /* Common ACPI table header */ 1797 }; 1798 1799 /******************************************************************************* 1800 * 1801 * SDEV - Secure Devices Table (ACPI 6.2) 1802 * Version 1 1803 * 1804 ******************************************************************************/ 1805 1806 struct acpi_table_sdev { 1807 struct acpi_table_header header; /* Common ACPI table header */ 1808 }; 1809 1810 struct acpi_sdev_header { 1811 u8 type; 1812 u8 flags; 1813 u16 length; 1814 }; 1815 1816 /* Values for subtable type above */ 1817 1818 enum acpi_sdev_type { 1819 ACPI_SDEV_TYPE_NAMESPACE_DEVICE = 0, 1820 ACPI_SDEV_TYPE_PCIE_ENDPOINT_DEVICE = 1, 1821 ACPI_SDEV_TYPE_RESERVED = 2 /* 2 and greater are reserved */ 1822 }; 1823 1824 /* Values for flags above */ 1825 1826 #define ACPI_SDEV_HANDOFF_TO_UNSECURE_OS (1) 1827 #define ACPI_SDEV_SECURE_COMPONENTS_PRESENT (1<<1) 1828 1829 /* 1830 * SDEV subtables 1831 */ 1832 1833 /* 0: Namespace Device Based Secure Device Structure */ 1834 1835 struct acpi_sdev_namespace { 1836 struct acpi_sdev_header header; 1837 u16 device_id_offset; 1838 u16 device_id_length; 1839 u16 vendor_data_offset; 1840 u16 vendor_data_length; 1841 }; 1842 1843 struct acpi_sdev_secure_component { 1844 u16 secure_component_offset; 1845 u16 secure_component_length; 1846 }; 1847 1848 /* 1849 * SDEV sub-subtables ("Components") for above 1850 */ 1851 struct acpi_sdev_component { 1852 struct acpi_sdev_header header; 1853 }; 1854 1855 /* Values for sub-subtable type above */ 1856 1857 enum acpi_sac_type { 1858 ACPI_SDEV_TYPE_ID_COMPONENT = 0, 1859 ACPI_SDEV_TYPE_MEM_COMPONENT = 1 1860 }; 1861 1862 struct acpi_sdev_id_component { 1863 struct acpi_sdev_header header; 1864 u16 hardware_id_offset; 1865 u16 hardware_id_length; 1866 u16 subsystem_id_offset; 1867 u16 subsystem_id_length; 1868 u16 hardware_revision; 1869 u8 hardware_rev_present; 1870 u8 class_code_present; 1871 u8 pci_base_class; 1872 u8 pci_sub_class; 1873 u8 pci_programming_xface; 1874 }; 1875 1876 struct acpi_sdev_mem_component { 1877 struct acpi_sdev_header header; 1878 u32 reserved; 1879 u64 memory_base_address; 1880 u64 memory_length; 1881 }; 1882 1883 /* 1: PCIe Endpoint Device Based Device Structure */ 1884 1885 struct acpi_sdev_pcie { 1886 struct acpi_sdev_header header; 1887 u16 segment; 1888 u16 start_bus; 1889 u16 path_offset; 1890 u16 path_length; 1891 u16 vendor_data_offset; 1892 u16 vendor_data_length; 1893 }; 1894 1895 /* 1a: PCIe Endpoint path entry */ 1896 1897 struct acpi_sdev_pcie_path { 1898 u8 device; 1899 u8 function; 1900 }; 1901 1902 /* Reset to default packing */ 1903 1904 #pragma pack() 1905 1906 #endif /* __ACTBL2_H__ */ 1907