xref: /openbmc/linux/include/acpi/actbl1.h (revision 87c2ce3b)
1 /******************************************************************************
2  *
3  * Name: actbl1.h - ACPI 1.0 tables
4  *
5  *****************************************************************************/
6 
7 /*
8  * Copyright (C) 2000 - 2005, R. Byron Moore
9  * All rights reserved.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions, and the following disclaimer,
16  *    without modification.
17  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
18  *    substantially similar to the "NO WARRANTY" disclaimer below
19  *    ("Disclaimer") and any redistribution must be conditioned upon
20  *    including a substantially similar Disclaimer requirement for further
21  *    binary redistribution.
22  * 3. Neither the names of the above-listed copyright holders nor the names
23  *    of any contributors may be used to endorse or promote products derived
24  *    from this software without specific prior written permission.
25  *
26  * Alternatively, this software may be distributed under the terms of the
27  * GNU General Public License ("GPL") version 2 as published by the Free
28  * Software Foundation.
29  *
30  * NO WARRANTY
31  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
34  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
39  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
40  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
41  * POSSIBILITY OF SUCH DAMAGES.
42  */
43 
44 #ifndef __ACTBL1_H__
45 #define __ACTBL1_H__
46 
47 #pragma pack(1)
48 
49 /*
50  * ACPI 1.0 Root System Description Table (RSDT)
51  */
52 struct rsdt_descriptor_rev1 {
53 	ACPI_TABLE_HEADER_DEF	/* ACPI common table header */
54 	u32 table_offset_entry[1];	/* Array of pointers to ACPI tables */
55 };
56 
57 /*
58  * ACPI 1.0 Firmware ACPI Control Structure (FACS)
59  */
60 struct facs_descriptor_rev1 {
61 	char signature[4];	/* ASCII table signature */
62 	u32 length;		/* Length of structure in bytes */
63 	u32 hardware_signature;	/* Hardware configuration signature */
64 	u32 firmware_waking_vector;	/* ACPI OS waking vector */
65 	u32 global_lock;	/* Global Lock */
66 
67 	/* Flags (32 bits) */
68 
69 	u8 S4bios_f:1;		/* 00:    S4BIOS support is present */
70 	 u8:7;			/* 01-07: Reserved, must be zero */
71 	u8 reserved1[3];	/* 08-31: Reserved, must be zero */
72 
73 	u8 reserved2[40];	/* Reserved, must be zero */
74 };
75 
76 /*
77  * ACPI 1.0 Fixed ACPI Description Table (FADT)
78  */
79 struct fadt_descriptor_rev1 {
80 	ACPI_TABLE_HEADER_DEF	/* ACPI common table header */
81 	u32 firmware_ctrl;	/* Physical address of FACS */
82 	u32 dsdt;		/* Physical address of DSDT */
83 	u8 model;		/* System Interrupt Model */
84 	u8 reserved1;		/* Reserved, must be zero */
85 	u16 sci_int;		/* System vector of SCI interrupt */
86 	u32 smi_cmd;		/* Port address of SMI command port */
87 	u8 acpi_enable;		/* Value to write to smi_cmd to enable ACPI */
88 	u8 acpi_disable;	/* Value to write to smi_cmd to disable ACPI */
89 	u8 S4bios_req;		/* Value to write to SMI CMD to enter S4BIOS state */
90 	u8 reserved2;		/* Reserved, must be zero */
91 	u32 pm1a_evt_blk;	/* Port address of Power Mgt 1a acpi_event Reg Blk */
92 	u32 pm1b_evt_blk;	/* Port address of Power Mgt 1b acpi_event Reg Blk */
93 	u32 pm1a_cnt_blk;	/* Port address of Power Mgt 1a Control Reg Blk */
94 	u32 pm1b_cnt_blk;	/* Port address of Power Mgt 1b Control Reg Blk */
95 	u32 pm2_cnt_blk;	/* Port address of Power Mgt 2 Control Reg Blk */
96 	u32 pm_tmr_blk;		/* Port address of Power Mgt Timer Ctrl Reg Blk */
97 	u32 gpe0_blk;		/* Port addr of General Purpose acpi_event 0 Reg Blk */
98 	u32 gpe1_blk;		/* Port addr of General Purpose acpi_event 1 Reg Blk */
99 	u8 pm1_evt_len;		/* Byte length of ports at pm1_x_evt_blk */
100 	u8 pm1_cnt_len;		/* Byte length of ports at pm1_x_cnt_blk */
101 	u8 pm2_cnt_len;		/* Byte Length of ports at pm2_cnt_blk */
102 	u8 pm_tm_len;		/* Byte Length of ports at pm_tm_blk */
103 	u8 gpe0_blk_len;	/* Byte Length of ports at gpe0_blk */
104 	u8 gpe1_blk_len;	/* Byte Length of ports at gpe1_blk */
105 	u8 gpe1_base;		/* Offset in gpe model where gpe1 events start */
106 	u8 reserved3;		/* Reserved, must be zero */
107 	u16 plvl2_lat;		/* Worst case HW latency to enter/exit C2 state */
108 	u16 plvl3_lat;		/* Worst case HW latency to enter/exit C3 state */
109 	u16 flush_size;		/* Size of area read to flush caches */
110 	u16 flush_stride;	/* Stride used in flushing caches */
111 	u8 duty_offset;		/* Bit location of duty cycle field in p_cnt reg */
112 	u8 duty_width;		/* Bit width of duty cycle field in p_cnt reg */
113 	u8 day_alrm;		/* Index to day-of-month alarm in RTC CMOS RAM */
114 	u8 mon_alrm;		/* Index to month-of-year alarm in RTC CMOS RAM */
115 	u8 century;		/* Index to century in RTC CMOS RAM */
116 	u8 reserved4[3];	/* Reserved, must be zero */
117 
118 	/* Flags (32 bits) */
119 
120 	u8 wb_invd:1;		/* 00:    The wbinvd instruction works properly */
121 	u8 wb_invd_flush:1;	/* 01:    The wbinvd flushes but does not invalidate */
122 	u8 proc_c1:1;		/* 02:    All processors support C1 state */
123 	u8 plvl2_up:1;		/* 03:    C2 state works on MP system */
124 	u8 pwr_button:1;	/* 04:    Power button is handled as a generic feature */
125 	u8 sleep_button:1;	/* 05:    Sleep button is handled as a generic feature, or not present */
126 	u8 fixed_rTC:1;		/* 06:    RTC wakeup stat not in fixed register space */
127 	u8 rtcs4:1;		/* 07:    RTC wakeup stat not possible from S4 */
128 	u8 tmr_val_ext:1;	/* 08:    tmr_val width is 32 bits (0 = 24 bits) */
129 	 u8:7;			/* 09-15: Reserved, must be zero */
130 	u8 reserved5[2];	/* 16-31: Reserved, must be zero */
131 };
132 
133 #pragma pack()
134 
135 #endif				/* __ACTBL1_H__ */
136