1 /*
2  *	w83627hf/thf WDT driver
3  *
4  *	(c) Copyright 2013 Guenter Roeck
5  *		converted to watchdog infrastructure
6  *
7  *	(c) Copyright 2007 Vlad Drukker <vlad@storewiz.com>
8  *		added support for W83627THF.
9  *
10  *	(c) Copyright 2003,2007 Pádraig Brady <P@draigBrady.com>
11  *
12  *	Based on advantechwdt.c which is based on wdt.c.
13  *	Original copyright messages:
14  *
15  *	(c) Copyright 2000-2001 Marek Michalkiewicz <marekm@linux.org.pl>
16  *
17  *	(c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>,
18  *						All Rights Reserved.
19  *
20  *	This program is free software; you can redistribute it and/or
21  *	modify it under the terms of the GNU General Public License
22  *	as published by the Free Software Foundation; either version
23  *	2 of the License, or (at your option) any later version.
24  *
25  *	Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
26  *	warranty for any of this software. This material is provided
27  *	"AS-IS" and at no charge.
28  *
29  *	(c) Copyright 1995    Alan Cox <alan@lxorguk.ukuu.org.uk>
30  */
31 
32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33 
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/types.h>
37 #include <linux/watchdog.h>
38 #include <linux/ioport.h>
39 #include <linux/notifier.h>
40 #include <linux/reboot.h>
41 #include <linux/init.h>
42 #include <linux/io.h>
43 
44 #define WATCHDOG_NAME "w83627hf/thf/hg/dhg WDT"
45 #define WATCHDOG_TIMEOUT 60		/* 60 sec default timeout */
46 
47 static int wdt_io;
48 static int cr_wdt_timeout;	/* WDT timeout register */
49 static int cr_wdt_control;	/* WDT control register */
50 
51 enum chips { w83627hf, w83627s, w83697hf, w83697ug, w83637hf, w83627thf,
52 	     w83687thf, w83627ehf, w83627dhg, w83627uhg, w83667hg, w83627dhg_p,
53 	     w83667hg_b, nct6775, nct6776, nct6779 };
54 
55 static int timeout;			/* in seconds */
56 module_param(timeout, int, 0);
57 MODULE_PARM_DESC(timeout,
58 		"Watchdog timeout in seconds. 1 <= timeout <= 255, default="
59 				__MODULE_STRING(WATCHDOG_TIMEOUT) ".");
60 
61 static bool nowayout = WATCHDOG_NOWAYOUT;
62 module_param(nowayout, bool, 0);
63 MODULE_PARM_DESC(nowayout,
64 		"Watchdog cannot be stopped once started (default="
65 				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
66 
67 /*
68  *	Kernel methods.
69  */
70 
71 #define WDT_EFER (wdt_io+0)   /* Extended Function Enable Registers */
72 #define WDT_EFIR (wdt_io+0)   /* Extended Function Index Register
73 							(same as EFER) */
74 #define WDT_EFDR (WDT_EFIR+1) /* Extended Function Data Register */
75 
76 #define W83627HF_LD_WDT		0x08
77 
78 #define W83627HF_ID		0x52
79 #define W83627S_ID		0x59
80 #define W83697HF_ID		0x60
81 #define W83697UG_ID		0x68
82 #define W83637HF_ID		0x70
83 #define W83627THF_ID		0x82
84 #define W83687THF_ID		0x85
85 #define W83627EHF_ID		0x88
86 #define W83627DHG_ID		0xa0
87 #define W83627UHG_ID		0xa2
88 #define W83667HG_ID		0xa5
89 #define W83627DHG_P_ID		0xb0
90 #define W83667HG_B_ID		0xb3
91 #define NCT6775_ID		0xb4
92 #define NCT6776_ID		0xc3
93 #define NCT6779_ID		0xc5
94 
95 #define W83627HF_WDT_TIMEOUT	0xf6
96 #define W83697HF_WDT_TIMEOUT	0xf4
97 
98 #define W83627HF_WDT_CONTROL	0xf5
99 #define W83697HF_WDT_CONTROL	0xf3
100 
101 static void superio_outb(int reg, int val)
102 {
103 	outb(reg, WDT_EFER);
104 	outb(val, WDT_EFDR);
105 }
106 
107 static inline int superio_inb(int reg)
108 {
109 	outb(reg, WDT_EFER);
110 	return inb(WDT_EFDR);
111 }
112 
113 static int superio_enter(void)
114 {
115 	if (!request_muxed_region(wdt_io, 2, WATCHDOG_NAME))
116 		return -EBUSY;
117 
118 	outb_p(0x87, WDT_EFER); /* Enter extended function mode */
119 	outb_p(0x87, WDT_EFER); /* Again according to manual */
120 
121 	return 0;
122 }
123 
124 static void superio_select(int ld)
125 {
126 	superio_outb(0x07, ld);
127 }
128 
129 static void superio_exit(void)
130 {
131 	outb_p(0xAA, WDT_EFER); /* Leave extended function mode */
132 	release_region(wdt_io, 2);
133 }
134 
135 static int w83627hf_init(struct watchdog_device *wdog, enum chips chip)
136 {
137 	int ret;
138 	unsigned char t;
139 
140 	ret = superio_enter();
141 	if (ret)
142 		return ret;
143 
144 	superio_select(W83627HF_LD_WDT);
145 
146 	/* set CR30 bit 0 to activate GPIO2 */
147 	t = superio_inb(0x30);
148 	if (!(t & 0x01))
149 		superio_outb(0x30, t | 0x01);
150 
151 	switch (chip) {
152 	case w83627hf:
153 	case w83627s:
154 		t = superio_inb(0x2B) & ~0x10;
155 		superio_outb(0x2B, t); /* set GPIO24 to WDT0 */
156 		break;
157 	case w83697hf:
158 		/* Set pin 119 to WDTO# mode (= CR29, WDT0) */
159 		t = superio_inb(0x29) & ~0x60;
160 		t |= 0x20;
161 		superio_outb(0x29, t);
162 		break;
163 	case w83697ug:
164 		/* Set pin 118 to WDTO# mode */
165 		t = superio_inb(0x2b) & ~0x04;
166 		superio_outb(0x2b, t);
167 		break;
168 	case w83627thf:
169 		t = (superio_inb(0x2B) & ~0x08) | 0x04;
170 		superio_outb(0x2B, t); /* set GPIO3 to WDT0 */
171 		break;
172 	case w83627dhg:
173 	case w83627dhg_p:
174 		t = superio_inb(0x2D) & ~0x01; /* PIN77 -> WDT0# */
175 		superio_outb(0x2D, t); /* set GPIO5 to WDT0 */
176 		t = superio_inb(cr_wdt_control);
177 		t |= 0x02;	/* enable the WDTO# output low pulse
178 				 * to the KBRST# pin */
179 		superio_outb(cr_wdt_control, t);
180 		break;
181 	case w83637hf:
182 		break;
183 	case w83687thf:
184 		t = superio_inb(0x2C) & ~0x80; /* PIN47 -> WDT0# */
185 		superio_outb(0x2C, t);
186 		break;
187 	case w83627ehf:
188 	case w83627uhg:
189 	case w83667hg:
190 	case w83667hg_b:
191 	case nct6775:
192 	case nct6776:
193 	case nct6779:
194 		/*
195 		 * These chips have a fixed WDTO# output pin (W83627UHG),
196 		 * or support more than one WDTO# output pin.
197 		 * Don't touch its configuration, and hope the BIOS
198 		 * does the right thing.
199 		 */
200 		t = superio_inb(cr_wdt_control);
201 		t |= 0x02;	/* enable the WDTO# output low pulse
202 				 * to the KBRST# pin */
203 		superio_outb(cr_wdt_control, t);
204 		break;
205 	default:
206 		break;
207 	}
208 
209 	t = superio_inb(cr_wdt_timeout);
210 	if (t != 0) {
211 		pr_info("Watchdog already running. Resetting timeout to %d sec\n",
212 			wdog->timeout);
213 		superio_outb(cr_wdt_timeout, wdog->timeout);
214 	}
215 
216 	/* set second mode & disable keyboard turning off watchdog */
217 	t = superio_inb(cr_wdt_control) & ~0x0C;
218 	superio_outb(cr_wdt_control, t);
219 
220 	/* reset trigger, disable keyboard & mouse turning off watchdog */
221 	t = superio_inb(0xF7) & ~0xD0;
222 	superio_outb(0xF7, t);
223 
224 	superio_exit();
225 
226 	return 0;
227 }
228 
229 static int wdt_set_time(unsigned int timeout)
230 {
231 	int ret;
232 
233 	ret = superio_enter();
234 	if (ret)
235 		return ret;
236 
237 	superio_select(W83627HF_LD_WDT);
238 	superio_outb(cr_wdt_timeout, timeout);
239 	superio_exit();
240 
241 	return 0;
242 }
243 
244 static int wdt_start(struct watchdog_device *wdog)
245 {
246 	return wdt_set_time(wdog->timeout);
247 }
248 
249 static int wdt_stop(struct watchdog_device *wdog)
250 {
251 	return wdt_set_time(0);
252 }
253 
254 static int wdt_set_timeout(struct watchdog_device *wdog, unsigned int timeout)
255 {
256 	wdog->timeout = timeout;
257 
258 	return 0;
259 }
260 
261 static unsigned int wdt_get_time(struct watchdog_device *wdog)
262 {
263 	unsigned int timeleft;
264 	int ret;
265 
266 	ret = superio_enter();
267 	if (ret)
268 		return 0;
269 
270 	superio_select(W83627HF_LD_WDT);
271 	timeleft = superio_inb(cr_wdt_timeout);
272 	superio_exit();
273 
274 	return timeleft;
275 }
276 
277 /*
278  *	Notifier for system down
279  */
280 static int wdt_notify_sys(struct notifier_block *this, unsigned long code,
281 	void *unused)
282 {
283 	if (code == SYS_DOWN || code == SYS_HALT)
284 		wdt_set_time(0);	/* Turn the WDT off */
285 
286 	return NOTIFY_DONE;
287 }
288 
289 /*
290  *	Kernel Interfaces
291  */
292 
293 static struct watchdog_info wdt_info = {
294 	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
295 	.identity = "W83627HF Watchdog",
296 };
297 
298 static struct watchdog_ops wdt_ops = {
299 	.owner = THIS_MODULE,
300 	.start = wdt_start,
301 	.stop = wdt_stop,
302 	.set_timeout = wdt_set_timeout,
303 	.get_timeleft = wdt_get_time,
304 };
305 
306 static struct watchdog_device wdt_dev = {
307 	.info = &wdt_info,
308 	.ops = &wdt_ops,
309 	.timeout = WATCHDOG_TIMEOUT,
310 	.min_timeout = 1,
311 	.max_timeout = 255,
312 };
313 
314 /*
315  *	The WDT needs to learn about soft shutdowns in order to
316  *	turn the timebomb registers off.
317  */
318 
319 static struct notifier_block wdt_notifier = {
320 	.notifier_call = wdt_notify_sys,
321 };
322 
323 static int wdt_find(int addr)
324 {
325 	u8 val;
326 	int ret;
327 
328 	cr_wdt_timeout = W83627HF_WDT_TIMEOUT;
329 	cr_wdt_control = W83627HF_WDT_CONTROL;
330 
331 	ret = superio_enter();
332 	if (ret)
333 		return ret;
334 	superio_select(W83627HF_LD_WDT);
335 	val = superio_inb(0x20);
336 	switch (val) {
337 	case W83627HF_ID:
338 		ret = w83627hf;
339 		break;
340 	case W83627S_ID:
341 		ret = w83627s;
342 		break;
343 	case W83697HF_ID:
344 		ret = w83697hf;
345 		cr_wdt_timeout = W83697HF_WDT_TIMEOUT;
346 		cr_wdt_control = W83697HF_WDT_CONTROL;
347 		break;
348 	case W83697UG_ID:
349 		ret = w83697ug;
350 		cr_wdt_timeout = W83697HF_WDT_TIMEOUT;
351 		cr_wdt_control = W83697HF_WDT_CONTROL;
352 		break;
353 	case W83637HF_ID:
354 		ret = w83637hf;
355 		break;
356 	case W83627THF_ID:
357 		ret = w83627thf;
358 		break;
359 	case W83687THF_ID:
360 		ret = w83687thf;
361 		break;
362 	case W83627EHF_ID:
363 		ret = w83627ehf;
364 		break;
365 	case W83627DHG_ID:
366 		ret = w83627dhg;
367 		break;
368 	case W83627DHG_P_ID:
369 		ret = w83627dhg_p;
370 		break;
371 	case W83627UHG_ID:
372 		ret = w83627uhg;
373 		break;
374 	case W83667HG_ID:
375 		ret = w83667hg;
376 		break;
377 	case W83667HG_B_ID:
378 		ret = w83667hg_b;
379 		break;
380 	case NCT6775_ID:
381 		ret = nct6775;
382 		break;
383 	case NCT6776_ID:
384 		ret = nct6776;
385 		break;
386 	case NCT6779_ID:
387 		ret = nct6779;
388 		break;
389 	case 0xff:
390 		ret = -ENODEV;
391 		break;
392 	default:
393 		ret = -ENODEV;
394 		pr_err("Unsupported chip ID: 0x%02x\n", val);
395 		break;
396 	}
397 	superio_exit();
398 	return ret;
399 }
400 
401 static int __init wdt_init(void)
402 {
403 	int ret;
404 	int chip;
405 	const char * const chip_name[] = {
406 		"W83627HF",
407 		"W83627S",
408 		"W83697HF",
409 		"W83697UG",
410 		"W83637HF",
411 		"W83627THF",
412 		"W83687THF",
413 		"W83627EHF",
414 		"W83627DHG",
415 		"W83627UHG",
416 		"W83667HG",
417 		"W83667DHG-P",
418 		"W83667HG-B",
419 		"NCT6775",
420 		"NCT6776",
421 		"NCT6779",
422 	};
423 
424 	wdt_io = 0x2e;
425 	chip = wdt_find(0x2e);
426 	if (chip < 0) {
427 		wdt_io = 0x4e;
428 		chip = wdt_find(0x4e);
429 		if (chip < 0)
430 			return chip;
431 	}
432 
433 	pr_info("WDT driver for %s Super I/O chip initialising\n",
434 		chip_name[chip]);
435 
436 	watchdog_init_timeout(&wdt_dev, timeout, NULL);
437 	watchdog_set_nowayout(&wdt_dev, nowayout);
438 
439 	ret = w83627hf_init(&wdt_dev, chip);
440 	if (ret) {
441 		pr_err("failed to initialize watchdog (err=%d)\n", ret);
442 		return ret;
443 	}
444 
445 	ret = register_reboot_notifier(&wdt_notifier);
446 	if (ret != 0) {
447 		pr_err("cannot register reboot notifier (err=%d)\n", ret);
448 		return ret;
449 	}
450 
451 	ret = watchdog_register_device(&wdt_dev);
452 	if (ret)
453 		goto unreg_reboot;
454 
455 	pr_info("initialized. timeout=%d sec (nowayout=%d)\n",
456 		wdt_dev.timeout, nowayout);
457 
458 	return ret;
459 
460 unreg_reboot:
461 	unregister_reboot_notifier(&wdt_notifier);
462 	return ret;
463 }
464 
465 static void __exit wdt_exit(void)
466 {
467 	watchdog_unregister_device(&wdt_dev);
468 	unregister_reboot_notifier(&wdt_notifier);
469 }
470 
471 module_init(wdt_init);
472 module_exit(wdt_exit);
473 
474 MODULE_LICENSE("GPL");
475 MODULE_AUTHOR("Pádraig  Brady <P@draigBrady.com>");
476 MODULE_DESCRIPTION("w83627hf/thf WDT driver");
477