1 /* 2 * SBSA(Server Base System Architecture) Generic Watchdog driver 3 * 4 * Copyright (c) 2015, Linaro Ltd. 5 * Author: Fu Wei <fu.wei@linaro.org> 6 * Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> 7 * Al Stone <al.stone@linaro.org> 8 * Timur Tabi <timur@codeaurora.org> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License 2 as published 12 * by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * ARM SBSA Generic Watchdog has two stage timeouts: 20 * the first signal (WS0) is for alerting the system by interrupt, 21 * the second one (WS1) is a real hardware reset. 22 * More details about the hardware specification of this device: 23 * ARM DEN0029B - Server Base System Architecture (SBSA) 24 * 25 * This driver can operate ARM SBSA Generic Watchdog as a single stage watchdog 26 * or a two stages watchdog, it's set up by the module parameter "action". 27 * In the single stage mode, when the timeout is reached, your system 28 * will be reset by WS1. The first signal (WS0) is ignored. 29 * In the two stages mode, when the timeout is reached, the first signal (WS0) 30 * will trigger panic. If the system is getting into trouble and cannot be reset 31 * by panic or restart properly by the kdump kernel(if supported), then the 32 * second stage (as long as the first stage) will be reached, system will be 33 * reset by WS1. This function can help administrator to backup the system 34 * context info by panic console output or kdump. 35 * 36 * SBSA GWDT: 37 * if action is 1 (the two stages mode): 38 * |--------WOR-------WS0--------WOR-------WS1 39 * |----timeout-----(panic)----timeout-----reset 40 * 41 * if action is 0 (the single stage mode): 42 * |------WOR-----WS0(ignored)-----WOR------WS1 43 * |--------------timeout-------------------reset 44 * 45 * Note: Since this watchdog timer has two stages, and each stage is determined 46 * by WOR, in the single stage mode, the timeout is (WOR * 2); in the two 47 * stages mode, the timeout is WOR. The maximum timeout in the two stages mode 48 * is half of that in the single stage mode. 49 * 50 */ 51 52 #include <linux/io.h> 53 #include <linux/interrupt.h> 54 #include <linux/module.h> 55 #include <linux/moduleparam.h> 56 #include <linux/of.h> 57 #include <linux/of_device.h> 58 #include <linux/platform_device.h> 59 #include <linux/uaccess.h> 60 #include <linux/watchdog.h> 61 #include <asm/arch_timer.h> 62 63 #define DRV_NAME "sbsa-gwdt" 64 #define WATCHDOG_NAME "SBSA Generic Watchdog" 65 66 /* SBSA Generic Watchdog register definitions */ 67 /* refresh frame */ 68 #define SBSA_GWDT_WRR 0x000 69 70 /* control frame */ 71 #define SBSA_GWDT_WCS 0x000 72 #define SBSA_GWDT_WOR 0x008 73 #define SBSA_GWDT_WCV 0x010 74 75 /* refresh/control frame */ 76 #define SBSA_GWDT_W_IIDR 0xfcc 77 #define SBSA_GWDT_IDR 0xfd0 78 79 /* Watchdog Control and Status Register */ 80 #define SBSA_GWDT_WCS_EN BIT(0) 81 #define SBSA_GWDT_WCS_WS0 BIT(1) 82 #define SBSA_GWDT_WCS_WS1 BIT(2) 83 84 /** 85 * struct sbsa_gwdt - Internal representation of the SBSA GWDT 86 * @wdd: kernel watchdog_device structure 87 * @clk: store the System Counter clock frequency, in Hz. 88 * @refresh_base: Virtual address of the watchdog refresh frame 89 * @control_base: Virtual address of the watchdog control frame 90 */ 91 struct sbsa_gwdt { 92 struct watchdog_device wdd; 93 u32 clk; 94 void __iomem *refresh_base; 95 void __iomem *control_base; 96 }; 97 98 #define DEFAULT_TIMEOUT 10 /* seconds */ 99 100 static unsigned int timeout; 101 module_param(timeout, uint, 0); 102 MODULE_PARM_DESC(timeout, 103 "Watchdog timeout in seconds. (>=0, default=" 104 __MODULE_STRING(DEFAULT_TIMEOUT) ")"); 105 106 /* 107 * action refers to action taken when watchdog gets WS0 108 * 0 = skip 109 * 1 = panic 110 * defaults to skip (0) 111 */ 112 static int action; 113 module_param(action, int, 0); 114 MODULE_PARM_DESC(action, "after watchdog gets WS0 interrupt, do: " 115 "0 = skip(*) 1 = panic"); 116 117 static bool nowayout = WATCHDOG_NOWAYOUT; 118 module_param(nowayout, bool, S_IRUGO); 119 MODULE_PARM_DESC(nowayout, 120 "Watchdog cannot be stopped once started (default=" 121 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 122 123 /* 124 * watchdog operation functions 125 */ 126 static int sbsa_gwdt_set_timeout(struct watchdog_device *wdd, 127 unsigned int timeout) 128 { 129 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); 130 131 wdd->timeout = timeout; 132 133 if (action) 134 writel(gwdt->clk * timeout, 135 gwdt->control_base + SBSA_GWDT_WOR); 136 else 137 /* 138 * In the single stage mode, The first signal (WS0) is ignored, 139 * the timeout is (WOR * 2), so the WOR should be configured 140 * to half value of timeout. 141 */ 142 writel(gwdt->clk / 2 * timeout, 143 gwdt->control_base + SBSA_GWDT_WOR); 144 145 return 0; 146 } 147 148 static unsigned int sbsa_gwdt_get_timeleft(struct watchdog_device *wdd) 149 { 150 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); 151 u64 timeleft = 0; 152 153 /* 154 * In the single stage mode, if WS0 is deasserted 155 * (watchdog is in the first stage), 156 * timeleft = WOR + (WCV - system counter) 157 */ 158 if (!action && 159 !(readl(gwdt->control_base + SBSA_GWDT_WCS) & SBSA_GWDT_WCS_WS0)) 160 timeleft += readl(gwdt->control_base + SBSA_GWDT_WOR); 161 162 timeleft += readq(gwdt->control_base + SBSA_GWDT_WCV) - 163 arch_counter_get_cntvct(); 164 165 do_div(timeleft, gwdt->clk); 166 167 return timeleft; 168 } 169 170 static int sbsa_gwdt_keepalive(struct watchdog_device *wdd) 171 { 172 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); 173 174 /* 175 * Writing WRR for an explicit watchdog refresh. 176 * You can write anyting (like 0). 177 */ 178 writel(0, gwdt->refresh_base + SBSA_GWDT_WRR); 179 180 return 0; 181 } 182 183 static int sbsa_gwdt_start(struct watchdog_device *wdd) 184 { 185 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); 186 187 /* writing WCS will cause an explicit watchdog refresh */ 188 writel(SBSA_GWDT_WCS_EN, gwdt->control_base + SBSA_GWDT_WCS); 189 190 return 0; 191 } 192 193 static int sbsa_gwdt_stop(struct watchdog_device *wdd) 194 { 195 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); 196 197 /* Simply write 0 to WCS to clean WCS_EN bit */ 198 writel(0, gwdt->control_base + SBSA_GWDT_WCS); 199 200 return 0; 201 } 202 203 static irqreturn_t sbsa_gwdt_interrupt(int irq, void *dev_id) 204 { 205 panic(WATCHDOG_NAME " timeout"); 206 207 return IRQ_HANDLED; 208 } 209 210 static const struct watchdog_info sbsa_gwdt_info = { 211 .identity = WATCHDOG_NAME, 212 .options = WDIOF_SETTIMEOUT | 213 WDIOF_KEEPALIVEPING | 214 WDIOF_MAGICCLOSE | 215 WDIOF_CARDRESET, 216 }; 217 218 static const struct watchdog_ops sbsa_gwdt_ops = { 219 .owner = THIS_MODULE, 220 .start = sbsa_gwdt_start, 221 .stop = sbsa_gwdt_stop, 222 .ping = sbsa_gwdt_keepalive, 223 .set_timeout = sbsa_gwdt_set_timeout, 224 .get_timeleft = sbsa_gwdt_get_timeleft, 225 }; 226 227 static int sbsa_gwdt_probe(struct platform_device *pdev) 228 { 229 void __iomem *rf_base, *cf_base; 230 struct device *dev = &pdev->dev; 231 struct watchdog_device *wdd; 232 struct sbsa_gwdt *gwdt; 233 struct resource *res; 234 int ret, irq; 235 u32 status; 236 237 gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL); 238 if (!gwdt) 239 return -ENOMEM; 240 platform_set_drvdata(pdev, gwdt); 241 242 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 243 cf_base = devm_ioremap_resource(dev, res); 244 if (IS_ERR(cf_base)) 245 return PTR_ERR(cf_base); 246 247 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 248 rf_base = devm_ioremap_resource(dev, res); 249 if (IS_ERR(rf_base)) 250 return PTR_ERR(rf_base); 251 252 /* 253 * Get the frequency of system counter from the cp15 interface of ARM 254 * Generic timer. We don't need to check it, because if it returns "0", 255 * system would panic in very early stage. 256 */ 257 gwdt->clk = arch_timer_get_cntfrq(); 258 gwdt->refresh_base = rf_base; 259 gwdt->control_base = cf_base; 260 261 wdd = &gwdt->wdd; 262 wdd->parent = dev; 263 wdd->info = &sbsa_gwdt_info; 264 wdd->ops = &sbsa_gwdt_ops; 265 wdd->min_timeout = 1; 266 wdd->max_hw_heartbeat_ms = U32_MAX / gwdt->clk * 1000; 267 wdd->timeout = DEFAULT_TIMEOUT; 268 watchdog_set_drvdata(wdd, gwdt); 269 watchdog_set_nowayout(wdd, nowayout); 270 271 status = readl(cf_base + SBSA_GWDT_WCS); 272 if (status & SBSA_GWDT_WCS_WS1) { 273 dev_warn(dev, "System reset by WDT.\n"); 274 wdd->bootstatus |= WDIOF_CARDRESET; 275 } 276 if (status & SBSA_GWDT_WCS_EN) 277 set_bit(WDOG_HW_RUNNING, &wdd->status); 278 279 if (action) { 280 irq = platform_get_irq(pdev, 0); 281 if (irq < 0) { 282 action = 0; 283 dev_warn(dev, "unable to get ws0 interrupt.\n"); 284 } else { 285 /* 286 * In case there is a pending ws0 interrupt, just ping 287 * the watchdog before registering the interrupt routine 288 */ 289 writel(0, rf_base + SBSA_GWDT_WRR); 290 if (devm_request_irq(dev, irq, sbsa_gwdt_interrupt, 0, 291 pdev->name, gwdt)) { 292 action = 0; 293 dev_warn(dev, "unable to request IRQ %d.\n", 294 irq); 295 } 296 } 297 if (!action) 298 dev_warn(dev, "falling back to single stage mode.\n"); 299 } 300 /* 301 * In the single stage mode, The first signal (WS0) is ignored, 302 * the timeout is (WOR * 2), so the maximum timeout should be doubled. 303 */ 304 if (!action) 305 wdd->max_hw_heartbeat_ms *= 2; 306 307 watchdog_init_timeout(wdd, timeout, dev); 308 /* 309 * Update timeout to WOR. 310 * Because of the explicit watchdog refresh mechanism, 311 * it's also a ping, if watchdog is enabled. 312 */ 313 sbsa_gwdt_set_timeout(wdd, wdd->timeout); 314 315 ret = watchdog_register_device(wdd); 316 if (ret) 317 return ret; 318 319 dev_info(dev, "Initialized with %ds timeout @ %u Hz, action=%d.%s\n", 320 wdd->timeout, gwdt->clk, action, 321 status & SBSA_GWDT_WCS_EN ? " [enabled]" : ""); 322 323 return 0; 324 } 325 326 static void sbsa_gwdt_shutdown(struct platform_device *pdev) 327 { 328 struct sbsa_gwdt *gwdt = platform_get_drvdata(pdev); 329 330 sbsa_gwdt_stop(&gwdt->wdd); 331 } 332 333 static int sbsa_gwdt_remove(struct platform_device *pdev) 334 { 335 struct sbsa_gwdt *gwdt = platform_get_drvdata(pdev); 336 337 watchdog_unregister_device(&gwdt->wdd); 338 339 return 0; 340 } 341 342 /* Disable watchdog if it is active during suspend */ 343 static int __maybe_unused sbsa_gwdt_suspend(struct device *dev) 344 { 345 struct sbsa_gwdt *gwdt = dev_get_drvdata(dev); 346 347 if (watchdog_active(&gwdt->wdd)) 348 sbsa_gwdt_stop(&gwdt->wdd); 349 350 return 0; 351 } 352 353 /* Enable watchdog if necessary */ 354 static int __maybe_unused sbsa_gwdt_resume(struct device *dev) 355 { 356 struct sbsa_gwdt *gwdt = dev_get_drvdata(dev); 357 358 if (watchdog_active(&gwdt->wdd)) 359 sbsa_gwdt_start(&gwdt->wdd); 360 361 return 0; 362 } 363 364 static const struct dev_pm_ops sbsa_gwdt_pm_ops = { 365 SET_SYSTEM_SLEEP_PM_OPS(sbsa_gwdt_suspend, sbsa_gwdt_resume) 366 }; 367 368 static const struct of_device_id sbsa_gwdt_of_match[] = { 369 { .compatible = "arm,sbsa-gwdt", }, 370 {}, 371 }; 372 MODULE_DEVICE_TABLE(of, sbsa_gwdt_of_match); 373 374 static const struct platform_device_id sbsa_gwdt_pdev_match[] = { 375 { .name = DRV_NAME, }, 376 {}, 377 }; 378 MODULE_DEVICE_TABLE(platform, sbsa_gwdt_pdev_match); 379 380 static struct platform_driver sbsa_gwdt_driver = { 381 .driver = { 382 .name = DRV_NAME, 383 .pm = &sbsa_gwdt_pm_ops, 384 .of_match_table = sbsa_gwdt_of_match, 385 }, 386 .probe = sbsa_gwdt_probe, 387 .remove = sbsa_gwdt_remove, 388 .shutdown = sbsa_gwdt_shutdown, 389 .id_table = sbsa_gwdt_pdev_match, 390 }; 391 392 module_platform_driver(sbsa_gwdt_driver); 393 394 MODULE_DESCRIPTION("SBSA Generic Watchdog Driver"); 395 MODULE_AUTHOR("Fu Wei <fu.wei@linaro.org>"); 396 MODULE_AUTHOR("Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>"); 397 MODULE_AUTHOR("Al Stone <al.stone@linaro.org>"); 398 MODULE_AUTHOR("Timur Tabi <timur@codeaurora.org>"); 399 MODULE_LICENSE("GPL v2"); 400 MODULE_ALIAS("platform:" DRV_NAME); 401