1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * SBSA(Server Base System Architecture) Generic Watchdog driver 4 * 5 * Copyright (c) 2015, Linaro Ltd. 6 * Author: Fu Wei <fu.wei@linaro.org> 7 * Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> 8 * Al Stone <al.stone@linaro.org> 9 * Timur Tabi <timur@codeaurora.org> 10 * 11 * ARM SBSA Generic Watchdog has two stage timeouts: 12 * the first signal (WS0) is for alerting the system by interrupt, 13 * the second one (WS1) is a real hardware reset. 14 * More details about the hardware specification of this device: 15 * ARM DEN0029B - Server Base System Architecture (SBSA) 16 * 17 * This driver can operate ARM SBSA Generic Watchdog as a single stage watchdog 18 * or a two stages watchdog, it's set up by the module parameter "action". 19 * In the single stage mode, when the timeout is reached, your system 20 * will be reset by WS1. The first signal (WS0) is ignored. 21 * In the two stages mode, when the timeout is reached, the first signal (WS0) 22 * will trigger panic. If the system is getting into trouble and cannot be reset 23 * by panic or restart properly by the kdump kernel(if supported), then the 24 * second stage (as long as the first stage) will be reached, system will be 25 * reset by WS1. This function can help administrator to backup the system 26 * context info by panic console output or kdump. 27 * 28 * SBSA GWDT: 29 * if action is 1 (the two stages mode): 30 * |--------WOR-------WS0--------WOR-------WS1 31 * |----timeout-----(panic)----timeout-----reset 32 * 33 * if action is 0 (the single stage mode): 34 * |------WOR-----WS0(ignored)-----WOR------WS1 35 * |--------------timeout-------------------reset 36 * 37 * Note: Since this watchdog timer has two stages, and each stage is determined 38 * by WOR, in the single stage mode, the timeout is (WOR * 2); in the two 39 * stages mode, the timeout is WOR. The maximum timeout in the two stages mode 40 * is half of that in the single stage mode. 41 */ 42 43 #include <linux/io.h> 44 #include <linux/io-64-nonatomic-lo-hi.h> 45 #include <linux/interrupt.h> 46 #include <linux/module.h> 47 #include <linux/moduleparam.h> 48 #include <linux/of.h> 49 #include <linux/of_device.h> 50 #include <linux/platform_device.h> 51 #include <linux/uaccess.h> 52 #include <linux/watchdog.h> 53 #include <asm/arch_timer.h> 54 55 #define DRV_NAME "sbsa-gwdt" 56 #define WATCHDOG_NAME "SBSA Generic Watchdog" 57 58 /* SBSA Generic Watchdog register definitions */ 59 /* refresh frame */ 60 #define SBSA_GWDT_WRR 0x000 61 62 /* control frame */ 63 #define SBSA_GWDT_WCS 0x000 64 #define SBSA_GWDT_WOR 0x008 65 #define SBSA_GWDT_WCV 0x010 66 67 /* refresh/control frame */ 68 #define SBSA_GWDT_W_IIDR 0xfcc 69 #define SBSA_GWDT_IDR 0xfd0 70 71 /* Watchdog Control and Status Register */ 72 #define SBSA_GWDT_WCS_EN BIT(0) 73 #define SBSA_GWDT_WCS_WS0 BIT(1) 74 #define SBSA_GWDT_WCS_WS1 BIT(2) 75 76 #define SBSA_GWDT_VERSION_MASK 0xF 77 #define SBSA_GWDT_VERSION_SHIFT 16 78 79 /** 80 * struct sbsa_gwdt - Internal representation of the SBSA GWDT 81 * @wdd: kernel watchdog_device structure 82 * @clk: store the System Counter clock frequency, in Hz. 83 * @version: store the architecture version 84 * @refresh_base: Virtual address of the watchdog refresh frame 85 * @control_base: Virtual address of the watchdog control frame 86 */ 87 struct sbsa_gwdt { 88 struct watchdog_device wdd; 89 u32 clk; 90 int version; 91 void __iomem *refresh_base; 92 void __iomem *control_base; 93 }; 94 95 #define DEFAULT_TIMEOUT 10 /* seconds */ 96 97 static unsigned int timeout; 98 module_param(timeout, uint, 0); 99 MODULE_PARM_DESC(timeout, 100 "Watchdog timeout in seconds. (>=0, default=" 101 __MODULE_STRING(DEFAULT_TIMEOUT) ")"); 102 103 /* 104 * action refers to action taken when watchdog gets WS0 105 * 0 = skip 106 * 1 = panic 107 * defaults to skip (0) 108 */ 109 static int action; 110 module_param(action, int, 0); 111 MODULE_PARM_DESC(action, "after watchdog gets WS0 interrupt, do: " 112 "0 = skip(*) 1 = panic"); 113 114 static bool nowayout = WATCHDOG_NOWAYOUT; 115 module_param(nowayout, bool, S_IRUGO); 116 MODULE_PARM_DESC(nowayout, 117 "Watchdog cannot be stopped once started (default=" 118 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 119 120 /* 121 * Arm Base System Architecture 1.0 introduces watchdog v1 which 122 * increases the length watchdog offset register to 48 bits. 123 * - For version 0: WOR is 32 bits; 124 * - For version 1: WOR is 48 bits which comprises the register 125 * offset 0x8 and 0xC, and the bits [63:48] are reserved which are 126 * Read-As-Zero and Writes-Ignored. 127 */ 128 static u64 sbsa_gwdt_reg_read(struct sbsa_gwdt *gwdt) 129 { 130 if (gwdt->version == 0) 131 return readl(gwdt->control_base + SBSA_GWDT_WOR); 132 else 133 return lo_hi_readq(gwdt->control_base + SBSA_GWDT_WOR); 134 } 135 136 static void sbsa_gwdt_reg_write(u64 val, struct sbsa_gwdt *gwdt) 137 { 138 if (gwdt->version == 0) 139 writel((u32)val, gwdt->control_base + SBSA_GWDT_WOR); 140 else 141 lo_hi_writeq(val, gwdt->control_base + SBSA_GWDT_WOR); 142 } 143 144 /* 145 * watchdog operation functions 146 */ 147 static int sbsa_gwdt_set_timeout(struct watchdog_device *wdd, 148 unsigned int timeout) 149 { 150 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); 151 152 wdd->timeout = timeout; 153 timeout = clamp_t(unsigned int, timeout, 1, wdd->max_hw_heartbeat_ms / 1000); 154 155 if (action) 156 sbsa_gwdt_reg_write(gwdt->clk * timeout, gwdt); 157 else 158 /* 159 * In the single stage mode, The first signal (WS0) is ignored, 160 * the timeout is (WOR * 2), so the WOR should be configured 161 * to half value of timeout. 162 */ 163 sbsa_gwdt_reg_write(gwdt->clk / 2 * timeout, gwdt); 164 165 return 0; 166 } 167 168 static unsigned int sbsa_gwdt_get_timeleft(struct watchdog_device *wdd) 169 { 170 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); 171 u64 timeleft = 0; 172 173 /* 174 * In the single stage mode, if WS0 is deasserted 175 * (watchdog is in the first stage), 176 * timeleft = WOR + (WCV - system counter) 177 */ 178 if (!action && 179 !(readl(gwdt->control_base + SBSA_GWDT_WCS) & SBSA_GWDT_WCS_WS0)) 180 timeleft += sbsa_gwdt_reg_read(gwdt); 181 182 timeleft += lo_hi_readq(gwdt->control_base + SBSA_GWDT_WCV) - 183 arch_timer_read_counter(); 184 185 do_div(timeleft, gwdt->clk); 186 187 return timeleft; 188 } 189 190 static int sbsa_gwdt_keepalive(struct watchdog_device *wdd) 191 { 192 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); 193 194 /* 195 * Writing WRR for an explicit watchdog refresh. 196 * You can write anyting (like 0). 197 */ 198 writel(0, gwdt->refresh_base + SBSA_GWDT_WRR); 199 200 return 0; 201 } 202 203 static void sbsa_gwdt_get_version(struct watchdog_device *wdd) 204 { 205 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); 206 int ver; 207 208 ver = readl(gwdt->control_base + SBSA_GWDT_W_IIDR); 209 ver = (ver >> SBSA_GWDT_VERSION_SHIFT) & SBSA_GWDT_VERSION_MASK; 210 211 gwdt->version = ver; 212 } 213 214 static int sbsa_gwdt_start(struct watchdog_device *wdd) 215 { 216 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); 217 218 /* writing WCS will cause an explicit watchdog refresh */ 219 writel(SBSA_GWDT_WCS_EN, gwdt->control_base + SBSA_GWDT_WCS); 220 221 return 0; 222 } 223 224 static int sbsa_gwdt_stop(struct watchdog_device *wdd) 225 { 226 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); 227 228 /* Simply write 0 to WCS to clean WCS_EN bit */ 229 writel(0, gwdt->control_base + SBSA_GWDT_WCS); 230 231 return 0; 232 } 233 234 static irqreturn_t sbsa_gwdt_interrupt(int irq, void *dev_id) 235 { 236 panic(WATCHDOG_NAME " timeout"); 237 238 return IRQ_HANDLED; 239 } 240 241 static const struct watchdog_info sbsa_gwdt_info = { 242 .identity = WATCHDOG_NAME, 243 .options = WDIOF_SETTIMEOUT | 244 WDIOF_KEEPALIVEPING | 245 WDIOF_MAGICCLOSE | 246 WDIOF_CARDRESET, 247 }; 248 249 static const struct watchdog_ops sbsa_gwdt_ops = { 250 .owner = THIS_MODULE, 251 .start = sbsa_gwdt_start, 252 .stop = sbsa_gwdt_stop, 253 .ping = sbsa_gwdt_keepalive, 254 .set_timeout = sbsa_gwdt_set_timeout, 255 .get_timeleft = sbsa_gwdt_get_timeleft, 256 }; 257 258 static int sbsa_gwdt_probe(struct platform_device *pdev) 259 { 260 void __iomem *rf_base, *cf_base; 261 struct device *dev = &pdev->dev; 262 struct watchdog_device *wdd; 263 struct sbsa_gwdt *gwdt; 264 int ret, irq; 265 u32 status; 266 267 gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL); 268 if (!gwdt) 269 return -ENOMEM; 270 platform_set_drvdata(pdev, gwdt); 271 272 cf_base = devm_platform_ioremap_resource(pdev, 0); 273 if (IS_ERR(cf_base)) 274 return PTR_ERR(cf_base); 275 276 rf_base = devm_platform_ioremap_resource(pdev, 1); 277 if (IS_ERR(rf_base)) 278 return PTR_ERR(rf_base); 279 280 /* 281 * Get the frequency of system counter from the cp15 interface of ARM 282 * Generic timer. We don't need to check it, because if it returns "0", 283 * system would panic in very early stage. 284 */ 285 gwdt->clk = arch_timer_get_cntfrq(); 286 gwdt->refresh_base = rf_base; 287 gwdt->control_base = cf_base; 288 289 wdd = &gwdt->wdd; 290 wdd->parent = dev; 291 wdd->info = &sbsa_gwdt_info; 292 wdd->ops = &sbsa_gwdt_ops; 293 wdd->min_timeout = 1; 294 wdd->timeout = DEFAULT_TIMEOUT; 295 watchdog_set_drvdata(wdd, gwdt); 296 watchdog_set_nowayout(wdd, nowayout); 297 sbsa_gwdt_get_version(wdd); 298 if (gwdt->version == 0) 299 wdd->max_hw_heartbeat_ms = U32_MAX / gwdt->clk * 1000; 300 else 301 wdd->max_hw_heartbeat_ms = GENMASK_ULL(47, 0) / gwdt->clk * 1000; 302 303 status = readl(cf_base + SBSA_GWDT_WCS); 304 if (status & SBSA_GWDT_WCS_WS1) { 305 dev_warn(dev, "System reset by WDT.\n"); 306 wdd->bootstatus |= WDIOF_CARDRESET; 307 } 308 if (status & SBSA_GWDT_WCS_EN) 309 set_bit(WDOG_HW_RUNNING, &wdd->status); 310 311 if (action) { 312 irq = platform_get_irq(pdev, 0); 313 if (irq < 0) { 314 action = 0; 315 dev_warn(dev, "unable to get ws0 interrupt.\n"); 316 } else { 317 /* 318 * In case there is a pending ws0 interrupt, just ping 319 * the watchdog before registering the interrupt routine 320 */ 321 writel(0, rf_base + SBSA_GWDT_WRR); 322 if (devm_request_irq(dev, irq, sbsa_gwdt_interrupt, 0, 323 pdev->name, gwdt)) { 324 action = 0; 325 dev_warn(dev, "unable to request IRQ %d.\n", 326 irq); 327 } 328 } 329 if (!action) 330 dev_warn(dev, "falling back to single stage mode.\n"); 331 } 332 /* 333 * In the single stage mode, The first signal (WS0) is ignored, 334 * the timeout is (WOR * 2), so the maximum timeout should be doubled. 335 */ 336 if (!action) 337 wdd->max_hw_heartbeat_ms *= 2; 338 339 watchdog_init_timeout(wdd, timeout, dev); 340 /* 341 * Update timeout to WOR. 342 * Because of the explicit watchdog refresh mechanism, 343 * it's also a ping, if watchdog is enabled. 344 */ 345 sbsa_gwdt_set_timeout(wdd, wdd->timeout); 346 347 watchdog_stop_on_reboot(wdd); 348 ret = devm_watchdog_register_device(dev, wdd); 349 if (ret) 350 return ret; 351 352 dev_info(dev, "Initialized with %ds timeout @ %u Hz, action=%d.%s\n", 353 wdd->timeout, gwdt->clk, action, 354 status & SBSA_GWDT_WCS_EN ? " [enabled]" : ""); 355 356 return 0; 357 } 358 359 /* Disable watchdog if it is active during suspend */ 360 static int __maybe_unused sbsa_gwdt_suspend(struct device *dev) 361 { 362 struct sbsa_gwdt *gwdt = dev_get_drvdata(dev); 363 364 if (watchdog_active(&gwdt->wdd)) 365 sbsa_gwdt_stop(&gwdt->wdd); 366 367 return 0; 368 } 369 370 /* Enable watchdog if necessary */ 371 static int __maybe_unused sbsa_gwdt_resume(struct device *dev) 372 { 373 struct sbsa_gwdt *gwdt = dev_get_drvdata(dev); 374 375 if (watchdog_active(&gwdt->wdd)) 376 sbsa_gwdt_start(&gwdt->wdd); 377 378 return 0; 379 } 380 381 static const struct dev_pm_ops sbsa_gwdt_pm_ops = { 382 SET_SYSTEM_SLEEP_PM_OPS(sbsa_gwdt_suspend, sbsa_gwdt_resume) 383 }; 384 385 static const struct of_device_id sbsa_gwdt_of_match[] = { 386 { .compatible = "arm,sbsa-gwdt", }, 387 {}, 388 }; 389 MODULE_DEVICE_TABLE(of, sbsa_gwdt_of_match); 390 391 static const struct platform_device_id sbsa_gwdt_pdev_match[] = { 392 { .name = DRV_NAME, }, 393 {}, 394 }; 395 MODULE_DEVICE_TABLE(platform, sbsa_gwdt_pdev_match); 396 397 static struct platform_driver sbsa_gwdt_driver = { 398 .driver = { 399 .name = DRV_NAME, 400 .pm = &sbsa_gwdt_pm_ops, 401 .of_match_table = sbsa_gwdt_of_match, 402 }, 403 .probe = sbsa_gwdt_probe, 404 .id_table = sbsa_gwdt_pdev_match, 405 }; 406 407 module_platform_driver(sbsa_gwdt_driver); 408 409 MODULE_DESCRIPTION("SBSA Generic Watchdog Driver"); 410 MODULE_AUTHOR("Fu Wei <fu.wei@linaro.org>"); 411 MODULE_AUTHOR("Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>"); 412 MODULE_AUTHOR("Al Stone <al.stone@linaro.org>"); 413 MODULE_AUTHOR("Timur Tabi <timur@codeaurora.org>"); 414 MODULE_LICENSE("GPL v2"); 415