1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Driver for Atmel SAMA5D4 Watchdog Timer
4  *
5  * Copyright (C) 2015-2019 Microchip Technology Inc. and its subsidiaries
6  */
7 
8 #include <linux/delay.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_irq.h>
15 #include <linux/platform_device.h>
16 #include <linux/reboot.h>
17 #include <linux/watchdog.h>
18 
19 #include "at91sam9_wdt.h"
20 
21 /* minimum and maximum watchdog timeout, in seconds */
22 #define MIN_WDT_TIMEOUT		1
23 #define MAX_WDT_TIMEOUT		16
24 #define WDT_DEFAULT_TIMEOUT	MAX_WDT_TIMEOUT
25 
26 #define WDT_SEC2TICKS(s)	((s) ? (((s) << 8) - 1) : 0)
27 
28 struct sama5d4_wdt {
29 	struct watchdog_device	wdd;
30 	void __iomem		*reg_base;
31 	u32			mr;
32 	u32			ir;
33 	unsigned long		last_ping;
34 	bool			need_irq;
35 	bool			sam9x60_support;
36 };
37 
38 static int wdt_timeout;
39 static bool nowayout = WATCHDOG_NOWAYOUT;
40 
41 module_param(wdt_timeout, int, 0);
42 MODULE_PARM_DESC(wdt_timeout,
43 	"Watchdog timeout in seconds. (default = "
44 	__MODULE_STRING(WDT_DEFAULT_TIMEOUT) ")");
45 
46 module_param(nowayout, bool, 0);
47 MODULE_PARM_DESC(nowayout,
48 	"Watchdog cannot be stopped once started (default="
49 	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
50 
51 #define wdt_enabled (!(wdt->mr & AT91_WDT_WDDIS))
52 
53 #define wdt_read(wdt, field) \
54 	readl_relaxed((wdt)->reg_base + (field))
55 
56 /* 4 slow clock periods is 4/32768 = 122.07µs*/
57 #define WDT_DELAY	usecs_to_jiffies(123)
58 
59 static void wdt_write(struct sama5d4_wdt *wdt, u32 field, u32 val)
60 {
61 	/*
62 	 * WDT_CR and WDT_MR must not be modified within three slow clock
63 	 * periods following a restart of the watchdog performed by a write
64 	 * access in WDT_CR.
65 	 */
66 	while (time_before(jiffies, wdt->last_ping + WDT_DELAY))
67 		usleep_range(30, 125);
68 	writel_relaxed(val, wdt->reg_base + field);
69 	wdt->last_ping = jiffies;
70 }
71 
72 static void wdt_write_nosleep(struct sama5d4_wdt *wdt, u32 field, u32 val)
73 {
74 	if (time_before(jiffies, wdt->last_ping + WDT_DELAY))
75 		udelay(123);
76 	writel_relaxed(val, wdt->reg_base + field);
77 	wdt->last_ping = jiffies;
78 }
79 
80 static int sama5d4_wdt_start(struct watchdog_device *wdd)
81 {
82 	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
83 
84 	if (wdt->sam9x60_support) {
85 		writel_relaxed(wdt->ir, wdt->reg_base + AT91_SAM9X60_IER);
86 		wdt->mr &= ~AT91_SAM9X60_WDDIS;
87 	} else {
88 		wdt->mr &= ~AT91_WDT_WDDIS;
89 	}
90 	wdt_write(wdt, AT91_WDT_MR, wdt->mr);
91 
92 	return 0;
93 }
94 
95 static int sama5d4_wdt_stop(struct watchdog_device *wdd)
96 {
97 	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
98 
99 	if (wdt->sam9x60_support) {
100 		writel_relaxed(wdt->ir, wdt->reg_base + AT91_SAM9X60_IDR);
101 		wdt->mr |= AT91_SAM9X60_WDDIS;
102 	} else {
103 		wdt->mr |= AT91_WDT_WDDIS;
104 	}
105 	wdt_write(wdt, AT91_WDT_MR, wdt->mr);
106 
107 	return 0;
108 }
109 
110 static int sama5d4_wdt_ping(struct watchdog_device *wdd)
111 {
112 	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
113 
114 	wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
115 
116 	return 0;
117 }
118 
119 static int sama5d4_wdt_set_timeout(struct watchdog_device *wdd,
120 				 unsigned int timeout)
121 {
122 	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
123 	u32 value = WDT_SEC2TICKS(timeout);
124 
125 	if (wdt->sam9x60_support) {
126 		wdt_write(wdt, AT91_SAM9X60_WLR,
127 			  AT91_SAM9X60_SET_COUNTER(value));
128 
129 		wdd->timeout = timeout;
130 		return 0;
131 	}
132 
133 	wdt->mr &= ~AT91_WDT_WDV;
134 	wdt->mr |= AT91_WDT_SET_WDV(value);
135 
136 	/*
137 	 * WDDIS has to be 0 when updating WDD/WDV. The datasheet states: When
138 	 * setting the WDDIS bit, and while it is set, the fields WDV and WDD
139 	 * must not be modified.
140 	 * If the watchdog is enabled, then the timeout can be updated. Else,
141 	 * wait that the user enables it.
142 	 */
143 	if (wdt_enabled)
144 		wdt_write(wdt, AT91_WDT_MR, wdt->mr & ~AT91_WDT_WDDIS);
145 
146 	wdd->timeout = timeout;
147 
148 	return 0;
149 }
150 
151 static const struct watchdog_info sama5d4_wdt_info = {
152 	.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
153 	.identity = "Atmel SAMA5D4 Watchdog",
154 };
155 
156 static const struct watchdog_ops sama5d4_wdt_ops = {
157 	.owner = THIS_MODULE,
158 	.start = sama5d4_wdt_start,
159 	.stop = sama5d4_wdt_stop,
160 	.ping = sama5d4_wdt_ping,
161 	.set_timeout = sama5d4_wdt_set_timeout,
162 };
163 
164 static irqreturn_t sama5d4_wdt_irq_handler(int irq, void *dev_id)
165 {
166 	struct sama5d4_wdt *wdt = platform_get_drvdata(dev_id);
167 	u32 reg;
168 
169 	if (wdt->sam9x60_support)
170 		reg = wdt_read(wdt, AT91_SAM9X60_ISR);
171 	else
172 		reg = wdt_read(wdt, AT91_WDT_SR);
173 
174 	if (reg) {
175 		pr_crit("Atmel Watchdog Software Reset\n");
176 		emergency_restart();
177 		pr_crit("Reboot didn't succeed\n");
178 	}
179 
180 	return IRQ_HANDLED;
181 }
182 
183 static int of_sama5d4_wdt_init(struct device_node *np, struct sama5d4_wdt *wdt)
184 {
185 	const char *tmp;
186 
187 	if (wdt->sam9x60_support)
188 		wdt->mr = AT91_SAM9X60_WDDIS;
189 	else
190 		wdt->mr = AT91_WDT_WDDIS;
191 
192 	if (!of_property_read_string(np, "atmel,watchdog-type", &tmp) &&
193 	    !strcmp(tmp, "software"))
194 		wdt->need_irq = true;
195 
196 	if (of_property_read_bool(np, "atmel,idle-halt"))
197 		wdt->mr |= AT91_WDT_WDIDLEHLT;
198 
199 	if (of_property_read_bool(np, "atmel,dbg-halt"))
200 		wdt->mr |= AT91_WDT_WDDBGHLT;
201 
202 	return 0;
203 }
204 
205 static int sama5d4_wdt_init(struct sama5d4_wdt *wdt)
206 {
207 	u32 reg, val;
208 
209 	val = WDT_SEC2TICKS(WDT_DEFAULT_TIMEOUT);
210 	/*
211 	 * When booting and resuming, the bootloader may have changed the
212 	 * watchdog configuration.
213 	 * If the watchdog is already running, we can safely update it.
214 	 * Else, we have to disable it properly.
215 	 */
216 	if (!wdt_enabled) {
217 		reg = wdt_read(wdt, AT91_WDT_MR);
218 		if (wdt->sam9x60_support && (!(reg & AT91_SAM9X60_WDDIS)))
219 			wdt_write_nosleep(wdt, AT91_WDT_MR,
220 					  reg | AT91_SAM9X60_WDDIS);
221 		else if (!wdt->sam9x60_support &&
222 			 (!(reg & AT91_WDT_WDDIS)))
223 			wdt_write_nosleep(wdt, AT91_WDT_MR,
224 					  reg | AT91_WDT_WDDIS);
225 	}
226 
227 	if (wdt->sam9x60_support) {
228 		if (wdt->need_irq)
229 			wdt->ir = AT91_SAM9X60_PERINT;
230 		else
231 			wdt->mr |= AT91_SAM9X60_PERIODRST;
232 
233 		wdt_write(wdt, AT91_SAM9X60_IER, wdt->ir);
234 		wdt_write(wdt, AT91_SAM9X60_WLR, AT91_SAM9X60_SET_COUNTER(val));
235 	} else {
236 		wdt->mr |= AT91_WDT_SET_WDD(WDT_SEC2TICKS(MAX_WDT_TIMEOUT));
237 		wdt->mr |= AT91_WDT_SET_WDV(val);
238 
239 		if (wdt->need_irq)
240 			wdt->mr |= AT91_WDT_WDFIEN;
241 		else
242 			wdt->mr |= AT91_WDT_WDRSTEN;
243 	}
244 
245 	wdt_write_nosleep(wdt, AT91_WDT_MR, wdt->mr);
246 
247 	return 0;
248 }
249 
250 static int sama5d4_wdt_probe(struct platform_device *pdev)
251 {
252 	struct device *dev = &pdev->dev;
253 	struct watchdog_device *wdd;
254 	struct sama5d4_wdt *wdt;
255 	void __iomem *regs;
256 	u32 irq = 0;
257 	u32 reg;
258 	int ret;
259 
260 	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
261 	if (!wdt)
262 		return -ENOMEM;
263 
264 	wdd = &wdt->wdd;
265 	wdd->timeout = WDT_DEFAULT_TIMEOUT;
266 	wdd->info = &sama5d4_wdt_info;
267 	wdd->ops = &sama5d4_wdt_ops;
268 	wdd->min_timeout = MIN_WDT_TIMEOUT;
269 	wdd->max_timeout = MAX_WDT_TIMEOUT;
270 	wdt->last_ping = jiffies;
271 
272 	if (of_device_is_compatible(dev->of_node, "microchip,sam9x60-wdt") ||
273 	    of_device_is_compatible(dev->of_node, "microchip,sama7g5-wdt"))
274 		wdt->sam9x60_support = true;
275 
276 	watchdog_set_drvdata(wdd, wdt);
277 
278 	regs = devm_platform_ioremap_resource(pdev, 0);
279 	if (IS_ERR(regs))
280 		return PTR_ERR(regs);
281 
282 	wdt->reg_base = regs;
283 
284 	ret = of_sama5d4_wdt_init(dev->of_node, wdt);
285 	if (ret)
286 		return ret;
287 
288 	if (wdt->need_irq) {
289 		irq = irq_of_parse_and_map(dev->of_node, 0);
290 		if (!irq) {
291 			dev_warn(dev, "failed to get IRQ from DT\n");
292 			wdt->need_irq = false;
293 		}
294 	}
295 
296 	if (wdt->need_irq) {
297 		ret = devm_request_irq(dev, irq, sama5d4_wdt_irq_handler,
298 				       IRQF_SHARED | IRQF_IRQPOLL |
299 				       IRQF_NO_SUSPEND, pdev->name, pdev);
300 		if (ret) {
301 			dev_err(dev, "cannot register interrupt handler\n");
302 			return ret;
303 		}
304 	}
305 
306 	watchdog_init_timeout(wdd, wdt_timeout, dev);
307 
308 	reg = wdt_read(wdt, AT91_WDT_MR);
309 	if (!(reg & AT91_WDT_WDDIS)) {
310 		wdt->mr &= ~AT91_WDT_WDDIS;
311 		set_bit(WDOG_HW_RUNNING, &wdd->status);
312 	}
313 
314 	ret = sama5d4_wdt_init(wdt);
315 	if (ret)
316 		return ret;
317 
318 	watchdog_set_nowayout(wdd, nowayout);
319 
320 	watchdog_stop_on_unregister(wdd);
321 	ret = devm_watchdog_register_device(dev, wdd);
322 	if (ret)
323 		return ret;
324 
325 	platform_set_drvdata(pdev, wdt);
326 
327 	dev_info(dev, "initialized (timeout = %d sec, nowayout = %d)\n",
328 		 wdd->timeout, nowayout);
329 
330 	return 0;
331 }
332 
333 static const struct of_device_id sama5d4_wdt_of_match[] = {
334 	{
335 		.compatible = "atmel,sama5d4-wdt",
336 	},
337 	{
338 		.compatible = "microchip,sam9x60-wdt",
339 	},
340 	{
341 		.compatible = "microchip,sama7g5-wdt",
342 	},
343 
344 	{ }
345 };
346 MODULE_DEVICE_TABLE(of, sama5d4_wdt_of_match);
347 
348 static int sama5d4_wdt_suspend_late(struct device *dev)
349 {
350 	struct sama5d4_wdt *wdt = dev_get_drvdata(dev);
351 
352 	if (watchdog_active(&wdt->wdd))
353 		sama5d4_wdt_stop(&wdt->wdd);
354 
355 	return 0;
356 }
357 
358 static int sama5d4_wdt_resume_early(struct device *dev)
359 {
360 	struct sama5d4_wdt *wdt = dev_get_drvdata(dev);
361 
362 	/*
363 	 * FIXME: writing MR also pings the watchdog which may not be desired.
364 	 * This should only be done when the registers are lost on suspend but
365 	 * there is no way to get this information right now.
366 	 */
367 	sama5d4_wdt_init(wdt);
368 
369 	if (watchdog_active(&wdt->wdd))
370 		sama5d4_wdt_start(&wdt->wdd);
371 
372 	return 0;
373 }
374 
375 static const struct dev_pm_ops sama5d4_wdt_pm_ops = {
376 	LATE_SYSTEM_SLEEP_PM_OPS(sama5d4_wdt_suspend_late,
377 				 sama5d4_wdt_resume_early)
378 };
379 
380 static struct platform_driver sama5d4_wdt_driver = {
381 	.probe		= sama5d4_wdt_probe,
382 	.driver		= {
383 		.name	= "sama5d4_wdt",
384 		.pm	= pm_sleep_ptr(&sama5d4_wdt_pm_ops),
385 		.of_match_table = sama5d4_wdt_of_match,
386 	}
387 };
388 module_platform_driver(sama5d4_wdt_driver);
389 
390 MODULE_AUTHOR("Atmel Corporation");
391 MODULE_DESCRIPTION("Atmel SAMA5D4 Watchdog Timer driver");
392 MODULE_LICENSE("GPL v2");
393