1 /* linux/drivers/char/watchdog/s3c2410_wdt.c 2 * 3 * Copyright (c) 2004 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * 6 * S3C2410 Watchdog Timer Support 7 * 8 * Based on, softdog.c by Alan Cox, 9 * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 24 */ 25 26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 27 28 #include <linux/module.h> 29 #include <linux/moduleparam.h> 30 #include <linux/types.h> 31 #include <linux/timer.h> 32 #include <linux/watchdog.h> 33 #include <linux/init.h> 34 #include <linux/platform_device.h> 35 #include <linux/interrupt.h> 36 #include <linux/clk.h> 37 #include <linux/uaccess.h> 38 #include <linux/io.h> 39 #include <linux/cpufreq.h> 40 #include <linux/slab.h> 41 #include <linux/err.h> 42 #include <linux/of.h> 43 44 #define S3C2410_WTCON 0x00 45 #define S3C2410_WTDAT 0x04 46 #define S3C2410_WTCNT 0x08 47 48 #define S3C2410_WTCON_RSTEN (1 << 0) 49 #define S3C2410_WTCON_INTEN (1 << 2) 50 #define S3C2410_WTCON_ENABLE (1 << 5) 51 52 #define S3C2410_WTCON_DIV16 (0 << 3) 53 #define S3C2410_WTCON_DIV32 (1 << 3) 54 #define S3C2410_WTCON_DIV64 (2 << 3) 55 #define S3C2410_WTCON_DIV128 (3 << 3) 56 57 #define S3C2410_WTCON_PRESCALE(x) ((x) << 8) 58 #define S3C2410_WTCON_PRESCALE_MASK (0xff << 8) 59 60 #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0) 61 #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15) 62 63 static bool nowayout = WATCHDOG_NOWAYOUT; 64 static int tmr_margin; 65 static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT; 66 static int soft_noboot; 67 static int debug; 68 69 module_param(tmr_margin, int, 0); 70 module_param(tmr_atboot, int, 0); 71 module_param(nowayout, bool, 0); 72 module_param(soft_noboot, int, 0); 73 module_param(debug, int, 0); 74 75 MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default=" 76 __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")"); 77 MODULE_PARM_DESC(tmr_atboot, 78 "Watchdog is started at boot time if set to 1, default=" 79 __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT)); 80 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" 81 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 82 MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, " 83 "0 to reboot (default 0)"); 84 MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)"); 85 86 struct s3c2410_wdt { 87 struct device *dev; 88 struct clk *clock; 89 void __iomem *reg_base; 90 unsigned int count; 91 spinlock_t lock; 92 unsigned long wtcon_save; 93 unsigned long wtdat_save; 94 struct watchdog_device wdt_device; 95 struct notifier_block freq_transition; 96 }; 97 98 /* watchdog control routines */ 99 100 #define DBG(fmt, ...) \ 101 do { \ 102 if (debug) \ 103 pr_info(fmt, ##__VA_ARGS__); \ 104 } while (0) 105 106 /* functions */ 107 108 static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb) 109 { 110 return container_of(nb, struct s3c2410_wdt, freq_transition); 111 } 112 113 static int s3c2410wdt_keepalive(struct watchdog_device *wdd) 114 { 115 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); 116 117 spin_lock(&wdt->lock); 118 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); 119 spin_unlock(&wdt->lock); 120 121 return 0; 122 } 123 124 static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt) 125 { 126 unsigned long wtcon; 127 128 wtcon = readl(wdt->reg_base + S3C2410_WTCON); 129 wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); 130 writel(wtcon, wdt->reg_base + S3C2410_WTCON); 131 } 132 133 static int s3c2410wdt_stop(struct watchdog_device *wdd) 134 { 135 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); 136 137 spin_lock(&wdt->lock); 138 __s3c2410wdt_stop(wdt); 139 spin_unlock(&wdt->lock); 140 141 return 0; 142 } 143 144 static int s3c2410wdt_start(struct watchdog_device *wdd) 145 { 146 unsigned long wtcon; 147 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); 148 149 spin_lock(&wdt->lock); 150 151 __s3c2410wdt_stop(wdt); 152 153 wtcon = readl(wdt->reg_base + S3C2410_WTCON); 154 wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128; 155 156 if (soft_noboot) { 157 wtcon |= S3C2410_WTCON_INTEN; 158 wtcon &= ~S3C2410_WTCON_RSTEN; 159 } else { 160 wtcon &= ~S3C2410_WTCON_INTEN; 161 wtcon |= S3C2410_WTCON_RSTEN; 162 } 163 164 DBG("%s: count=0x%08x, wtcon=%08lx\n", 165 __func__, wdt->count, wtcon); 166 167 writel(wdt->count, wdt->reg_base + S3C2410_WTDAT); 168 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); 169 writel(wtcon, wdt->reg_base + S3C2410_WTCON); 170 spin_unlock(&wdt->lock); 171 172 return 0; 173 } 174 175 static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt) 176 { 177 return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE; 178 } 179 180 static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout) 181 { 182 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); 183 unsigned long freq = clk_get_rate(wdt->clock); 184 unsigned int count; 185 unsigned int divisor = 1; 186 unsigned long wtcon; 187 188 if (timeout < 1) 189 return -EINVAL; 190 191 freq /= 128; 192 count = timeout * freq; 193 194 DBG("%s: count=%d, timeout=%d, freq=%lu\n", 195 __func__, count, timeout, freq); 196 197 /* if the count is bigger than the watchdog register, 198 then work out what we need to do (and if) we can 199 actually make this value 200 */ 201 202 if (count >= 0x10000) { 203 for (divisor = 1; divisor <= 0x100; divisor++) { 204 if ((count / divisor) < 0x10000) 205 break; 206 } 207 208 if ((count / divisor) >= 0x10000) { 209 dev_err(wdt->dev, "timeout %d too big\n", timeout); 210 return -EINVAL; 211 } 212 } 213 214 DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n", 215 __func__, timeout, divisor, count, count/divisor); 216 217 count /= divisor; 218 wdt->count = count; 219 220 /* update the pre-scaler */ 221 wtcon = readl(wdt->reg_base + S3C2410_WTCON); 222 wtcon &= ~S3C2410_WTCON_PRESCALE_MASK; 223 wtcon |= S3C2410_WTCON_PRESCALE(divisor-1); 224 225 writel(count, wdt->reg_base + S3C2410_WTDAT); 226 writel(wtcon, wdt->reg_base + S3C2410_WTCON); 227 228 wdd->timeout = (count * divisor) / freq; 229 230 return 0; 231 } 232 233 #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE) 234 235 static const struct watchdog_info s3c2410_wdt_ident = { 236 .options = OPTIONS, 237 .firmware_version = 0, 238 .identity = "S3C2410 Watchdog", 239 }; 240 241 static struct watchdog_ops s3c2410wdt_ops = { 242 .owner = THIS_MODULE, 243 .start = s3c2410wdt_start, 244 .stop = s3c2410wdt_stop, 245 .ping = s3c2410wdt_keepalive, 246 .set_timeout = s3c2410wdt_set_heartbeat, 247 }; 248 249 static struct watchdog_device s3c2410_wdd = { 250 .info = &s3c2410_wdt_ident, 251 .ops = &s3c2410wdt_ops, 252 .timeout = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME, 253 }; 254 255 /* interrupt handler code */ 256 257 static irqreturn_t s3c2410wdt_irq(int irqno, void *param) 258 { 259 struct s3c2410_wdt *wdt = platform_get_drvdata(param); 260 261 dev_info(wdt->dev, "watchdog timer expired (irq)\n"); 262 263 s3c2410wdt_keepalive(&wdt->wdt_device); 264 return IRQ_HANDLED; 265 } 266 267 #ifdef CONFIG_CPU_FREQ 268 269 static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb, 270 unsigned long val, void *data) 271 { 272 int ret; 273 struct s3c2410_wdt *wdt = freq_to_wdt(nb); 274 275 if (!s3c2410wdt_is_running(wdt)) 276 goto done; 277 278 if (val == CPUFREQ_PRECHANGE) { 279 /* To ensure that over the change we don't cause the 280 * watchdog to trigger, we perform an keep-alive if 281 * the watchdog is running. 282 */ 283 284 s3c2410wdt_keepalive(&wdt->wdt_device); 285 } else if (val == CPUFREQ_POSTCHANGE) { 286 s3c2410wdt_stop(&wdt->wdt_device); 287 288 ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, 289 wdt->wdt_device.timeout); 290 291 if (ret >= 0) 292 s3c2410wdt_start(&wdt->wdt_device); 293 else 294 goto err; 295 } 296 297 done: 298 return 0; 299 300 err: 301 dev_err(wdt->dev, "cannot set new value for timeout %d\n", 302 wdt->wdt_device.timeout); 303 return ret; 304 } 305 306 static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt) 307 { 308 wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition; 309 310 return cpufreq_register_notifier(&wdt->freq_transition, 311 CPUFREQ_TRANSITION_NOTIFIER); 312 } 313 314 static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt) 315 { 316 wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition; 317 318 cpufreq_unregister_notifier(&wdt->freq_transition, 319 CPUFREQ_TRANSITION_NOTIFIER); 320 } 321 322 #else 323 324 static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt) 325 { 326 return 0; 327 } 328 329 static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt) 330 { 331 } 332 #endif 333 334 static int s3c2410wdt_probe(struct platform_device *pdev) 335 { 336 struct device *dev; 337 struct s3c2410_wdt *wdt; 338 struct resource *wdt_mem; 339 struct resource *wdt_irq; 340 unsigned int wtcon; 341 int started = 0; 342 int ret; 343 344 DBG("%s: probe=%p\n", __func__, pdev); 345 346 dev = &pdev->dev; 347 348 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); 349 if (!wdt) 350 return -ENOMEM; 351 352 wdt->dev = &pdev->dev; 353 spin_lock_init(&wdt->lock); 354 wdt->wdt_device = s3c2410_wdd; 355 356 wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 357 if (wdt_irq == NULL) { 358 dev_err(dev, "no irq resource specified\n"); 359 ret = -ENOENT; 360 goto err; 361 } 362 363 /* get the memory region for the watchdog timer */ 364 wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 365 wdt->reg_base = devm_ioremap_resource(dev, wdt_mem); 366 if (IS_ERR(wdt->reg_base)) { 367 ret = PTR_ERR(wdt->reg_base); 368 goto err; 369 } 370 371 DBG("probe: mapped reg_base=%p\n", wdt->reg_base); 372 373 wdt->clock = devm_clk_get(dev, "watchdog"); 374 if (IS_ERR(wdt->clock)) { 375 dev_err(dev, "failed to find watchdog clock source\n"); 376 ret = PTR_ERR(wdt->clock); 377 goto err; 378 } 379 380 clk_prepare_enable(wdt->clock); 381 382 ret = s3c2410wdt_cpufreq_register(wdt); 383 if (ret < 0) { 384 dev_err(dev, "failed to register cpufreq\n"); 385 goto err_clk; 386 } 387 388 watchdog_set_drvdata(&wdt->wdt_device, wdt); 389 390 /* see if we can actually set the requested timer margin, and if 391 * not, try the default value */ 392 393 watchdog_init_timeout(&wdt->wdt_device, tmr_margin, &pdev->dev); 394 ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, 395 wdt->wdt_device.timeout); 396 if (ret) { 397 started = s3c2410wdt_set_heartbeat(&wdt->wdt_device, 398 CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); 399 400 if (started == 0) 401 dev_info(dev, 402 "tmr_margin value out of range, default %d used\n", 403 CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); 404 else 405 dev_info(dev, "default timer value is out of range, " 406 "cannot start\n"); 407 } 408 409 ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0, 410 pdev->name, pdev); 411 if (ret != 0) { 412 dev_err(dev, "failed to install irq (%d)\n", ret); 413 goto err_cpufreq; 414 } 415 416 watchdog_set_nowayout(&wdt->wdt_device, nowayout); 417 418 ret = watchdog_register_device(&wdt->wdt_device); 419 if (ret) { 420 dev_err(dev, "cannot register watchdog (%d)\n", ret); 421 goto err_cpufreq; 422 } 423 424 if (tmr_atboot && started == 0) { 425 dev_info(dev, "starting watchdog timer\n"); 426 s3c2410wdt_start(&wdt->wdt_device); 427 } else if (!tmr_atboot) { 428 /* if we're not enabling the watchdog, then ensure it is 429 * disabled if it has been left running from the bootloader 430 * or other source */ 431 432 s3c2410wdt_stop(&wdt->wdt_device); 433 } 434 435 platform_set_drvdata(pdev, wdt); 436 437 /* print out a statement of readiness */ 438 439 wtcon = readl(wdt->reg_base + S3C2410_WTCON); 440 441 dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n", 442 (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in", 443 (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis", 444 (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis"); 445 446 return 0; 447 448 err_cpufreq: 449 s3c2410wdt_cpufreq_deregister(wdt); 450 451 err_clk: 452 clk_disable_unprepare(wdt->clock); 453 wdt->clock = NULL; 454 455 err: 456 return ret; 457 } 458 459 static int s3c2410wdt_remove(struct platform_device *dev) 460 { 461 struct s3c2410_wdt *wdt = platform_get_drvdata(dev); 462 463 watchdog_unregister_device(&wdt->wdt_device); 464 465 s3c2410wdt_cpufreq_deregister(wdt); 466 467 clk_disable_unprepare(wdt->clock); 468 wdt->clock = NULL; 469 470 return 0; 471 } 472 473 static void s3c2410wdt_shutdown(struct platform_device *dev) 474 { 475 struct s3c2410_wdt *wdt = platform_get_drvdata(dev); 476 477 s3c2410wdt_stop(&wdt->wdt_device); 478 } 479 480 #ifdef CONFIG_PM_SLEEP 481 482 static int s3c2410wdt_suspend(struct device *dev) 483 { 484 struct s3c2410_wdt *wdt = dev_get_drvdata(dev); 485 486 /* Save watchdog state, and turn it off. */ 487 wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON); 488 wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT); 489 490 /* Note that WTCNT doesn't need to be saved. */ 491 s3c2410wdt_stop(&wdt->wdt_device); 492 493 return 0; 494 } 495 496 static int s3c2410wdt_resume(struct device *dev) 497 { 498 struct s3c2410_wdt *wdt = dev_get_drvdata(dev); 499 500 /* Restore watchdog state. */ 501 writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT); 502 writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */ 503 writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON); 504 505 dev_info(dev, "watchdog %sabled\n", 506 (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis"); 507 508 return 0; 509 } 510 #endif 511 512 static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend, 513 s3c2410wdt_resume); 514 515 #ifdef CONFIG_OF 516 static const struct of_device_id s3c2410_wdt_match[] = { 517 { .compatible = "samsung,s3c2410-wdt" }, 518 {}, 519 }; 520 MODULE_DEVICE_TABLE(of, s3c2410_wdt_match); 521 #endif 522 523 static struct platform_driver s3c2410wdt_driver = { 524 .probe = s3c2410wdt_probe, 525 .remove = s3c2410wdt_remove, 526 .shutdown = s3c2410wdt_shutdown, 527 .driver = { 528 .owner = THIS_MODULE, 529 .name = "s3c2410-wdt", 530 .pm = &s3c2410wdt_pm_ops, 531 .of_match_table = of_match_ptr(s3c2410_wdt_match), 532 }, 533 }; 534 535 module_platform_driver(s3c2410wdt_driver); 536 537 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, " 538 "Dimitry Andric <dimitry.andric@tomtom.com>"); 539 MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver"); 540 MODULE_LICENSE("GPL"); 541 MODULE_ALIAS("platform:s3c2410-wdt"); 542