1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2004 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * 6 * S3C2410 Watchdog Timer Support 7 * 8 * Based on, softdog.c by Alan Cox, 9 * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/types.h> 15 #include <linux/timer.h> 16 #include <linux/watchdog.h> 17 #include <linux/platform_device.h> 18 #include <linux/interrupt.h> 19 #include <linux/clk.h> 20 #include <linux/uaccess.h> 21 #include <linux/io.h> 22 #include <linux/cpufreq.h> 23 #include <linux/slab.h> 24 #include <linux/err.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 #include <linux/mfd/syscon.h> 28 #include <linux/regmap.h> 29 #include <linux/delay.h> 30 31 #define S3C2410_WTCON 0x00 32 #define S3C2410_WTDAT 0x04 33 #define S3C2410_WTCNT 0x08 34 #define S3C2410_WTCLRINT 0x0c 35 36 #define S3C2410_WTCNT_MAXCNT 0xffff 37 38 #define S3C2410_WTCON_RSTEN (1 << 0) 39 #define S3C2410_WTCON_INTEN (1 << 2) 40 #define S3C2410_WTCON_ENABLE (1 << 5) 41 42 #define S3C2410_WTCON_DIV16 (0 << 3) 43 #define S3C2410_WTCON_DIV32 (1 << 3) 44 #define S3C2410_WTCON_DIV64 (2 << 3) 45 #define S3C2410_WTCON_DIV128 (3 << 3) 46 47 #define S3C2410_WTCON_MAXDIV 0x80 48 49 #define S3C2410_WTCON_PRESCALE(x) ((x) << 8) 50 #define S3C2410_WTCON_PRESCALE_MASK (0xff << 8) 51 #define S3C2410_WTCON_PRESCALE_MAX 0xff 52 53 #define S3C2410_WATCHDOG_ATBOOT (0) 54 #define S3C2410_WATCHDOG_DEFAULT_TIME (15) 55 56 #define EXYNOS5_RST_STAT_REG_OFFSET 0x0404 57 #define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408 58 #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c 59 #define EXYNOS850_CLUSTER0_NONCPU_OUT 0x1220 60 #define EXYNOS850_CLUSTER0_NONCPU_INT_EN 0x1244 61 #define EXYNOS850_CLUSTER1_NONCPU_OUT 0x1620 62 #define EXYNOS850_CLUSTER1_NONCPU_INT_EN 0x1644 63 #define EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT 0x1520 64 #define EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN 0x1544 65 66 #define EXYNOS850_CLUSTER0_WDTRESET_BIT 24 67 #define EXYNOS850_CLUSTER1_WDTRESET_BIT 23 68 #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25 69 #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24 70 71 /** 72 * DOC: Quirk flags for different Samsung watchdog IP-cores 73 * 74 * This driver supports multiple Samsung SoCs, each of which might have 75 * different set of registers and features supported. As watchdog block 76 * sometimes requires modifying PMU registers for proper functioning, register 77 * differences in both watchdog and PMU IP-cores should be accounted for. Quirk 78 * flags described below serve the purpose of telling the driver about mentioned 79 * SoC traits, and can be specified in driver data for each particular supported 80 * device. 81 * 82 * %QUIRK_HAS_WTCLRINT_REG: Watchdog block has WTCLRINT register. It's used to 83 * clear the interrupt once the interrupt service routine is complete. It's 84 * write-only, writing any values to this register clears the interrupt, but 85 * reading is not permitted. 86 * 87 * %QUIRK_HAS_PMU_MASK_RESET: PMU block has the register for disabling/enabling 88 * WDT reset request. On old SoCs it's usually called MASK_WDT_RESET_REQUEST, 89 * new SoCs have CLUSTERx_NONCPU_INT_EN register, which 'mask_bit' value is 90 * inverted compared to the former one. 91 * 92 * %QUIRK_HAS_PMU_RST_STAT: PMU block has RST_STAT (reset status) register, 93 * which contains bits indicating the reason for most recent CPU reset. If 94 * present, driver will use this register to check if previous reboot was due to 95 * watchdog timer reset. 96 * 97 * %QUIRK_HAS_PMU_AUTO_DISABLE: PMU block has AUTOMATIC_WDT_RESET_DISABLE 98 * register. If 'mask_bit' bit is set, PMU will disable WDT reset when 99 * corresponding processor is in reset state. 100 * 101 * %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. CLUSTERx_NONCPU_OUT) 102 * with "watchdog counter enable" bit. That bit should be set to make watchdog 103 * counter running. 104 */ 105 #define QUIRK_HAS_WTCLRINT_REG (1 << 0) 106 #define QUIRK_HAS_PMU_MASK_RESET (1 << 1) 107 #define QUIRK_HAS_PMU_RST_STAT (1 << 2) 108 #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) 109 #define QUIRK_HAS_PMU_CNT_EN (1 << 4) 110 111 /* These quirks require that we have a PMU register map */ 112 #define QUIRKS_HAVE_PMUREG \ 113 (QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_RST_STAT | \ 114 QUIRK_HAS_PMU_AUTO_DISABLE | QUIRK_HAS_PMU_CNT_EN) 115 116 static bool nowayout = WATCHDOG_NOWAYOUT; 117 static int tmr_margin; 118 static int tmr_atboot = S3C2410_WATCHDOG_ATBOOT; 119 static int soft_noboot; 120 121 module_param(tmr_margin, int, 0); 122 module_param(tmr_atboot, int, 0); 123 module_param(nowayout, bool, 0); 124 module_param(soft_noboot, int, 0); 125 126 MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default=" 127 __MODULE_STRING(S3C2410_WATCHDOG_DEFAULT_TIME) ")"); 128 MODULE_PARM_DESC(tmr_atboot, 129 "Watchdog is started at boot time if set to 1, default=" 130 __MODULE_STRING(S3C2410_WATCHDOG_ATBOOT)); 131 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" 132 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 133 MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default 0)"); 134 135 /** 136 * struct s3c2410_wdt_variant - Per-variant config data 137 * 138 * @disable_reg: Offset in pmureg for the register that disables the watchdog 139 * timer reset functionality. 140 * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog 141 * timer reset functionality. 142 * @mask_reset_inv: If set, mask_reset_reg value will have inverted meaning. 143 * @mask_bit: Bit number for the watchdog timer in the disable register and the 144 * mask reset register. 145 * @rst_stat_reg: Offset in pmureg for the register that has the reset status. 146 * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog 147 * reset. 148 * @cnt_en_reg: Offset in pmureg for the register that enables WDT counter. 149 * @cnt_en_bit: Bit number for "watchdog counter enable" in cnt_en register. 150 * @quirks: A bitfield of quirks. 151 */ 152 153 struct s3c2410_wdt_variant { 154 int disable_reg; 155 int mask_reset_reg; 156 bool mask_reset_inv; 157 int mask_bit; 158 int rst_stat_reg; 159 int rst_stat_bit; 160 int cnt_en_reg; 161 int cnt_en_bit; 162 u32 quirks; 163 }; 164 165 struct s3c2410_wdt { 166 struct device *dev; 167 struct clk *bus_clk; /* for register interface (PCLK) */ 168 struct clk *src_clk; /* for WDT counter */ 169 void __iomem *reg_base; 170 unsigned int count; 171 spinlock_t lock; 172 unsigned long wtcon_save; 173 unsigned long wtdat_save; 174 struct watchdog_device wdt_device; 175 struct notifier_block freq_transition; 176 const struct s3c2410_wdt_variant *drv_data; 177 struct regmap *pmureg; 178 }; 179 180 static const struct s3c2410_wdt_variant drv_data_s3c2410 = { 181 .quirks = 0 182 }; 183 184 #ifdef CONFIG_OF 185 static const struct s3c2410_wdt_variant drv_data_s3c6410 = { 186 .quirks = QUIRK_HAS_WTCLRINT_REG, 187 }; 188 189 static const struct s3c2410_wdt_variant drv_data_exynos5250 = { 190 .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, 191 .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, 192 .mask_bit = 20, 193 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, 194 .rst_stat_bit = 20, 195 .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \ 196 QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE, 197 }; 198 199 static const struct s3c2410_wdt_variant drv_data_exynos5420 = { 200 .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, 201 .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, 202 .mask_bit = 0, 203 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, 204 .rst_stat_bit = 9, 205 .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \ 206 QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE, 207 }; 208 209 static const struct s3c2410_wdt_variant drv_data_exynos7 = { 210 .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, 211 .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, 212 .mask_bit = 23, 213 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, 214 .rst_stat_bit = 23, /* A57 WDTRESET */ 215 .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \ 216 QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE, 217 }; 218 219 static const struct s3c2410_wdt_variant drv_data_exynos850_cl0 = { 220 .mask_reset_reg = EXYNOS850_CLUSTER0_NONCPU_INT_EN, 221 .mask_bit = 2, 222 .mask_reset_inv = true, 223 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, 224 .rst_stat_bit = EXYNOS850_CLUSTER0_WDTRESET_BIT, 225 .cnt_en_reg = EXYNOS850_CLUSTER0_NONCPU_OUT, 226 .cnt_en_bit = 7, 227 .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \ 228 QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, 229 }; 230 231 static const struct s3c2410_wdt_variant drv_data_exynos850_cl1 = { 232 .mask_reset_reg = EXYNOS850_CLUSTER1_NONCPU_INT_EN, 233 .mask_bit = 2, 234 .mask_reset_inv = true, 235 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, 236 .rst_stat_bit = EXYNOS850_CLUSTER1_WDTRESET_BIT, 237 .cnt_en_reg = EXYNOS850_CLUSTER1_NONCPU_OUT, 238 .cnt_en_bit = 7, 239 .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \ 240 QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, 241 }; 242 243 static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl0 = { 244 .mask_reset_reg = EXYNOS850_CLUSTER0_NONCPU_INT_EN, 245 .mask_bit = 2, 246 .mask_reset_inv = true, 247 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, 248 .rst_stat_bit = EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT, 249 .cnt_en_reg = EXYNOS850_CLUSTER0_NONCPU_OUT, 250 .cnt_en_bit = 7, 251 .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | 252 QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, 253 }; 254 255 static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = { 256 .mask_reset_reg = EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN, 257 .mask_bit = 2, 258 .mask_reset_inv = true, 259 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, 260 .rst_stat_bit = EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT, 261 .cnt_en_reg = EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT, 262 .cnt_en_bit = 7, 263 .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | 264 QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, 265 }; 266 267 static const struct of_device_id s3c2410_wdt_match[] = { 268 { .compatible = "samsung,s3c2410-wdt", 269 .data = &drv_data_s3c2410 }, 270 { .compatible = "samsung,s3c6410-wdt", 271 .data = &drv_data_s3c6410 }, 272 { .compatible = "samsung,exynos5250-wdt", 273 .data = &drv_data_exynos5250 }, 274 { .compatible = "samsung,exynos5420-wdt", 275 .data = &drv_data_exynos5420 }, 276 { .compatible = "samsung,exynos7-wdt", 277 .data = &drv_data_exynos7 }, 278 { .compatible = "samsung,exynos850-wdt", 279 .data = &drv_data_exynos850_cl0 }, 280 { .compatible = "samsung,exynosautov9-wdt", 281 .data = &drv_data_exynosautov9_cl0 }, 282 {}, 283 }; 284 MODULE_DEVICE_TABLE(of, s3c2410_wdt_match); 285 #endif 286 287 static const struct platform_device_id s3c2410_wdt_ids[] = { 288 { 289 .name = "s3c2410-wdt", 290 .driver_data = (unsigned long)&drv_data_s3c2410, 291 }, 292 {} 293 }; 294 MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids); 295 296 /* functions */ 297 298 static inline unsigned long s3c2410wdt_get_freq(struct s3c2410_wdt *wdt) 299 { 300 return clk_get_rate(wdt->src_clk ? wdt->src_clk : wdt->bus_clk); 301 } 302 303 static inline unsigned int s3c2410wdt_max_timeout(struct s3c2410_wdt *wdt) 304 { 305 const unsigned long freq = s3c2410wdt_get_freq(wdt); 306 307 return S3C2410_WTCNT_MAXCNT / (freq / (S3C2410_WTCON_PRESCALE_MAX + 1) 308 / S3C2410_WTCON_MAXDIV); 309 } 310 311 static int s3c2410wdt_disable_wdt_reset(struct s3c2410_wdt *wdt, bool mask) 312 { 313 const u32 mask_val = BIT(wdt->drv_data->mask_bit); 314 const u32 val = mask ? mask_val : 0; 315 int ret; 316 317 ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->disable_reg, 318 mask_val, val); 319 if (ret < 0) 320 dev_err(wdt->dev, "failed to update reg(%d)\n", ret); 321 322 return ret; 323 } 324 325 static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask) 326 { 327 const u32 mask_val = BIT(wdt->drv_data->mask_bit); 328 const bool val_inv = wdt->drv_data->mask_reset_inv; 329 const u32 val = (mask ^ val_inv) ? mask_val : 0; 330 int ret; 331 332 ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->mask_reset_reg, 333 mask_val, val); 334 if (ret < 0) 335 dev_err(wdt->dev, "failed to update reg(%d)\n", ret); 336 337 return ret; 338 } 339 340 static int s3c2410wdt_enable_counter(struct s3c2410_wdt *wdt, bool en) 341 { 342 const u32 mask_val = BIT(wdt->drv_data->cnt_en_bit); 343 const u32 val = en ? mask_val : 0; 344 int ret; 345 346 ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->cnt_en_reg, 347 mask_val, val); 348 if (ret < 0) 349 dev_err(wdt->dev, "failed to update reg(%d)\n", ret); 350 351 return ret; 352 } 353 354 static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en) 355 { 356 int ret; 357 358 if (wdt->drv_data->quirks & QUIRK_HAS_PMU_AUTO_DISABLE) { 359 ret = s3c2410wdt_disable_wdt_reset(wdt, !en); 360 if (ret < 0) 361 return ret; 362 } 363 364 if (wdt->drv_data->quirks & QUIRK_HAS_PMU_MASK_RESET) { 365 ret = s3c2410wdt_mask_wdt_reset(wdt, !en); 366 if (ret < 0) 367 return ret; 368 } 369 370 if (wdt->drv_data->quirks & QUIRK_HAS_PMU_CNT_EN) { 371 ret = s3c2410wdt_enable_counter(wdt, en); 372 if (ret < 0) 373 return ret; 374 } 375 376 return 0; 377 } 378 379 static int s3c2410wdt_keepalive(struct watchdog_device *wdd) 380 { 381 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); 382 383 spin_lock(&wdt->lock); 384 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); 385 spin_unlock(&wdt->lock); 386 387 return 0; 388 } 389 390 static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt) 391 { 392 unsigned long wtcon; 393 394 wtcon = readl(wdt->reg_base + S3C2410_WTCON); 395 wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); 396 writel(wtcon, wdt->reg_base + S3C2410_WTCON); 397 } 398 399 static int s3c2410wdt_stop(struct watchdog_device *wdd) 400 { 401 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); 402 403 spin_lock(&wdt->lock); 404 __s3c2410wdt_stop(wdt); 405 spin_unlock(&wdt->lock); 406 407 return 0; 408 } 409 410 static int s3c2410wdt_start(struct watchdog_device *wdd) 411 { 412 unsigned long wtcon; 413 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); 414 415 spin_lock(&wdt->lock); 416 417 __s3c2410wdt_stop(wdt); 418 419 wtcon = readl(wdt->reg_base + S3C2410_WTCON); 420 wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128; 421 422 if (soft_noboot) { 423 wtcon |= S3C2410_WTCON_INTEN; 424 wtcon &= ~S3C2410_WTCON_RSTEN; 425 } else { 426 wtcon &= ~S3C2410_WTCON_INTEN; 427 wtcon |= S3C2410_WTCON_RSTEN; 428 } 429 430 dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n", 431 wdt->count, wtcon); 432 433 writel(wdt->count, wdt->reg_base + S3C2410_WTDAT); 434 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); 435 writel(wtcon, wdt->reg_base + S3C2410_WTCON); 436 spin_unlock(&wdt->lock); 437 438 return 0; 439 } 440 441 static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, 442 unsigned int timeout) 443 { 444 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); 445 unsigned long freq = s3c2410wdt_get_freq(wdt); 446 unsigned int count; 447 unsigned int divisor = 1; 448 unsigned long wtcon; 449 450 if (timeout < 1) 451 return -EINVAL; 452 453 freq = DIV_ROUND_UP(freq, 128); 454 count = timeout * freq; 455 456 dev_dbg(wdt->dev, "Heartbeat: count=%d, timeout=%d, freq=%lu\n", 457 count, timeout, freq); 458 459 /* if the count is bigger than the watchdog register, 460 then work out what we need to do (and if) we can 461 actually make this value 462 */ 463 464 if (count >= 0x10000) { 465 divisor = DIV_ROUND_UP(count, 0xffff); 466 467 if (divisor > 0x100) { 468 dev_err(wdt->dev, "timeout %d too big\n", timeout); 469 return -EINVAL; 470 } 471 } 472 473 dev_dbg(wdt->dev, "Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n", 474 timeout, divisor, count, DIV_ROUND_UP(count, divisor)); 475 476 count = DIV_ROUND_UP(count, divisor); 477 wdt->count = count; 478 479 /* update the pre-scaler */ 480 wtcon = readl(wdt->reg_base + S3C2410_WTCON); 481 wtcon &= ~S3C2410_WTCON_PRESCALE_MASK; 482 wtcon |= S3C2410_WTCON_PRESCALE(divisor-1); 483 484 writel(count, wdt->reg_base + S3C2410_WTDAT); 485 writel(wtcon, wdt->reg_base + S3C2410_WTCON); 486 487 wdd->timeout = (count * divisor) / freq; 488 489 return 0; 490 } 491 492 static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action, 493 void *data) 494 { 495 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); 496 void __iomem *wdt_base = wdt->reg_base; 497 498 /* disable watchdog, to be safe */ 499 writel(0, wdt_base + S3C2410_WTCON); 500 501 /* put initial values into count and data */ 502 writel(0x80, wdt_base + S3C2410_WTCNT); 503 writel(0x80, wdt_base + S3C2410_WTDAT); 504 505 /* set the watchdog to go and reset... */ 506 writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 | 507 S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20), 508 wdt_base + S3C2410_WTCON); 509 510 /* wait for reset to assert... */ 511 mdelay(500); 512 513 return 0; 514 } 515 516 #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE) 517 518 static const struct watchdog_info s3c2410_wdt_ident = { 519 .options = OPTIONS, 520 .firmware_version = 0, 521 .identity = "S3C2410 Watchdog", 522 }; 523 524 static const struct watchdog_ops s3c2410wdt_ops = { 525 .owner = THIS_MODULE, 526 .start = s3c2410wdt_start, 527 .stop = s3c2410wdt_stop, 528 .ping = s3c2410wdt_keepalive, 529 .set_timeout = s3c2410wdt_set_heartbeat, 530 .restart = s3c2410wdt_restart, 531 }; 532 533 static const struct watchdog_device s3c2410_wdd = { 534 .info = &s3c2410_wdt_ident, 535 .ops = &s3c2410wdt_ops, 536 .timeout = S3C2410_WATCHDOG_DEFAULT_TIME, 537 }; 538 539 /* interrupt handler code */ 540 541 static irqreturn_t s3c2410wdt_irq(int irqno, void *param) 542 { 543 struct s3c2410_wdt *wdt = platform_get_drvdata(param); 544 545 dev_info(wdt->dev, "watchdog timer expired (irq)\n"); 546 547 s3c2410wdt_keepalive(&wdt->wdt_device); 548 549 if (wdt->drv_data->quirks & QUIRK_HAS_WTCLRINT_REG) 550 writel(0x1, wdt->reg_base + S3C2410_WTCLRINT); 551 552 return IRQ_HANDLED; 553 } 554 555 static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt) 556 { 557 unsigned int rst_stat; 558 int ret; 559 560 if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_RST_STAT)) 561 return 0; 562 563 ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat); 564 if (ret) 565 dev_warn(wdt->dev, "Couldn't get RST_STAT register\n"); 566 else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit)) 567 return WDIOF_CARDRESET; 568 569 return 0; 570 } 571 572 static inline int 573 s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt) 574 { 575 const struct s3c2410_wdt_variant *variant; 576 struct device *dev = &pdev->dev; 577 578 variant = of_device_get_match_data(dev); 579 if (!variant) { 580 /* Device matched by platform_device_id */ 581 variant = (struct s3c2410_wdt_variant *) 582 platform_get_device_id(pdev)->driver_data; 583 } 584 585 #ifdef CONFIG_OF 586 /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */ 587 if (variant == &drv_data_exynos850_cl0 || 588 variant == &drv_data_exynosautov9_cl0) { 589 u32 index; 590 int err; 591 592 err = of_property_read_u32(dev->of_node, 593 "samsung,cluster-index", &index); 594 if (err) 595 return dev_err_probe(dev, -EINVAL, "failed to get cluster index\n"); 596 597 switch (index) { 598 case 0: 599 break; 600 case 1: 601 variant = (variant == &drv_data_exynos850_cl0) ? 602 &drv_data_exynos850_cl1 : 603 &drv_data_exynosautov9_cl1; 604 break; 605 default: 606 return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index); 607 } 608 } 609 #endif 610 611 wdt->drv_data = variant; 612 return 0; 613 } 614 615 static void s3c2410wdt_wdt_disable_action(void *data) 616 { 617 s3c2410wdt_enable(data, false); 618 } 619 620 static int s3c2410wdt_probe(struct platform_device *pdev) 621 { 622 struct device *dev = &pdev->dev; 623 struct s3c2410_wdt *wdt; 624 unsigned int wtcon; 625 int wdt_irq; 626 int ret; 627 628 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); 629 if (!wdt) 630 return -ENOMEM; 631 632 wdt->dev = dev; 633 spin_lock_init(&wdt->lock); 634 wdt->wdt_device = s3c2410_wdd; 635 636 ret = s3c2410_get_wdt_drv_data(pdev, wdt); 637 if (ret) 638 return ret; 639 640 if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) { 641 wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, 642 "samsung,syscon-phandle"); 643 if (IS_ERR(wdt->pmureg)) 644 return dev_err_probe(dev, PTR_ERR(wdt->pmureg), 645 "syscon regmap lookup failed.\n"); 646 } 647 648 wdt_irq = platform_get_irq(pdev, 0); 649 if (wdt_irq < 0) 650 return wdt_irq; 651 652 /* get the memory region for the watchdog timer */ 653 wdt->reg_base = devm_platform_ioremap_resource(pdev, 0); 654 if (IS_ERR(wdt->reg_base)) 655 return PTR_ERR(wdt->reg_base); 656 657 wdt->bus_clk = devm_clk_get_enabled(dev, "watchdog"); 658 if (IS_ERR(wdt->bus_clk)) 659 return dev_err_probe(dev, PTR_ERR(wdt->bus_clk), "failed to get bus clock\n"); 660 661 /* 662 * "watchdog_src" clock is optional; if it's not present -- just skip it 663 * and use "watchdog" clock as both bus and source clock. 664 */ 665 wdt->src_clk = devm_clk_get_optional_enabled(dev, "watchdog_src"); 666 if (IS_ERR(wdt->src_clk)) 667 return dev_err_probe(dev, PTR_ERR(wdt->src_clk), "failed to get source clock\n"); 668 669 wdt->wdt_device.min_timeout = 1; 670 wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt); 671 672 watchdog_set_drvdata(&wdt->wdt_device, wdt); 673 674 /* see if we can actually set the requested timer margin, and if 675 * not, try the default value */ 676 677 watchdog_init_timeout(&wdt->wdt_device, tmr_margin, dev); 678 ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, 679 wdt->wdt_device.timeout); 680 if (ret) { 681 ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, 682 S3C2410_WATCHDOG_DEFAULT_TIME); 683 if (ret == 0) 684 dev_warn(dev, "tmr_margin value out of range, default %d used\n", 685 S3C2410_WATCHDOG_DEFAULT_TIME); 686 else 687 return dev_err_probe(dev, ret, "failed to use default timeout\n"); 688 } 689 690 ret = devm_request_irq(dev, wdt_irq, s3c2410wdt_irq, 0, 691 pdev->name, pdev); 692 if (ret != 0) 693 return dev_err_probe(dev, ret, "failed to install irq (%d)\n", ret); 694 695 watchdog_set_nowayout(&wdt->wdt_device, nowayout); 696 watchdog_set_restart_priority(&wdt->wdt_device, 128); 697 698 wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); 699 wdt->wdt_device.parent = dev; 700 701 /* 702 * If "tmr_atboot" param is non-zero, start the watchdog right now. Also 703 * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog. 704 * 705 * If we're not enabling the watchdog, then ensure it is disabled if it 706 * has been left running from the bootloader or other source. 707 */ 708 if (tmr_atboot) { 709 dev_info(dev, "starting watchdog timer\n"); 710 s3c2410wdt_start(&wdt->wdt_device); 711 set_bit(WDOG_HW_RUNNING, &wdt->wdt_device.status); 712 } else { 713 s3c2410wdt_stop(&wdt->wdt_device); 714 } 715 716 ret = devm_watchdog_register_device(dev, &wdt->wdt_device); 717 if (ret) 718 return ret; 719 720 ret = s3c2410wdt_enable(wdt, true); 721 if (ret < 0) 722 return ret; 723 724 ret = devm_add_action_or_reset(dev, s3c2410wdt_wdt_disable_action, wdt); 725 if (ret) 726 return ret; 727 728 platform_set_drvdata(pdev, wdt); 729 730 /* print out a statement of readiness */ 731 732 wtcon = readl(wdt->reg_base + S3C2410_WTCON); 733 734 dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n", 735 (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in", 736 (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis", 737 (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis"); 738 739 return 0; 740 } 741 742 static void s3c2410wdt_shutdown(struct platform_device *dev) 743 { 744 struct s3c2410_wdt *wdt = platform_get_drvdata(dev); 745 746 s3c2410wdt_enable(wdt, false); 747 s3c2410wdt_stop(&wdt->wdt_device); 748 } 749 750 static int s3c2410wdt_suspend(struct device *dev) 751 { 752 int ret; 753 struct s3c2410_wdt *wdt = dev_get_drvdata(dev); 754 755 /* Save watchdog state, and turn it off. */ 756 wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON); 757 wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT); 758 759 ret = s3c2410wdt_enable(wdt, false); 760 if (ret < 0) 761 return ret; 762 763 /* Note that WTCNT doesn't need to be saved. */ 764 s3c2410wdt_stop(&wdt->wdt_device); 765 766 return 0; 767 } 768 769 static int s3c2410wdt_resume(struct device *dev) 770 { 771 int ret; 772 struct s3c2410_wdt *wdt = dev_get_drvdata(dev); 773 774 /* Restore watchdog state. */ 775 writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT); 776 writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */ 777 writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON); 778 779 ret = s3c2410wdt_enable(wdt, true); 780 if (ret < 0) 781 return ret; 782 783 dev_info(dev, "watchdog %sabled\n", 784 (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis"); 785 786 return 0; 787 } 788 789 static DEFINE_SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, 790 s3c2410wdt_suspend, s3c2410wdt_resume); 791 792 static struct platform_driver s3c2410wdt_driver = { 793 .probe = s3c2410wdt_probe, 794 .shutdown = s3c2410wdt_shutdown, 795 .id_table = s3c2410_wdt_ids, 796 .driver = { 797 .name = "s3c2410-wdt", 798 .pm = pm_sleep_ptr(&s3c2410wdt_pm_ops), 799 .of_match_table = of_match_ptr(s3c2410_wdt_match), 800 }, 801 }; 802 803 module_platform_driver(s3c2410wdt_driver); 804 805 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Dimitry Andric <dimitry.andric@tomtom.com>"); 806 MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver"); 807 MODULE_LICENSE("GPL"); 808