1 /* Copyright (c) 2014, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 */ 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/io.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/platform_device.h> 20 #include <linux/watchdog.h> 21 #include <linux/of_device.h> 22 23 enum wdt_reg { 24 WDT_RST, 25 WDT_EN, 26 WDT_STS, 27 WDT_BARK_TIME, 28 WDT_BITE_TIME, 29 }; 30 31 static const u32 reg_offset_data_apcs_tmr[] = { 32 [WDT_RST] = 0x38, 33 [WDT_EN] = 0x40, 34 [WDT_STS] = 0x44, 35 [WDT_BARK_TIME] = 0x4C, 36 [WDT_BITE_TIME] = 0x5C, 37 }; 38 39 static const u32 reg_offset_data_kpss[] = { 40 [WDT_RST] = 0x4, 41 [WDT_EN] = 0x8, 42 [WDT_STS] = 0xC, 43 [WDT_BARK_TIME] = 0x10, 44 [WDT_BITE_TIME] = 0x14, 45 }; 46 47 struct qcom_wdt { 48 struct watchdog_device wdd; 49 struct clk *clk; 50 unsigned long rate; 51 void __iomem *base; 52 const u32 *layout; 53 }; 54 55 static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg) 56 { 57 return wdt->base + wdt->layout[reg]; 58 } 59 60 static inline 61 struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd) 62 { 63 return container_of(wdd, struct qcom_wdt, wdd); 64 } 65 66 static int qcom_wdt_start(struct watchdog_device *wdd) 67 { 68 struct qcom_wdt *wdt = to_qcom_wdt(wdd); 69 70 writel(0, wdt_addr(wdt, WDT_EN)); 71 writel(1, wdt_addr(wdt, WDT_RST)); 72 writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME)); 73 writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME)); 74 writel(1, wdt_addr(wdt, WDT_EN)); 75 return 0; 76 } 77 78 static int qcom_wdt_stop(struct watchdog_device *wdd) 79 { 80 struct qcom_wdt *wdt = to_qcom_wdt(wdd); 81 82 writel(0, wdt_addr(wdt, WDT_EN)); 83 return 0; 84 } 85 86 static int qcom_wdt_ping(struct watchdog_device *wdd) 87 { 88 struct qcom_wdt *wdt = to_qcom_wdt(wdd); 89 90 writel(1, wdt_addr(wdt, WDT_RST)); 91 return 0; 92 } 93 94 static int qcom_wdt_set_timeout(struct watchdog_device *wdd, 95 unsigned int timeout) 96 { 97 wdd->timeout = timeout; 98 return qcom_wdt_start(wdd); 99 } 100 101 static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action, 102 void *data) 103 { 104 struct qcom_wdt *wdt = to_qcom_wdt(wdd); 105 u32 timeout; 106 107 /* 108 * Trigger watchdog bite: 109 * Setup BITE_TIME to be 128ms, and enable WDT. 110 */ 111 timeout = 128 * wdt->rate / 1000; 112 113 writel(0, wdt_addr(wdt, WDT_EN)); 114 writel(1, wdt_addr(wdt, WDT_RST)); 115 writel(timeout, wdt_addr(wdt, WDT_BARK_TIME)); 116 writel(timeout, wdt_addr(wdt, WDT_BITE_TIME)); 117 writel(1, wdt_addr(wdt, WDT_EN)); 118 119 /* 120 * Actually make sure the above sequence hits hardware before sleeping. 121 */ 122 wmb(); 123 124 msleep(150); 125 return 0; 126 } 127 128 static const struct watchdog_ops qcom_wdt_ops = { 129 .start = qcom_wdt_start, 130 .stop = qcom_wdt_stop, 131 .ping = qcom_wdt_ping, 132 .set_timeout = qcom_wdt_set_timeout, 133 .restart = qcom_wdt_restart, 134 .owner = THIS_MODULE, 135 }; 136 137 static const struct watchdog_info qcom_wdt_info = { 138 .options = WDIOF_KEEPALIVEPING 139 | WDIOF_MAGICCLOSE 140 | WDIOF_SETTIMEOUT 141 | WDIOF_CARDRESET, 142 .identity = KBUILD_MODNAME, 143 }; 144 145 static int qcom_wdt_probe(struct platform_device *pdev) 146 { 147 struct qcom_wdt *wdt; 148 struct resource *res; 149 struct device_node *np = pdev->dev.of_node; 150 const u32 *regs; 151 u32 percpu_offset; 152 int ret; 153 154 regs = of_device_get_match_data(&pdev->dev); 155 if (!regs) { 156 dev_err(&pdev->dev, "Unsupported QCOM WDT module\n"); 157 return -ENODEV; 158 } 159 160 wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL); 161 if (!wdt) 162 return -ENOMEM; 163 164 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 165 if (!res) 166 return -ENOMEM; 167 168 /* We use CPU0's DGT for the watchdog */ 169 if (of_property_read_u32(np, "cpu-offset", &percpu_offset)) 170 percpu_offset = 0; 171 172 res->start += percpu_offset; 173 res->end += percpu_offset; 174 175 wdt->base = devm_ioremap_resource(&pdev->dev, res); 176 if (IS_ERR(wdt->base)) 177 return PTR_ERR(wdt->base); 178 179 wdt->clk = devm_clk_get(&pdev->dev, NULL); 180 if (IS_ERR(wdt->clk)) { 181 dev_err(&pdev->dev, "failed to get input clock\n"); 182 return PTR_ERR(wdt->clk); 183 } 184 185 ret = clk_prepare_enable(wdt->clk); 186 if (ret) { 187 dev_err(&pdev->dev, "failed to setup clock\n"); 188 return ret; 189 } 190 191 /* 192 * We use the clock rate to calculate the max timeout, so ensure it's 193 * not zero to avoid a divide-by-zero exception. 194 * 195 * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such 196 * that it would bite before a second elapses it's usefulness is 197 * limited. Bail if this is the case. 198 */ 199 wdt->rate = clk_get_rate(wdt->clk); 200 if (wdt->rate == 0 || 201 wdt->rate > 0x10000000U) { 202 dev_err(&pdev->dev, "invalid clock rate\n"); 203 ret = -EINVAL; 204 goto err_clk_unprepare; 205 } 206 207 wdt->wdd.info = &qcom_wdt_info; 208 wdt->wdd.ops = &qcom_wdt_ops; 209 wdt->wdd.min_timeout = 1; 210 wdt->wdd.max_timeout = 0x10000000U / wdt->rate; 211 wdt->wdd.parent = &pdev->dev; 212 wdt->layout = regs; 213 214 if (readl(wdt_addr(wdt, WDT_STS)) & 1) 215 wdt->wdd.bootstatus = WDIOF_CARDRESET; 216 217 /* 218 * If 'timeout-sec' unspecified in devicetree, assume a 30 second 219 * default, unless the max timeout is less than 30 seconds, then use 220 * the max instead. 221 */ 222 wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U); 223 watchdog_init_timeout(&wdt->wdd, 0, &pdev->dev); 224 225 ret = watchdog_register_device(&wdt->wdd); 226 if (ret) { 227 dev_err(&pdev->dev, "failed to register watchdog\n"); 228 goto err_clk_unprepare; 229 } 230 231 platform_set_drvdata(pdev, wdt); 232 return 0; 233 234 err_clk_unprepare: 235 clk_disable_unprepare(wdt->clk); 236 return ret; 237 } 238 239 static int qcom_wdt_remove(struct platform_device *pdev) 240 { 241 struct qcom_wdt *wdt = platform_get_drvdata(pdev); 242 243 watchdog_unregister_device(&wdt->wdd); 244 clk_disable_unprepare(wdt->clk); 245 return 0; 246 } 247 248 static const struct of_device_id qcom_wdt_of_table[] = { 249 { .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr }, 250 { .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr }, 251 { .compatible = "qcom,kpss-wdt", .data = reg_offset_data_kpss }, 252 { }, 253 }; 254 MODULE_DEVICE_TABLE(of, qcom_wdt_of_table); 255 256 static struct platform_driver qcom_watchdog_driver = { 257 .probe = qcom_wdt_probe, 258 .remove = qcom_wdt_remove, 259 .driver = { 260 .name = KBUILD_MODNAME, 261 .of_match_table = qcom_wdt_of_table, 262 }, 263 }; 264 module_platform_driver(qcom_watchdog_driver); 265 266 MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver"); 267 MODULE_LICENSE("GPL v2"); 268