1 /* Copyright (c) 2014, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 */ 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/io.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/platform_device.h> 20 #include <linux/watchdog.h> 21 #include <linux/of_device.h> 22 23 enum wdt_reg { 24 WDT_RST, 25 WDT_EN, 26 WDT_STS, 27 WDT_BARK_TIME, 28 WDT_BITE_TIME, 29 }; 30 31 static const u32 reg_offset_data_apcs_tmr[] = { 32 [WDT_RST] = 0x38, 33 [WDT_EN] = 0x40, 34 [WDT_STS] = 0x44, 35 [WDT_BARK_TIME] = 0x4C, 36 [WDT_BITE_TIME] = 0x5C, 37 }; 38 39 static const u32 reg_offset_data_kpss[] = { 40 [WDT_RST] = 0x4, 41 [WDT_EN] = 0x8, 42 [WDT_STS] = 0xC, 43 [WDT_BARK_TIME] = 0x10, 44 [WDT_BITE_TIME] = 0x14, 45 }; 46 47 struct qcom_wdt { 48 struct watchdog_device wdd; 49 struct clk *clk; 50 unsigned long rate; 51 void __iomem *base; 52 const u32 *layout; 53 }; 54 55 static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg) 56 { 57 return wdt->base + wdt->layout[reg]; 58 } 59 60 static inline 61 struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd) 62 { 63 return container_of(wdd, struct qcom_wdt, wdd); 64 } 65 66 static int qcom_wdt_start(struct watchdog_device *wdd) 67 { 68 struct qcom_wdt *wdt = to_qcom_wdt(wdd); 69 70 writel(0, wdt_addr(wdt, WDT_EN)); 71 writel(1, wdt_addr(wdt, WDT_RST)); 72 writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME)); 73 writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME)); 74 writel(1, wdt_addr(wdt, WDT_EN)); 75 return 0; 76 } 77 78 static int qcom_wdt_stop(struct watchdog_device *wdd) 79 { 80 struct qcom_wdt *wdt = to_qcom_wdt(wdd); 81 82 writel(0, wdt_addr(wdt, WDT_EN)); 83 return 0; 84 } 85 86 static int qcom_wdt_ping(struct watchdog_device *wdd) 87 { 88 struct qcom_wdt *wdt = to_qcom_wdt(wdd); 89 90 writel(1, wdt_addr(wdt, WDT_RST)); 91 return 0; 92 } 93 94 static int qcom_wdt_set_timeout(struct watchdog_device *wdd, 95 unsigned int timeout) 96 { 97 wdd->timeout = timeout; 98 return qcom_wdt_start(wdd); 99 } 100 101 static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action, 102 void *data) 103 { 104 struct qcom_wdt *wdt = to_qcom_wdt(wdd); 105 u32 timeout; 106 107 /* 108 * Trigger watchdog bite: 109 * Setup BITE_TIME to be 128ms, and enable WDT. 110 */ 111 timeout = 128 * wdt->rate / 1000; 112 113 writel(0, wdt_addr(wdt, WDT_EN)); 114 writel(1, wdt_addr(wdt, WDT_RST)); 115 writel(timeout, wdt_addr(wdt, WDT_BARK_TIME)); 116 writel(timeout, wdt_addr(wdt, WDT_BITE_TIME)); 117 writel(1, wdt_addr(wdt, WDT_EN)); 118 119 /* 120 * Actually make sure the above sequence hits hardware before sleeping. 121 */ 122 wmb(); 123 124 msleep(150); 125 return 0; 126 } 127 128 static const struct watchdog_ops qcom_wdt_ops = { 129 .start = qcom_wdt_start, 130 .stop = qcom_wdt_stop, 131 .ping = qcom_wdt_ping, 132 .set_timeout = qcom_wdt_set_timeout, 133 .restart = qcom_wdt_restart, 134 .owner = THIS_MODULE, 135 }; 136 137 static const struct watchdog_info qcom_wdt_info = { 138 .options = WDIOF_KEEPALIVEPING 139 | WDIOF_MAGICCLOSE 140 | WDIOF_SETTIMEOUT 141 | WDIOF_CARDRESET, 142 .identity = KBUILD_MODNAME, 143 }; 144 145 static void qcom_clk_disable_unprepare(void *data) 146 { 147 clk_disable_unprepare(data); 148 } 149 150 static int qcom_wdt_probe(struct platform_device *pdev) 151 { 152 struct device *dev = &pdev->dev; 153 struct qcom_wdt *wdt; 154 struct resource *res; 155 struct device_node *np = dev->of_node; 156 const u32 *regs; 157 u32 percpu_offset; 158 int ret; 159 160 regs = of_device_get_match_data(dev); 161 if (!regs) { 162 dev_err(dev, "Unsupported QCOM WDT module\n"); 163 return -ENODEV; 164 } 165 166 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); 167 if (!wdt) 168 return -ENOMEM; 169 170 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 171 if (!res) 172 return -ENOMEM; 173 174 /* We use CPU0's DGT for the watchdog */ 175 if (of_property_read_u32(np, "cpu-offset", &percpu_offset)) 176 percpu_offset = 0; 177 178 res->start += percpu_offset; 179 res->end += percpu_offset; 180 181 wdt->base = devm_ioremap_resource(dev, res); 182 if (IS_ERR(wdt->base)) 183 return PTR_ERR(wdt->base); 184 185 wdt->clk = devm_clk_get(dev, NULL); 186 if (IS_ERR(wdt->clk)) { 187 dev_err(dev, "failed to get input clock\n"); 188 return PTR_ERR(wdt->clk); 189 } 190 191 ret = clk_prepare_enable(wdt->clk); 192 if (ret) { 193 dev_err(dev, "failed to setup clock\n"); 194 return ret; 195 } 196 ret = devm_add_action_or_reset(dev, qcom_clk_disable_unprepare, 197 wdt->clk); 198 if (ret) 199 return ret; 200 201 /* 202 * We use the clock rate to calculate the max timeout, so ensure it's 203 * not zero to avoid a divide-by-zero exception. 204 * 205 * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such 206 * that it would bite before a second elapses it's usefulness is 207 * limited. Bail if this is the case. 208 */ 209 wdt->rate = clk_get_rate(wdt->clk); 210 if (wdt->rate == 0 || 211 wdt->rate > 0x10000000U) { 212 dev_err(dev, "invalid clock rate\n"); 213 return -EINVAL; 214 } 215 216 wdt->wdd.info = &qcom_wdt_info; 217 wdt->wdd.ops = &qcom_wdt_ops; 218 wdt->wdd.min_timeout = 1; 219 wdt->wdd.max_timeout = 0x10000000U / wdt->rate; 220 wdt->wdd.parent = dev; 221 wdt->layout = regs; 222 223 if (readl(wdt_addr(wdt, WDT_STS)) & 1) 224 wdt->wdd.bootstatus = WDIOF_CARDRESET; 225 226 /* 227 * If 'timeout-sec' unspecified in devicetree, assume a 30 second 228 * default, unless the max timeout is less than 30 seconds, then use 229 * the max instead. 230 */ 231 wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U); 232 watchdog_init_timeout(&wdt->wdd, 0, dev); 233 234 ret = devm_watchdog_register_device(dev, &wdt->wdd); 235 if (ret) { 236 dev_err(dev, "failed to register watchdog\n"); 237 return ret; 238 } 239 240 platform_set_drvdata(pdev, wdt); 241 return 0; 242 } 243 244 static int __maybe_unused qcom_wdt_suspend(struct device *dev) 245 { 246 struct qcom_wdt *wdt = dev_get_drvdata(dev); 247 248 if (watchdog_active(&wdt->wdd)) 249 qcom_wdt_stop(&wdt->wdd); 250 251 return 0; 252 } 253 254 static int __maybe_unused qcom_wdt_resume(struct device *dev) 255 { 256 struct qcom_wdt *wdt = dev_get_drvdata(dev); 257 258 if (watchdog_active(&wdt->wdd)) 259 qcom_wdt_start(&wdt->wdd); 260 261 return 0; 262 } 263 264 static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume); 265 266 static const struct of_device_id qcom_wdt_of_table[] = { 267 { .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr }, 268 { .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr }, 269 { .compatible = "qcom,kpss-wdt", .data = reg_offset_data_kpss }, 270 { }, 271 }; 272 MODULE_DEVICE_TABLE(of, qcom_wdt_of_table); 273 274 static struct platform_driver qcom_watchdog_driver = { 275 .probe = qcom_wdt_probe, 276 .driver = { 277 .name = KBUILD_MODNAME, 278 .of_match_table = qcom_wdt_of_table, 279 .pm = &qcom_wdt_pm_ops, 280 }, 281 }; 282 module_platform_driver(qcom_watchdog_driver); 283 284 MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver"); 285 MODULE_LICENSE("GPL v2"); 286