1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2014, The Linux Foundation. All rights reserved. 3 */ 4 #include <linux/bits.h> 5 #include <linux/clk.h> 6 #include <linux/delay.h> 7 #include <linux/interrupt.h> 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/watchdog.h> 14 #include <linux/of_device.h> 15 16 enum wdt_reg { 17 WDT_RST, 18 WDT_EN, 19 WDT_STS, 20 WDT_BARK_TIME, 21 WDT_BITE_TIME, 22 }; 23 24 #define QCOM_WDT_ENABLE BIT(0) 25 #define QCOM_WDT_ENABLE_IRQ BIT(1) 26 27 static const u32 reg_offset_data_apcs_tmr[] = { 28 [WDT_RST] = 0x38, 29 [WDT_EN] = 0x40, 30 [WDT_STS] = 0x44, 31 [WDT_BARK_TIME] = 0x4C, 32 [WDT_BITE_TIME] = 0x5C, 33 }; 34 35 static const u32 reg_offset_data_kpss[] = { 36 [WDT_RST] = 0x4, 37 [WDT_EN] = 0x8, 38 [WDT_STS] = 0xC, 39 [WDT_BARK_TIME] = 0x10, 40 [WDT_BITE_TIME] = 0x14, 41 }; 42 43 struct qcom_wdt { 44 struct watchdog_device wdd; 45 struct clk *clk; 46 unsigned long rate; 47 void __iomem *base; 48 const u32 *layout; 49 }; 50 51 static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg) 52 { 53 return wdt->base + wdt->layout[reg]; 54 } 55 56 static inline 57 struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd) 58 { 59 return container_of(wdd, struct qcom_wdt, wdd); 60 } 61 62 static inline int qcom_get_enable(struct watchdog_device *wdd) 63 { 64 int enable = QCOM_WDT_ENABLE; 65 66 if (wdd->pretimeout) 67 enable |= QCOM_WDT_ENABLE_IRQ; 68 69 return enable; 70 } 71 72 static irqreturn_t qcom_wdt_isr(int irq, void *arg) 73 { 74 struct watchdog_device *wdd = arg; 75 76 watchdog_notify_pretimeout(wdd); 77 78 return IRQ_HANDLED; 79 } 80 81 static int qcom_wdt_start(struct watchdog_device *wdd) 82 { 83 struct qcom_wdt *wdt = to_qcom_wdt(wdd); 84 unsigned int bark = wdd->timeout - wdd->pretimeout; 85 86 writel(0, wdt_addr(wdt, WDT_EN)); 87 writel(1, wdt_addr(wdt, WDT_RST)); 88 writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME)); 89 writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME)); 90 writel(qcom_get_enable(wdd), wdt_addr(wdt, WDT_EN)); 91 return 0; 92 } 93 94 static int qcom_wdt_stop(struct watchdog_device *wdd) 95 { 96 struct qcom_wdt *wdt = to_qcom_wdt(wdd); 97 98 writel(0, wdt_addr(wdt, WDT_EN)); 99 return 0; 100 } 101 102 static int qcom_wdt_ping(struct watchdog_device *wdd) 103 { 104 struct qcom_wdt *wdt = to_qcom_wdt(wdd); 105 106 writel(1, wdt_addr(wdt, WDT_RST)); 107 return 0; 108 } 109 110 static int qcom_wdt_set_timeout(struct watchdog_device *wdd, 111 unsigned int timeout) 112 { 113 wdd->timeout = timeout; 114 return qcom_wdt_start(wdd); 115 } 116 117 static int qcom_wdt_set_pretimeout(struct watchdog_device *wdd, 118 unsigned int timeout) 119 { 120 wdd->pretimeout = timeout; 121 return qcom_wdt_start(wdd); 122 } 123 124 static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action, 125 void *data) 126 { 127 struct qcom_wdt *wdt = to_qcom_wdt(wdd); 128 u32 timeout; 129 130 /* 131 * Trigger watchdog bite: 132 * Setup BITE_TIME to be 128ms, and enable WDT. 133 */ 134 timeout = 128 * wdt->rate / 1000; 135 136 writel(0, wdt_addr(wdt, WDT_EN)); 137 writel(1, wdt_addr(wdt, WDT_RST)); 138 writel(timeout, wdt_addr(wdt, WDT_BARK_TIME)); 139 writel(timeout, wdt_addr(wdt, WDT_BITE_TIME)); 140 writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN)); 141 142 /* 143 * Actually make sure the above sequence hits hardware before sleeping. 144 */ 145 wmb(); 146 147 msleep(150); 148 return 0; 149 } 150 151 static const struct watchdog_ops qcom_wdt_ops = { 152 .start = qcom_wdt_start, 153 .stop = qcom_wdt_stop, 154 .ping = qcom_wdt_ping, 155 .set_timeout = qcom_wdt_set_timeout, 156 .set_pretimeout = qcom_wdt_set_pretimeout, 157 .restart = qcom_wdt_restart, 158 .owner = THIS_MODULE, 159 }; 160 161 static const struct watchdog_info qcom_wdt_info = { 162 .options = WDIOF_KEEPALIVEPING 163 | WDIOF_MAGICCLOSE 164 | WDIOF_SETTIMEOUT 165 | WDIOF_CARDRESET, 166 .identity = KBUILD_MODNAME, 167 }; 168 169 static const struct watchdog_info qcom_wdt_pt_info = { 170 .options = WDIOF_KEEPALIVEPING 171 | WDIOF_MAGICCLOSE 172 | WDIOF_SETTIMEOUT 173 | WDIOF_PRETIMEOUT 174 | WDIOF_CARDRESET, 175 .identity = KBUILD_MODNAME, 176 }; 177 178 static void qcom_clk_disable_unprepare(void *data) 179 { 180 clk_disable_unprepare(data); 181 } 182 183 static int qcom_wdt_probe(struct platform_device *pdev) 184 { 185 struct device *dev = &pdev->dev; 186 struct qcom_wdt *wdt; 187 struct resource *res; 188 struct device_node *np = dev->of_node; 189 const u32 *regs; 190 u32 percpu_offset; 191 int irq, ret; 192 193 regs = of_device_get_match_data(dev); 194 if (!regs) { 195 dev_err(dev, "Unsupported QCOM WDT module\n"); 196 return -ENODEV; 197 } 198 199 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); 200 if (!wdt) 201 return -ENOMEM; 202 203 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 204 if (!res) 205 return -ENOMEM; 206 207 /* We use CPU0's DGT for the watchdog */ 208 if (of_property_read_u32(np, "cpu-offset", &percpu_offset)) 209 percpu_offset = 0; 210 211 res->start += percpu_offset; 212 res->end += percpu_offset; 213 214 wdt->base = devm_ioremap_resource(dev, res); 215 if (IS_ERR(wdt->base)) 216 return PTR_ERR(wdt->base); 217 218 wdt->clk = devm_clk_get(dev, NULL); 219 if (IS_ERR(wdt->clk)) { 220 dev_err(dev, "failed to get input clock\n"); 221 return PTR_ERR(wdt->clk); 222 } 223 224 ret = clk_prepare_enable(wdt->clk); 225 if (ret) { 226 dev_err(dev, "failed to setup clock\n"); 227 return ret; 228 } 229 ret = devm_add_action_or_reset(dev, qcom_clk_disable_unprepare, 230 wdt->clk); 231 if (ret) 232 return ret; 233 234 /* 235 * We use the clock rate to calculate the max timeout, so ensure it's 236 * not zero to avoid a divide-by-zero exception. 237 * 238 * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such 239 * that it would bite before a second elapses it's usefulness is 240 * limited. Bail if this is the case. 241 */ 242 wdt->rate = clk_get_rate(wdt->clk); 243 if (wdt->rate == 0 || 244 wdt->rate > 0x10000000U) { 245 dev_err(dev, "invalid clock rate\n"); 246 return -EINVAL; 247 } 248 249 /* check if there is pretimeout support */ 250 irq = platform_get_irq(pdev, 0); 251 if (irq > 0) { 252 ret = devm_request_irq(dev, irq, qcom_wdt_isr, 253 IRQF_TRIGGER_RISING, 254 "wdt_bark", &wdt->wdd); 255 if (ret) 256 return ret; 257 258 wdt->wdd.info = &qcom_wdt_pt_info; 259 wdt->wdd.pretimeout = 1; 260 } else { 261 if (irq == -EPROBE_DEFER) 262 return -EPROBE_DEFER; 263 264 wdt->wdd.info = &qcom_wdt_info; 265 } 266 267 wdt->wdd.ops = &qcom_wdt_ops; 268 wdt->wdd.min_timeout = 1; 269 wdt->wdd.max_timeout = 0x10000000U / wdt->rate; 270 wdt->wdd.parent = dev; 271 wdt->layout = regs; 272 273 if (readl(wdt_addr(wdt, WDT_STS)) & 1) 274 wdt->wdd.bootstatus = WDIOF_CARDRESET; 275 276 /* 277 * If 'timeout-sec' unspecified in devicetree, assume a 30 second 278 * default, unless the max timeout is less than 30 seconds, then use 279 * the max instead. 280 */ 281 wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U); 282 watchdog_init_timeout(&wdt->wdd, 0, dev); 283 284 ret = devm_watchdog_register_device(dev, &wdt->wdd); 285 if (ret) 286 return ret; 287 288 platform_set_drvdata(pdev, wdt); 289 return 0; 290 } 291 292 static int __maybe_unused qcom_wdt_suspend(struct device *dev) 293 { 294 struct qcom_wdt *wdt = dev_get_drvdata(dev); 295 296 if (watchdog_active(&wdt->wdd)) 297 qcom_wdt_stop(&wdt->wdd); 298 299 return 0; 300 } 301 302 static int __maybe_unused qcom_wdt_resume(struct device *dev) 303 { 304 struct qcom_wdt *wdt = dev_get_drvdata(dev); 305 306 if (watchdog_active(&wdt->wdd)) 307 qcom_wdt_start(&wdt->wdd); 308 309 return 0; 310 } 311 312 static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume); 313 314 static const struct of_device_id qcom_wdt_of_table[] = { 315 { .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr }, 316 { .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr }, 317 { .compatible = "qcom,kpss-wdt", .data = reg_offset_data_kpss }, 318 { }, 319 }; 320 MODULE_DEVICE_TABLE(of, qcom_wdt_of_table); 321 322 static struct platform_driver qcom_watchdog_driver = { 323 .probe = qcom_wdt_probe, 324 .driver = { 325 .name = KBUILD_MODNAME, 326 .of_match_table = qcom_wdt_of_table, 327 .pm = &qcom_wdt_pm_ops, 328 }, 329 }; 330 module_platform_driver(qcom_watchdog_driver); 331 332 MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver"); 333 MODULE_LICENSE("GPL v2"); 334