1 /*
2  * drivers/char/watchdog/pnx4008_wdt.c
3  *
4  * Watchdog driver for PNX4008 board
5  *
6  * Authors: Dmitry Chigirev <source@mvista.com>,
7  *	    Vitaly Wool <vitalywool@gmail.com>
8  * Based on sa1100 driver,
9  * Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
10  *
11  * 2005-2006 (c) MontaVista Software, Inc.
12  *
13  * (C) 2012 Wolfram Sang, Pengutronix
14  *
15  * This file is licensed under the terms of the GNU General Public License
16  * version 2. This program is licensed "as is" without any warranty of any
17  * kind, whether express or implied.
18  */
19 
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21 
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/miscdevice.h>
27 #include <linux/watchdog.h>
28 #include <linux/init.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/spinlock.h>
32 #include <linux/io.h>
33 #include <linux/slab.h>
34 #include <linux/err.h>
35 #include <linux/of.h>
36 #include <mach/hardware.h>
37 
38 /* WatchDog Timer - Chapter 23 Page 207 */
39 
40 #define DEFAULT_HEARTBEAT 19
41 #define MAX_HEARTBEAT     60
42 
43 /* Watchdog timer register set definition */
44 #define WDTIM_INT(p)     ((p) + 0x0)
45 #define WDTIM_CTRL(p)    ((p) + 0x4)
46 #define WDTIM_COUNTER(p) ((p) + 0x8)
47 #define WDTIM_MCTRL(p)   ((p) + 0xC)
48 #define WDTIM_MATCH0(p)  ((p) + 0x10)
49 #define WDTIM_EMR(p)     ((p) + 0x14)
50 #define WDTIM_PULSE(p)   ((p) + 0x18)
51 #define WDTIM_RES(p)     ((p) + 0x1C)
52 
53 /* WDTIM_INT bit definitions */
54 #define MATCH_INT      1
55 
56 /* WDTIM_CTRL bit definitions */
57 #define COUNT_ENAB     1
58 #define RESET_COUNT    (1 << 1)
59 #define DEBUG_EN       (1 << 2)
60 
61 /* WDTIM_MCTRL bit definitions */
62 #define MR0_INT        1
63 #undef  RESET_COUNT0
64 #define RESET_COUNT0   (1 << 2)
65 #define STOP_COUNT0    (1 << 2)
66 #define M_RES1         (1 << 3)
67 #define M_RES2         (1 << 4)
68 #define RESFRC1        (1 << 5)
69 #define RESFRC2        (1 << 6)
70 
71 /* WDTIM_EMR bit definitions */
72 #define EXT_MATCH0      1
73 #define MATCH_OUTPUT_HIGH (2 << 4)	/*a MATCH_CTRL setting */
74 
75 /* WDTIM_RES bit definitions */
76 #define WDOG_RESET      1	/* read only */
77 
78 #define WDOG_COUNTER_RATE 13000000	/*the counter clock is 13 MHz fixed */
79 
80 static bool nowayout = WATCHDOG_NOWAYOUT;
81 static unsigned int heartbeat = DEFAULT_HEARTBEAT;
82 
83 static DEFINE_SPINLOCK(io_lock);
84 static void __iomem	*wdt_base;
85 struct clk		*wdt_clk;
86 
87 static int pnx4008_wdt_start(struct watchdog_device *wdd)
88 {
89 	spin_lock(&io_lock);
90 
91 	/* stop counter, initiate counter reset */
92 	writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
93 	/*wait for reset to complete. 100% guarantee event */
94 	while (readl(WDTIM_COUNTER(wdt_base)))
95 		cpu_relax();
96 	/* internal and external reset, stop after that */
97 	writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base));
98 	/* configure match output */
99 	writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
100 	/* clear interrupt, just in case */
101 	writel(MATCH_INT, WDTIM_INT(wdt_base));
102 	/* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */
103 	writel(0xFFFF, WDTIM_PULSE(wdt_base));
104 	writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
105 	/*enable counter, stop when debugger active */
106 	writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base));
107 
108 	spin_unlock(&io_lock);
109 	return 0;
110 }
111 
112 static int pnx4008_wdt_stop(struct watchdog_device *wdd)
113 {
114 	spin_lock(&io_lock);
115 
116 	writel(0, WDTIM_CTRL(wdt_base));	/*stop counter */
117 
118 	spin_unlock(&io_lock);
119 	return 0;
120 }
121 
122 static int pnx4008_wdt_set_timeout(struct watchdog_device *wdd,
123 				    unsigned int new_timeout)
124 {
125 	wdd->timeout = new_timeout;
126 	return 0;
127 }
128 
129 static const struct watchdog_info pnx4008_wdt_ident = {
130 	.options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE |
131 	    WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
132 	.identity = "PNX4008 Watchdog",
133 };
134 
135 static const struct watchdog_ops pnx4008_wdt_ops = {
136 	.owner = THIS_MODULE,
137 	.start = pnx4008_wdt_start,
138 	.stop = pnx4008_wdt_stop,
139 	.set_timeout = pnx4008_wdt_set_timeout,
140 };
141 
142 static struct watchdog_device pnx4008_wdd = {
143 	.info = &pnx4008_wdt_ident,
144 	.ops = &pnx4008_wdt_ops,
145 	.timeout = DEFAULT_HEARTBEAT,
146 	.min_timeout = 1,
147 	.max_timeout = MAX_HEARTBEAT,
148 };
149 
150 static int pnx4008_wdt_probe(struct platform_device *pdev)
151 {
152 	struct resource *r;
153 	int ret = 0;
154 
155 	watchdog_init_timeout(&pnx4008_wdd, heartbeat, &pdev->dev);
156 
157 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
158 	wdt_base = devm_ioremap_resource(&pdev->dev, r);
159 	if (IS_ERR(wdt_base))
160 		return PTR_ERR(wdt_base);
161 
162 	wdt_clk = devm_clk_get(&pdev->dev, NULL);
163 	if (IS_ERR(wdt_clk))
164 		return PTR_ERR(wdt_clk);
165 
166 	ret = clk_enable(wdt_clk);
167 	if (ret)
168 		return ret;
169 
170 	pnx4008_wdd.bootstatus = (readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ?
171 			WDIOF_CARDRESET : 0;
172 	watchdog_set_nowayout(&pnx4008_wdd, nowayout);
173 
174 	pnx4008_wdt_stop(&pnx4008_wdd);	/* disable for now */
175 
176 	ret = watchdog_register_device(&pnx4008_wdd);
177 	if (ret < 0) {
178 		dev_err(&pdev->dev, "cannot register watchdog device\n");
179 		goto disable_clk;
180 	}
181 
182 	dev_info(&pdev->dev, "PNX4008 Watchdog Timer: heartbeat %d sec\n",
183 		 pnx4008_wdd.timeout);
184 
185 	return 0;
186 
187 disable_clk:
188 	clk_disable(wdt_clk);
189 	return ret;
190 }
191 
192 static int pnx4008_wdt_remove(struct platform_device *pdev)
193 {
194 	watchdog_unregister_device(&pnx4008_wdd);
195 
196 	clk_disable(wdt_clk);
197 
198 	return 0;
199 }
200 
201 #ifdef CONFIG_OF
202 static const struct of_device_id pnx4008_wdt_match[] = {
203 	{ .compatible = "nxp,pnx4008-wdt" },
204 	{ }
205 };
206 MODULE_DEVICE_TABLE(of, pnx4008_wdt_match);
207 #endif
208 
209 static struct platform_driver platform_wdt_driver = {
210 	.driver = {
211 		.name = "pnx4008-watchdog",
212 		.owner	= THIS_MODULE,
213 		.of_match_table = of_match_ptr(pnx4008_wdt_match),
214 	},
215 	.probe = pnx4008_wdt_probe,
216 	.remove = pnx4008_wdt_remove,
217 };
218 
219 module_platform_driver(platform_wdt_driver);
220 
221 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
222 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
223 MODULE_DESCRIPTION("PNX4008 Watchdog Driver");
224 
225 module_param(heartbeat, uint, 0);
226 MODULE_PARM_DESC(heartbeat,
227 		 "Watchdog heartbeat period in seconds from 1 to "
228 		 __MODULE_STRING(MAX_HEARTBEAT) ", default "
229 		 __MODULE_STRING(DEFAULT_HEARTBEAT));
230 
231 module_param(nowayout, bool, 0);
232 MODULE_PARM_DESC(nowayout,
233 		 "Set to 1 to keep watchdog running after device release");
234 
235 MODULE_LICENSE("GPL");
236 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
237 MODULE_ALIAS("platform:pnx4008-watchdog");
238