1 /* 2 * drivers/char/watchdog/pnx4008_wdt.c 3 * 4 * Watchdog driver for PNX4008 board 5 * 6 * Authors: Dmitry Chigirev <source@mvista.com>, 7 * Vitaly Wool <vitalywool@gmail.com> 8 * Based on sa1100 driver, 9 * Copyright (C) 2000 Oleg Drokin <green@crimea.edu> 10 * 11 * 2005-2006 (c) MontaVista Software, Inc. 12 * 13 * (C) 2012 Wolfram Sang, Pengutronix 14 * 15 * This file is licensed under the terms of the GNU General Public License 16 * version 2. This program is licensed "as is" without any warranty of any 17 * kind, whether express or implied. 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/module.h> 23 #include <linux/moduleparam.h> 24 #include <linux/types.h> 25 #include <linux/kernel.h> 26 #include <linux/watchdog.h> 27 #include <linux/platform_device.h> 28 #include <linux/clk.h> 29 #include <linux/spinlock.h> 30 #include <linux/io.h> 31 #include <linux/slab.h> 32 #include <linux/err.h> 33 #include <linux/of.h> 34 #include <linux/delay.h> 35 #include <linux/reboot.h> 36 #include <mach/hardware.h> 37 38 /* WatchDog Timer - Chapter 23 Page 207 */ 39 40 #define DEFAULT_HEARTBEAT 19 41 #define MAX_HEARTBEAT 60 42 43 /* Watchdog timer register set definition */ 44 #define WDTIM_INT(p) ((p) + 0x0) 45 #define WDTIM_CTRL(p) ((p) + 0x4) 46 #define WDTIM_COUNTER(p) ((p) + 0x8) 47 #define WDTIM_MCTRL(p) ((p) + 0xC) 48 #define WDTIM_MATCH0(p) ((p) + 0x10) 49 #define WDTIM_EMR(p) ((p) + 0x14) 50 #define WDTIM_PULSE(p) ((p) + 0x18) 51 #define WDTIM_RES(p) ((p) + 0x1C) 52 53 /* WDTIM_INT bit definitions */ 54 #define MATCH_INT 1 55 56 /* WDTIM_CTRL bit definitions */ 57 #define COUNT_ENAB 1 58 #define RESET_COUNT (1 << 1) 59 #define DEBUG_EN (1 << 2) 60 61 /* WDTIM_MCTRL bit definitions */ 62 #define MR0_INT 1 63 #undef RESET_COUNT0 64 #define RESET_COUNT0 (1 << 2) 65 #define STOP_COUNT0 (1 << 2) 66 #define M_RES1 (1 << 3) 67 #define M_RES2 (1 << 4) 68 #define RESFRC1 (1 << 5) 69 #define RESFRC2 (1 << 6) 70 71 /* WDTIM_EMR bit definitions */ 72 #define EXT_MATCH0 1 73 #define MATCH_OUTPUT_HIGH (2 << 4) /*a MATCH_CTRL setting */ 74 75 /* WDTIM_RES bit definitions */ 76 #define WDOG_RESET 1 /* read only */ 77 78 #define WDOG_COUNTER_RATE 13000000 /*the counter clock is 13 MHz fixed */ 79 80 static bool nowayout = WATCHDOG_NOWAYOUT; 81 static unsigned int heartbeat; 82 83 static DEFINE_SPINLOCK(io_lock); 84 static void __iomem *wdt_base; 85 static struct clk *wdt_clk; 86 87 static int pnx4008_wdt_start(struct watchdog_device *wdd) 88 { 89 spin_lock(&io_lock); 90 91 /* stop counter, initiate counter reset */ 92 writel(RESET_COUNT, WDTIM_CTRL(wdt_base)); 93 /*wait for reset to complete. 100% guarantee event */ 94 while (readl(WDTIM_COUNTER(wdt_base))) 95 cpu_relax(); 96 /* internal and external reset, stop after that */ 97 writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base)); 98 /* configure match output */ 99 writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base)); 100 /* clear interrupt, just in case */ 101 writel(MATCH_INT, WDTIM_INT(wdt_base)); 102 /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */ 103 writel(0xFFFF, WDTIM_PULSE(wdt_base)); 104 writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base)); 105 /*enable counter, stop when debugger active */ 106 writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base)); 107 108 spin_unlock(&io_lock); 109 return 0; 110 } 111 112 static int pnx4008_wdt_stop(struct watchdog_device *wdd) 113 { 114 spin_lock(&io_lock); 115 116 writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */ 117 118 spin_unlock(&io_lock); 119 return 0; 120 } 121 122 static int pnx4008_wdt_set_timeout(struct watchdog_device *wdd, 123 unsigned int new_timeout) 124 { 125 wdd->timeout = new_timeout; 126 return 0; 127 } 128 129 static int pnx4008_restart_handler(struct watchdog_device *wdd, 130 unsigned long mode, void *cmd) 131 { 132 const char *boot_cmd = cmd; 133 134 /* 135 * Verify if a "cmd" passed from the userspace program rebooting 136 * the system; if available, handle it. 137 * - For details, see the 'reboot' syscall in kernel/reboot.c 138 * - If the received "cmd" is not supported, use the default mode. 139 */ 140 if (boot_cmd) { 141 if (boot_cmd[0] == 'h') 142 mode = REBOOT_HARD; 143 else if (boot_cmd[0] == 's') 144 mode = REBOOT_SOFT; 145 } 146 147 if (mode == REBOOT_SOFT) { 148 /* Force match output active */ 149 writel(EXT_MATCH0, WDTIM_EMR(wdt_base)); 150 /* Internal reset on match output (RESOUT_N not asserted) */ 151 writel(M_RES1, WDTIM_MCTRL(wdt_base)); 152 } else { 153 /* Instant assert of RESETOUT_N with pulse length 1mS */ 154 writel(13000, WDTIM_PULSE(wdt_base)); 155 writel(M_RES2 | RESFRC1 | RESFRC2, WDTIM_MCTRL(wdt_base)); 156 } 157 158 /* Wait for watchdog to reset system */ 159 mdelay(1000); 160 161 return NOTIFY_DONE; 162 } 163 164 static const struct watchdog_info pnx4008_wdt_ident = { 165 .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE | 166 WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, 167 .identity = "PNX4008 Watchdog", 168 }; 169 170 static const struct watchdog_ops pnx4008_wdt_ops = { 171 .owner = THIS_MODULE, 172 .start = pnx4008_wdt_start, 173 .stop = pnx4008_wdt_stop, 174 .set_timeout = pnx4008_wdt_set_timeout, 175 .restart = pnx4008_restart_handler, 176 }; 177 178 static struct watchdog_device pnx4008_wdd = { 179 .info = &pnx4008_wdt_ident, 180 .ops = &pnx4008_wdt_ops, 181 .timeout = DEFAULT_HEARTBEAT, 182 .min_timeout = 1, 183 .max_timeout = MAX_HEARTBEAT, 184 }; 185 186 static void pnx4008_clk_disable_unprepare(void *data) 187 { 188 clk_disable_unprepare(data); 189 } 190 191 static int pnx4008_wdt_probe(struct platform_device *pdev) 192 { 193 struct device *dev = &pdev->dev; 194 int ret = 0; 195 196 watchdog_init_timeout(&pnx4008_wdd, heartbeat, dev); 197 198 wdt_base = devm_platform_ioremap_resource(pdev, 0); 199 if (IS_ERR(wdt_base)) 200 return PTR_ERR(wdt_base); 201 202 wdt_clk = devm_clk_get(dev, NULL); 203 if (IS_ERR(wdt_clk)) 204 return PTR_ERR(wdt_clk); 205 206 ret = clk_prepare_enable(wdt_clk); 207 if (ret) 208 return ret; 209 ret = devm_add_action_or_reset(dev, pnx4008_clk_disable_unprepare, 210 wdt_clk); 211 if (ret) 212 return ret; 213 214 pnx4008_wdd.bootstatus = (readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ? 215 WDIOF_CARDRESET : 0; 216 pnx4008_wdd.parent = dev; 217 watchdog_set_nowayout(&pnx4008_wdd, nowayout); 218 watchdog_set_restart_priority(&pnx4008_wdd, 128); 219 220 if (readl(WDTIM_CTRL(wdt_base)) & COUNT_ENAB) 221 set_bit(WDOG_HW_RUNNING, &pnx4008_wdd.status); 222 223 ret = devm_watchdog_register_device(dev, &pnx4008_wdd); 224 if (ret < 0) { 225 dev_err(dev, "cannot register watchdog device\n"); 226 return ret; 227 } 228 229 dev_info(dev, "heartbeat %d sec\n", pnx4008_wdd.timeout); 230 231 return 0; 232 } 233 234 #ifdef CONFIG_OF 235 static const struct of_device_id pnx4008_wdt_match[] = { 236 { .compatible = "nxp,pnx4008-wdt" }, 237 { } 238 }; 239 MODULE_DEVICE_TABLE(of, pnx4008_wdt_match); 240 #endif 241 242 static struct platform_driver platform_wdt_driver = { 243 .driver = { 244 .name = "pnx4008-watchdog", 245 .of_match_table = of_match_ptr(pnx4008_wdt_match), 246 }, 247 .probe = pnx4008_wdt_probe, 248 }; 249 250 module_platform_driver(platform_wdt_driver); 251 252 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); 253 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 254 MODULE_DESCRIPTION("PNX4008 Watchdog Driver"); 255 256 module_param(heartbeat, uint, 0); 257 MODULE_PARM_DESC(heartbeat, 258 "Watchdog heartbeat period in seconds from 1 to " 259 __MODULE_STRING(MAX_HEARTBEAT) ", default " 260 __MODULE_STRING(DEFAULT_HEARTBEAT)); 261 262 module_param(nowayout, bool, 0); 263 MODULE_PARM_DESC(nowayout, 264 "Set to 1 to keep watchdog running after device release"); 265 266 MODULE_LICENSE("GPL"); 267 MODULE_ALIAS("platform:pnx4008-watchdog"); 268