1 /*
2  * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt
3  *
4  * (C) Copyright 2013 - 2014 Xilinx, Inc.
5  * (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>)
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * as published by the Free Software Foundation; either version
10  * 2 of the License, or (at your option) any later version.
11  */
12 
13 #include <linux/clk.h>
14 #include <linux/err.h>
15 #include <linux/module.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/ioport.h>
19 #include <linux/watchdog.h>
20 #include <linux/io.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/of_address.h>
24 
25 /* Register offsets for the Wdt device */
26 #define XWT_TWCSR0_OFFSET   0x0 /* Control/Status Register0 */
27 #define XWT_TWCSR1_OFFSET   0x4 /* Control/Status Register1 */
28 #define XWT_TBR_OFFSET      0x8 /* Timebase Register Offset */
29 
30 /* Control/Status Register Masks  */
31 #define XWT_CSR0_WRS_MASK   0x00000008 /* Reset status */
32 #define XWT_CSR0_WDS_MASK   0x00000004 /* Timer state  */
33 #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */
34 
35 /* Control/Status Register 0/1 bits  */
36 #define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 */
37 
38 /* SelfTest constants */
39 #define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000
40 #define XWT_TIMER_FAILED            0xFFFFFFFF
41 
42 #define WATCHDOG_NAME     "Xilinx Watchdog"
43 
44 struct xwdt_device {
45 	void __iomem *base;
46 	u32 wdt_interval;
47 	spinlock_t spinlock;
48 	struct watchdog_device xilinx_wdt_wdd;
49 	struct clk		*clk;
50 };
51 
52 static int xilinx_wdt_start(struct watchdog_device *wdd)
53 {
54 	int ret;
55 	u32 control_status_reg;
56 	struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
57 
58 	ret = clk_enable(xdev->clk);
59 	if (ret) {
60 		dev_err(wdd->parent, "Failed to enable clock\n");
61 		return ret;
62 	}
63 
64 	spin_lock(&xdev->spinlock);
65 
66 	/* Clean previous status and enable the watchdog timer */
67 	control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
68 	control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
69 
70 	iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK),
71 		  xdev->base + XWT_TWCSR0_OFFSET);
72 
73 	iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET);
74 
75 	spin_unlock(&xdev->spinlock);
76 
77 	return 0;
78 }
79 
80 static int xilinx_wdt_stop(struct watchdog_device *wdd)
81 {
82 	u32 control_status_reg;
83 	struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
84 
85 	spin_lock(&xdev->spinlock);
86 
87 	control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
88 
89 	iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK),
90 		  xdev->base + XWT_TWCSR0_OFFSET);
91 
92 	iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET);
93 
94 	spin_unlock(&xdev->spinlock);
95 
96 	clk_disable(xdev->clk);
97 
98 	pr_info("Stopped!\n");
99 
100 	return 0;
101 }
102 
103 static int xilinx_wdt_keepalive(struct watchdog_device *wdd)
104 {
105 	u32 control_status_reg;
106 	struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
107 
108 	spin_lock(&xdev->spinlock);
109 
110 	control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
111 	control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
112 	iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET);
113 
114 	spin_unlock(&xdev->spinlock);
115 
116 	return 0;
117 }
118 
119 static const struct watchdog_info xilinx_wdt_ident = {
120 	.options =  WDIOF_MAGICCLOSE |
121 		    WDIOF_KEEPALIVEPING,
122 	.firmware_version =	1,
123 	.identity =	WATCHDOG_NAME,
124 };
125 
126 static const struct watchdog_ops xilinx_wdt_ops = {
127 	.owner = THIS_MODULE,
128 	.start = xilinx_wdt_start,
129 	.stop = xilinx_wdt_stop,
130 	.ping = xilinx_wdt_keepalive,
131 };
132 
133 static u32 xwdt_selftest(struct xwdt_device *xdev)
134 {
135 	int i;
136 	u32 timer_value1;
137 	u32 timer_value2;
138 
139 	spin_lock(&xdev->spinlock);
140 
141 	timer_value1 = ioread32(xdev->base + XWT_TBR_OFFSET);
142 	timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
143 
144 	for (i = 0;
145 		((i <= XWT_MAX_SELFTEST_LOOP_COUNT) &&
146 			(timer_value2 == timer_value1)); i++) {
147 		timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
148 	}
149 
150 	spin_unlock(&xdev->spinlock);
151 
152 	if (timer_value2 != timer_value1)
153 		return ~XWT_TIMER_FAILED;
154 	else
155 		return XWT_TIMER_FAILED;
156 }
157 
158 static int xwdt_probe(struct platform_device *pdev)
159 {
160 	int rc;
161 	u32 pfreq = 0, enable_once = 0;
162 	struct resource *res;
163 	struct xwdt_device *xdev;
164 	struct watchdog_device *xilinx_wdt_wdd;
165 
166 	xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
167 	if (!xdev)
168 		return -ENOMEM;
169 
170 	xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd;
171 	xilinx_wdt_wdd->info = &xilinx_wdt_ident;
172 	xilinx_wdt_wdd->ops = &xilinx_wdt_ops;
173 	xilinx_wdt_wdd->parent = &pdev->dev;
174 
175 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
176 	xdev->base = devm_ioremap_resource(&pdev->dev, res);
177 	if (IS_ERR(xdev->base))
178 		return PTR_ERR(xdev->base);
179 
180 	rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-interval",
181 				  &xdev->wdt_interval);
182 	if (rc)
183 		dev_warn(&pdev->dev,
184 			 "Parameter \"xlnx,wdt-interval\" not found\n");
185 
186 	rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-enable-once",
187 				  &enable_once);
188 	if (rc)
189 		dev_warn(&pdev->dev,
190 			 "Parameter \"xlnx,wdt-enable-once\" not found\n");
191 
192 	watchdog_set_nowayout(xilinx_wdt_wdd, enable_once);
193 
194 	xdev->clk = devm_clk_get(&pdev->dev, NULL);
195 	if (IS_ERR(xdev->clk)) {
196 		if (PTR_ERR(xdev->clk) != -ENOENT)
197 			return PTR_ERR(xdev->clk);
198 
199 		/*
200 		 * Clock framework support is optional, continue on
201 		 * anyways if we don't find a matching clock.
202 		 */
203 		xdev->clk = NULL;
204 
205 		rc = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
206 					  &pfreq);
207 		if (rc)
208 			dev_warn(&pdev->dev,
209 				 "The watchdog clock freq cannot be obtained\n");
210 	} else {
211 		pfreq = clk_get_rate(xdev->clk);
212 	}
213 
214 	/*
215 	 * Twice of the 2^wdt_interval / freq  because the first wdt overflow is
216 	 * ignored (interrupt), reset is only generated at second wdt overflow
217 	 */
218 	if (pfreq && xdev->wdt_interval)
219 		xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) /
220 					  pfreq);
221 
222 	spin_lock_init(&xdev->spinlock);
223 	watchdog_set_drvdata(xilinx_wdt_wdd, xdev);
224 
225 	rc = clk_prepare_enable(xdev->clk);
226 	if (rc) {
227 		dev_err(&pdev->dev, "unable to enable clock\n");
228 		return rc;
229 	}
230 
231 	rc = xwdt_selftest(xdev);
232 	if (rc == XWT_TIMER_FAILED) {
233 		dev_err(&pdev->dev, "SelfTest routine error\n");
234 		goto err_clk_disable;
235 	}
236 
237 	rc = watchdog_register_device(xilinx_wdt_wdd);
238 	if (rc) {
239 		dev_err(&pdev->dev, "Cannot register watchdog (err=%d)\n", rc);
240 		goto err_clk_disable;
241 	}
242 
243 	clk_disable(xdev->clk);
244 
245 	dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds\n",
246 		 xdev->base, xilinx_wdt_wdd->timeout);
247 
248 	platform_set_drvdata(pdev, xdev);
249 
250 	return 0;
251 err_clk_disable:
252 	clk_disable_unprepare(xdev->clk);
253 
254 	return rc;
255 }
256 
257 static int xwdt_remove(struct platform_device *pdev)
258 {
259 	struct xwdt_device *xdev = platform_get_drvdata(pdev);
260 
261 	watchdog_unregister_device(&xdev->xilinx_wdt_wdd);
262 	clk_disable_unprepare(xdev->clk);
263 
264 	return 0;
265 }
266 
267 /**
268  * xwdt_suspend - Suspend the device.
269  *
270  * @dev: handle to the device structure.
271  * Return: 0 always.
272  */
273 static int __maybe_unused xwdt_suspend(struct device *dev)
274 {
275 	struct platform_device *pdev = to_platform_device(dev);
276 	struct xwdt_device *xdev = platform_get_drvdata(pdev);
277 
278 	if (watchdog_active(&xdev->xilinx_wdt_wdd))
279 		xilinx_wdt_stop(&xdev->xilinx_wdt_wdd);
280 
281 	return 0;
282 }
283 
284 /**
285  * xwdt_resume - Resume the device.
286  *
287  * @dev: handle to the device structure.
288  * Return: 0 on success, errno otherwise.
289  */
290 static int __maybe_unused xwdt_resume(struct device *dev)
291 {
292 	struct platform_device *pdev = to_platform_device(dev);
293 	struct xwdt_device *xdev = platform_get_drvdata(pdev);
294 	int ret = 0;
295 
296 	if (watchdog_active(&xdev->xilinx_wdt_wdd))
297 		ret = xilinx_wdt_start(&xdev->xilinx_wdt_wdd);
298 
299 	return ret;
300 }
301 
302 static SIMPLE_DEV_PM_OPS(xwdt_pm_ops, xwdt_suspend, xwdt_resume);
303 
304 /* Match table for of_platform binding */
305 static const struct of_device_id xwdt_of_match[] = {
306 	{ .compatible = "xlnx,xps-timebase-wdt-1.00.a", },
307 	{ .compatible = "xlnx,xps-timebase-wdt-1.01.a", },
308 	{},
309 };
310 MODULE_DEVICE_TABLE(of, xwdt_of_match);
311 
312 static struct platform_driver xwdt_driver = {
313 	.probe       = xwdt_probe,
314 	.remove      = xwdt_remove,
315 	.driver = {
316 		.name  = WATCHDOG_NAME,
317 		.of_match_table = xwdt_of_match,
318 		.pm = &xwdt_pm_ops,
319 	},
320 };
321 
322 module_platform_driver(xwdt_driver);
323 
324 MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>");
325 MODULE_DESCRIPTION("Xilinx Watchdog driver");
326 MODULE_LICENSE("GPL v2");
327