1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License.  See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007-2017 Cavium, Inc.
7 */
8#include <asm/asm.h>
9#include <asm/regdef.h>
10
11#define CVMSEG_BASE	-32768
12#define CVMSEG_SIZE	6912
13#define SAVE_REG(r)	sd $r, CVMSEG_BASE + CVMSEG_SIZE - ((32 - r) * 8)($0)
14
15        NESTED(octeon_wdt_nmi_stage2, 0, sp)
16	.set 	push
17	.set 	noreorder
18	.set 	noat
19	/* Clear Dcache so cvmseg works right. */
20	cache	1,0($0)
21	/* Use K0 to do a read/modify/write of CVMMEMCTL */
22	dmfc0	k0, $11, 7
23	/* Clear out the size of CVMSEG	*/
24	dins	k0, $0, 0, 6
25	/* Set CVMSEG to its largest value */
26	ori	k0, k0, 0x1c0 | 54
27	/* Store the CVMMEMCTL value */
28	dmtc0	k0, $11, 7
29	/*
30	 * Restore K0 from the debug scratch register, it was saved in
31	 * the boot-vector code.
32	 */
33	dmfc0	k0, $31
34
35	/*
36	 * Save all registers to the top CVMSEG. This shouldn't
37	 * corrupt any state used by the kernel. Also all registers
38	 * should have the value right before the NMI.
39	 */
40	SAVE_REG(0)
41	SAVE_REG(1)
42	SAVE_REG(2)
43	SAVE_REG(3)
44	SAVE_REG(4)
45	SAVE_REG(5)
46	SAVE_REG(6)
47	SAVE_REG(7)
48	SAVE_REG(8)
49	SAVE_REG(9)
50	SAVE_REG(10)
51	SAVE_REG(11)
52	SAVE_REG(12)
53	SAVE_REG(13)
54	SAVE_REG(14)
55	SAVE_REG(15)
56	SAVE_REG(16)
57	SAVE_REG(17)
58	SAVE_REG(18)
59	SAVE_REG(19)
60	SAVE_REG(20)
61	SAVE_REG(21)
62	SAVE_REG(22)
63	SAVE_REG(23)
64	SAVE_REG(24)
65	SAVE_REG(25)
66	SAVE_REG(26)
67	SAVE_REG(27)
68	SAVE_REG(28)
69	SAVE_REG(29)
70	SAVE_REG(30)
71	SAVE_REG(31)
72	/* Write zero to all CVMSEG locations per Core-15169 */
73	dli	a0, CVMSEG_SIZE - (33 * 8)
741:	sd	zero, CVMSEG_BASE(a0)
75	daddiu	a0, a0, -8
76	bgez	a0, 1b
77	nop
78	/* Set the stack to begin right below the registers */
79	dli	sp, CVMSEG_BASE + CVMSEG_SIZE - (32 * 8)
80	/* Load the address of the third stage handler */
81	dla	$25, octeon_wdt_nmi_stage3
82	/* Call the third stage handler */
83	jal	$25
84	/* a0 is the address of the saved registers */
85	 move	a0, sp
86	/* Loop forvever if we get here. */
872:	b	2b
88	nop
89	.set pop
90	END(octeon_wdt_nmi_stage2)
91