1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Octeon Watchdog driver 4 * 5 * Copyright (C) 2007-2017 Cavium, Inc. 6 * 7 * Converted to use WATCHDOG_CORE by Aaro Koskinen <aaro.koskinen@iki.fi>. 8 * 9 * Some parts derived from wdt.c 10 * 11 * (c) Copyright 1996-1997 Alan Cox <alan@lxorguk.ukuu.org.uk>, 12 * All Rights Reserved. 13 * 14 * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide 15 * warranty for any of this software. This material is provided 16 * "AS-IS" and at no charge. 17 * 18 * (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk> 19 * 20 * The OCTEON watchdog has a maximum timeout of 2^32 * io_clock. 21 * For most systems this is less than 10 seconds, so to allow for 22 * software to request longer watchdog heartbeats, we maintain software 23 * counters to count multiples of the base rate. If the system locks 24 * up in such a manner that we can not run the software counters, the 25 * only result is a watchdog reset sooner than was requested. But 26 * that is OK, because in this case userspace would likely not be able 27 * to do anything anyhow. 28 * 29 * The hardware watchdog interval we call the period. The OCTEON 30 * watchdog goes through several stages, after the first period an 31 * irq is asserted, then if it is not reset, after the next period NMI 32 * is asserted, then after an additional period a chip wide soft reset. 33 * So for the software counters, we reset watchdog after each period 34 * and decrement the counter. But for the last two periods we need to 35 * let the watchdog progress to the NMI stage so we disable the irq 36 * and let it proceed. Once in the NMI, we print the register state 37 * to the serial port and then wait for the reset. 38 * 39 * A watchdog is maintained for each CPU in the system, that way if 40 * one CPU suffers a lockup, we also get a register dump and reset. 41 * The userspace ping resets the watchdog on all CPUs. 42 * 43 * Before userspace opens the watchdog device, we still run the 44 * watchdogs to catch any lockups that may be kernel related. 45 * 46 */ 47 48 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 49 50 #include <linux/interrupt.h> 51 #include <linux/watchdog.h> 52 #include <linux/cpumask.h> 53 #include <linux/module.h> 54 #include <linux/delay.h> 55 #include <linux/cpu.h> 56 #include <linux/irq.h> 57 #include <linux/irqdomain.h> 58 59 #include <asm/mipsregs.h> 60 #include <asm/uasm.h> 61 62 #include <asm/octeon/octeon.h> 63 #include <asm/octeon/cvmx-boot-vector.h> 64 #include <asm/octeon/cvmx-ciu2-defs.h> 65 #include <asm/octeon/cvmx-rst-defs.h> 66 67 /* Watchdog interrupt major block number (8 MSBs of intsn) */ 68 #define WD_BLOCK_NUMBER 0x01 69 70 static int divisor; 71 72 /* The count needed to achieve timeout_sec. */ 73 static unsigned int timeout_cnt; 74 75 /* The maximum period supported. */ 76 static unsigned int max_timeout_sec; 77 78 /* The current period. */ 79 static unsigned int timeout_sec; 80 81 /* Set to non-zero when userspace countdown mode active */ 82 static bool do_countdown; 83 static unsigned int countdown_reset; 84 static unsigned int per_cpu_countdown[NR_CPUS]; 85 86 static cpumask_t irq_enabled_cpus; 87 88 #define WD_TIMO 60 /* Default heartbeat = 60 seconds */ 89 90 #define CVMX_GSERX_SCRATCH(offset) (CVMX_ADD_IO_SEG(0x0001180090000020ull) + ((offset) & 15) * 0x1000000ull) 91 92 static int heartbeat = WD_TIMO; 93 module_param(heartbeat, int, 0444); 94 MODULE_PARM_DESC(heartbeat, 95 "Watchdog heartbeat in seconds. (0 < heartbeat, default=" 96 __MODULE_STRING(WD_TIMO) ")"); 97 98 static bool nowayout = WATCHDOG_NOWAYOUT; 99 module_param(nowayout, bool, 0444); 100 MODULE_PARM_DESC(nowayout, 101 "Watchdog cannot be stopped once started (default=" 102 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 103 104 static int disable; 105 module_param(disable, int, 0444); 106 MODULE_PARM_DESC(disable, 107 "Disable the watchdog entirely (default=0)"); 108 109 static struct cvmx_boot_vector_element *octeon_wdt_bootvector; 110 111 void octeon_wdt_nmi_stage2(void); 112 113 static int cpu2core(int cpu) 114 { 115 #ifdef CONFIG_SMP 116 return cpu_logical_map(cpu) & 0x3f; 117 #else 118 return cvmx_get_core_num(); 119 #endif 120 } 121 122 /** 123 * octeon_wdt_poke_irq - Poke the watchdog when an interrupt is received 124 * 125 * @cpl: 126 * @dev_id: 127 * 128 * Returns 129 */ 130 static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id) 131 { 132 int cpu = raw_smp_processor_id(); 133 unsigned int core = cpu2core(cpu); 134 int node = cpu_to_node(cpu); 135 136 if (do_countdown) { 137 if (per_cpu_countdown[cpu] > 0) { 138 /* We're alive, poke the watchdog */ 139 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); 140 per_cpu_countdown[cpu]--; 141 } else { 142 /* Bad news, you are about to reboot. */ 143 disable_irq_nosync(cpl); 144 cpumask_clear_cpu(cpu, &irq_enabled_cpus); 145 } 146 } else { 147 /* Not open, just ping away... */ 148 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); 149 } 150 return IRQ_HANDLED; 151 } 152 153 /* From setup.c */ 154 extern int prom_putchar(char c); 155 156 /** 157 * octeon_wdt_write_string - Write a string to the uart 158 * 159 * @str: String to write 160 */ 161 static void octeon_wdt_write_string(const char *str) 162 { 163 /* Just loop writing one byte at a time */ 164 while (*str) 165 prom_putchar(*str++); 166 } 167 168 /** 169 * octeon_wdt_write_hex() - Write a hex number out of the uart 170 * 171 * @value: Number to display 172 * @digits: Number of digits to print (1 to 16) 173 */ 174 static void octeon_wdt_write_hex(u64 value, int digits) 175 { 176 int d; 177 int v; 178 179 for (d = 0; d < digits; d++) { 180 v = (value >> ((digits - d - 1) * 4)) & 0xf; 181 if (v >= 10) 182 prom_putchar('a' + v - 10); 183 else 184 prom_putchar('0' + v); 185 } 186 } 187 188 static const char reg_name[][3] = { 189 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", 190 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", 191 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 192 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 193 }; 194 195 /** 196 * octeon_wdt_nmi_stage3: 197 * 198 * NMI stage 3 handler. NMIs are handled in the following manner: 199 * 1) The first NMI handler enables CVMSEG and transfers from 200 * the bootbus region into normal memory. It is careful to not 201 * destroy any registers. 202 * 2) The second stage handler uses CVMSEG to save the registers 203 * and create a stack for C code. It then calls the third level 204 * handler with one argument, a pointer to the register values. 205 * 3) The third, and final, level handler is the following C 206 * function that prints out some useful infomration. 207 * 208 * @reg: Pointer to register state before the NMI 209 */ 210 void octeon_wdt_nmi_stage3(u64 reg[32]) 211 { 212 u64 i; 213 214 unsigned int coreid = cvmx_get_core_num(); 215 /* 216 * Save status and cause early to get them before any changes 217 * might happen. 218 */ 219 u64 cp0_cause = read_c0_cause(); 220 u64 cp0_status = read_c0_status(); 221 u64 cp0_error_epc = read_c0_errorepc(); 222 u64 cp0_epc = read_c0_epc(); 223 224 /* Delay so output from all cores output is not jumbled together. */ 225 udelay(85000 * coreid); 226 227 octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x"); 228 octeon_wdt_write_hex(coreid, 2); 229 octeon_wdt_write_string(" ***\r\n"); 230 for (i = 0; i < 32; i++) { 231 octeon_wdt_write_string("\t"); 232 octeon_wdt_write_string(reg_name[i]); 233 octeon_wdt_write_string("\t0x"); 234 octeon_wdt_write_hex(reg[i], 16); 235 if (i & 1) 236 octeon_wdt_write_string("\r\n"); 237 } 238 octeon_wdt_write_string("\terr_epc\t0x"); 239 octeon_wdt_write_hex(cp0_error_epc, 16); 240 241 octeon_wdt_write_string("\tepc\t0x"); 242 octeon_wdt_write_hex(cp0_epc, 16); 243 octeon_wdt_write_string("\r\n"); 244 245 octeon_wdt_write_string("\tstatus\t0x"); 246 octeon_wdt_write_hex(cp0_status, 16); 247 octeon_wdt_write_string("\tcause\t0x"); 248 octeon_wdt_write_hex(cp0_cause, 16); 249 octeon_wdt_write_string("\r\n"); 250 251 /* The CIU register is different for each Octeon model. */ 252 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { 253 octeon_wdt_write_string("\tsrc_wd\t0x"); 254 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_WDOG(coreid)), 16); 255 octeon_wdt_write_string("\ten_wd\t0x"); 256 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_WDOG(coreid)), 16); 257 octeon_wdt_write_string("\r\n"); 258 octeon_wdt_write_string("\tsrc_rml\t0x"); 259 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_RML(coreid)), 16); 260 octeon_wdt_write_string("\ten_rml\t0x"); 261 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_RML(coreid)), 16); 262 octeon_wdt_write_string("\r\n"); 263 octeon_wdt_write_string("\tsum\t0x"); 264 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)), 16); 265 octeon_wdt_write_string("\r\n"); 266 } else if (!octeon_has_feature(OCTEON_FEATURE_CIU3)) { 267 octeon_wdt_write_string("\tsum0\t0x"); 268 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16); 269 octeon_wdt_write_string("\ten0\t0x"); 270 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16); 271 octeon_wdt_write_string("\r\n"); 272 } 273 274 octeon_wdt_write_string("*** Chip soft reset soon ***\r\n"); 275 276 /* 277 * G-30204: We must trigger a soft reset before watchdog 278 * does an incomplete job of doing it. 279 */ 280 if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX)) { 281 u64 scr; 282 unsigned int node = cvmx_get_node_num(); 283 unsigned int lcore = cvmx_get_local_core_num(); 284 union cvmx_ciu_wdogx ciu_wdog; 285 286 /* 287 * Wait for other cores to print out information, but 288 * not too long. Do the soft reset before watchdog 289 * can trigger it. 290 */ 291 do { 292 ciu_wdog.u64 = cvmx_read_csr_node(node, CVMX_CIU_WDOGX(lcore)); 293 } while (ciu_wdog.s.cnt > 0x10000); 294 295 scr = cvmx_read_csr_node(0, CVMX_GSERX_SCRATCH(0)); 296 scr |= 1 << 11; /* Indicate watchdog in bit 11 */ 297 cvmx_write_csr_node(0, CVMX_GSERX_SCRATCH(0), scr); 298 cvmx_write_csr_node(0, CVMX_RST_SOFT_RST, 1); 299 } 300 } 301 302 static int octeon_wdt_cpu_to_irq(int cpu) 303 { 304 unsigned int coreid; 305 int node; 306 int irq; 307 308 coreid = cpu2core(cpu); 309 node = cpu_to_node(cpu); 310 311 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) { 312 struct irq_domain *domain; 313 int hwirq; 314 315 domain = octeon_irq_get_block_domain(node, 316 WD_BLOCK_NUMBER); 317 hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | coreid; 318 irq = irq_find_mapping(domain, hwirq); 319 } else { 320 irq = OCTEON_IRQ_WDOG0 + coreid; 321 } 322 return irq; 323 } 324 325 static int octeon_wdt_cpu_pre_down(unsigned int cpu) 326 { 327 unsigned int core; 328 int node; 329 union cvmx_ciu_wdogx ciu_wdog; 330 331 core = cpu2core(cpu); 332 333 node = cpu_to_node(cpu); 334 335 /* Poke the watchdog to clear out its state */ 336 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); 337 338 /* Disable the hardware. */ 339 ciu_wdog.u64 = 0; 340 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64); 341 342 free_irq(octeon_wdt_cpu_to_irq(cpu), octeon_wdt_poke_irq); 343 return 0; 344 } 345 346 static int octeon_wdt_cpu_online(unsigned int cpu) 347 { 348 unsigned int core; 349 unsigned int irq; 350 union cvmx_ciu_wdogx ciu_wdog; 351 int node; 352 struct irq_domain *domain; 353 int hwirq; 354 355 core = cpu2core(cpu); 356 node = cpu_to_node(cpu); 357 358 octeon_wdt_bootvector[core].target_ptr = (u64)octeon_wdt_nmi_stage2; 359 360 /* Disable it before doing anything with the interrupts. */ 361 ciu_wdog.u64 = 0; 362 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64); 363 364 per_cpu_countdown[cpu] = countdown_reset; 365 366 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) { 367 /* Must get the domain for the watchdog block */ 368 domain = octeon_irq_get_block_domain(node, WD_BLOCK_NUMBER); 369 370 /* Get a irq for the wd intsn (hardware interrupt) */ 371 hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | core; 372 irq = irq_create_mapping(domain, hwirq); 373 irqd_set_trigger_type(irq_get_irq_data(irq), 374 IRQ_TYPE_EDGE_RISING); 375 } else 376 irq = OCTEON_IRQ_WDOG0 + core; 377 378 if (request_irq(irq, octeon_wdt_poke_irq, 379 IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq)) 380 panic("octeon_wdt: Couldn't obtain irq %d", irq); 381 382 /* Must set the irq affinity here */ 383 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) { 384 cpumask_t mask; 385 386 cpumask_clear(&mask); 387 cpumask_set_cpu(cpu, &mask); 388 irq_set_affinity(irq, &mask); 389 } 390 391 cpumask_set_cpu(cpu, &irq_enabled_cpus); 392 393 /* Poke the watchdog to clear out its state */ 394 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); 395 396 /* Finally enable the watchdog now that all handlers are installed */ 397 ciu_wdog.u64 = 0; 398 ciu_wdog.s.len = timeout_cnt; 399 ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */ 400 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64); 401 402 return 0; 403 } 404 405 static int octeon_wdt_ping(struct watchdog_device __always_unused *wdog) 406 { 407 int cpu; 408 int coreid; 409 int node; 410 411 if (disable) 412 return 0; 413 414 for_each_online_cpu(cpu) { 415 coreid = cpu2core(cpu); 416 node = cpu_to_node(cpu); 417 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1); 418 per_cpu_countdown[cpu] = countdown_reset; 419 if ((countdown_reset || !do_countdown) && 420 !cpumask_test_cpu(cpu, &irq_enabled_cpus)) { 421 /* We have to enable the irq */ 422 enable_irq(octeon_wdt_cpu_to_irq(cpu)); 423 cpumask_set_cpu(cpu, &irq_enabled_cpus); 424 } 425 } 426 return 0; 427 } 428 429 static void octeon_wdt_calc_parameters(int t) 430 { 431 unsigned int periods; 432 433 timeout_sec = max_timeout_sec; 434 435 436 /* 437 * Find the largest interrupt period, that can evenly divide 438 * the requested heartbeat time. 439 */ 440 while ((t % timeout_sec) != 0) 441 timeout_sec--; 442 443 periods = t / timeout_sec; 444 445 /* 446 * The last two periods are after the irq is disabled, and 447 * then to the nmi, so we subtract them off. 448 */ 449 450 countdown_reset = periods > 2 ? periods - 2 : 0; 451 heartbeat = t; 452 timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * timeout_sec) >> 8; 453 } 454 455 static int octeon_wdt_set_timeout(struct watchdog_device *wdog, 456 unsigned int t) 457 { 458 int cpu; 459 int coreid; 460 union cvmx_ciu_wdogx ciu_wdog; 461 int node; 462 463 if (t <= 0) 464 return -1; 465 466 octeon_wdt_calc_parameters(t); 467 468 if (disable) 469 return 0; 470 471 for_each_online_cpu(cpu) { 472 coreid = cpu2core(cpu); 473 node = cpu_to_node(cpu); 474 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1); 475 ciu_wdog.u64 = 0; 476 ciu_wdog.s.len = timeout_cnt; 477 ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */ 478 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(coreid), ciu_wdog.u64); 479 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1); 480 } 481 octeon_wdt_ping(wdog); /* Get the irqs back on. */ 482 return 0; 483 } 484 485 static int octeon_wdt_start(struct watchdog_device *wdog) 486 { 487 octeon_wdt_ping(wdog); 488 do_countdown = 1; 489 return 0; 490 } 491 492 static int octeon_wdt_stop(struct watchdog_device *wdog) 493 { 494 do_countdown = 0; 495 octeon_wdt_ping(wdog); 496 return 0; 497 } 498 499 static const struct watchdog_info octeon_wdt_info = { 500 .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, 501 .identity = "OCTEON", 502 }; 503 504 static const struct watchdog_ops octeon_wdt_ops = { 505 .owner = THIS_MODULE, 506 .start = octeon_wdt_start, 507 .stop = octeon_wdt_stop, 508 .ping = octeon_wdt_ping, 509 .set_timeout = octeon_wdt_set_timeout, 510 }; 511 512 static struct watchdog_device octeon_wdt = { 513 .info = &octeon_wdt_info, 514 .ops = &octeon_wdt_ops, 515 }; 516 517 static enum cpuhp_state octeon_wdt_online; 518 /** 519 * octeon_wdt_init - Module/ driver initialization. 520 * 521 * Returns Zero on success 522 */ 523 static int __init octeon_wdt_init(void) 524 { 525 int ret; 526 527 octeon_wdt_bootvector = cvmx_boot_vector_get(); 528 if (!octeon_wdt_bootvector) { 529 pr_err("Error: Cannot allocate boot vector.\n"); 530 return -ENOMEM; 531 } 532 533 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 534 divisor = 0x200; 535 else if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 536 divisor = 0x400; 537 else 538 divisor = 0x100; 539 540 /* 541 * Watchdog time expiration length = The 16 bits of LEN 542 * represent the most significant bits of a 24 bit decrementer 543 * that decrements every divisor cycle. 544 * 545 * Try for a timeout of 5 sec, if that fails a smaller number 546 * of even seconds, 547 */ 548 max_timeout_sec = 6; 549 do { 550 max_timeout_sec--; 551 timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * max_timeout_sec) >> 8; 552 } while (timeout_cnt > 65535); 553 554 BUG_ON(timeout_cnt == 0); 555 556 octeon_wdt_calc_parameters(heartbeat); 557 558 pr_info("Initial granularity %d Sec\n", timeout_sec); 559 560 octeon_wdt.timeout = timeout_sec; 561 octeon_wdt.max_timeout = UINT_MAX; 562 563 watchdog_set_nowayout(&octeon_wdt, nowayout); 564 565 ret = watchdog_register_device(&octeon_wdt); 566 if (ret) { 567 pr_err("watchdog_register_device() failed: %d\n", ret); 568 return ret; 569 } 570 571 if (disable) { 572 pr_notice("disabled\n"); 573 return 0; 574 } 575 576 cpumask_clear(&irq_enabled_cpus); 577 578 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "watchdog/octeon:online", 579 octeon_wdt_cpu_online, octeon_wdt_cpu_pre_down); 580 if (ret < 0) 581 goto err; 582 octeon_wdt_online = ret; 583 return 0; 584 err: 585 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0); 586 watchdog_unregister_device(&octeon_wdt); 587 return ret; 588 } 589 590 /** 591 * octeon_wdt_cleanup - Module / driver shutdown 592 */ 593 static void __exit octeon_wdt_cleanup(void) 594 { 595 watchdog_unregister_device(&octeon_wdt); 596 597 if (disable) 598 return; 599 600 cpuhp_remove_state(octeon_wdt_online); 601 602 /* 603 * Disable the boot-bus memory, the code it points to is soon 604 * to go missing. 605 */ 606 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0); 607 } 608 609 MODULE_LICENSE("GPL"); 610 MODULE_AUTHOR("Cavium Inc. <support@cavium.com>"); 611 MODULE_DESCRIPTION("Cavium Inc. OCTEON Watchdog driver."); 612 module_init(octeon_wdt_init); 613 module_exit(octeon_wdt_cleanup); 614