1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Octeon Watchdog driver 4 * 5 * Copyright (C) 2007-2017 Cavium, Inc. 6 * 7 * Converted to use WATCHDOG_CORE by Aaro Koskinen <aaro.koskinen@iki.fi>. 8 * 9 * Some parts derived from wdt.c 10 * 11 * (c) Copyright 1996-1997 Alan Cox <alan@lxorguk.ukuu.org.uk>, 12 * All Rights Reserved. 13 * 14 * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide 15 * warranty for any of this software. This material is provided 16 * "AS-IS" and at no charge. 17 * 18 * (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk> 19 * 20 * The OCTEON watchdog has a maximum timeout of 2^32 * io_clock. 21 * For most systems this is less than 10 seconds, so to allow for 22 * software to request longer watchdog heartbeats, we maintain software 23 * counters to count multiples of the base rate. If the system locks 24 * up in such a manner that we can not run the software counters, the 25 * only result is a watchdog reset sooner than was requested. But 26 * that is OK, because in this case userspace would likely not be able 27 * to do anything anyhow. 28 * 29 * The hardware watchdog interval we call the period. The OCTEON 30 * watchdog goes through several stages, after the first period an 31 * irq is asserted, then if it is not reset, after the next period NMI 32 * is asserted, then after an additional period a chip wide soft reset. 33 * So for the software counters, we reset watchdog after each period 34 * and decrement the counter. But for the last two periods we need to 35 * let the watchdog progress to the NMI stage so we disable the irq 36 * and let it proceed. Once in the NMI, we print the register state 37 * to the serial port and then wait for the reset. 38 * 39 * A watchdog is maintained for each CPU in the system, that way if 40 * one CPU suffers a lockup, we also get a register dump and reset. 41 * The userspace ping resets the watchdog on all CPUs. 42 * 43 * Before userspace opens the watchdog device, we still run the 44 * watchdogs to catch any lockups that may be kernel related. 45 * 46 */ 47 48 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 49 50 #include <linux/interrupt.h> 51 #include <linux/watchdog.h> 52 #include <linux/cpumask.h> 53 #include <linux/module.h> 54 #include <linux/delay.h> 55 #include <linux/cpu.h> 56 #include <linux/irq.h> 57 #include <linux/irqdomain.h> 58 59 #include <asm/mipsregs.h> 60 #include <asm/uasm.h> 61 62 #include <asm/octeon/octeon.h> 63 #include <asm/octeon/cvmx-boot-vector.h> 64 #include <asm/octeon/cvmx-ciu2-defs.h> 65 #include <asm/octeon/cvmx-rst-defs.h> 66 67 /* Watchdog interrupt major block number (8 MSBs of intsn) */ 68 #define WD_BLOCK_NUMBER 0x01 69 70 static int divisor; 71 72 /* The count needed to achieve timeout_sec. */ 73 static unsigned int timeout_cnt; 74 75 /* The maximum period supported. */ 76 static unsigned int max_timeout_sec; 77 78 /* The current period. */ 79 static unsigned int timeout_sec; 80 81 /* Set to non-zero when userspace countdown mode active */ 82 static bool do_countdown; 83 static unsigned int countdown_reset; 84 static unsigned int per_cpu_countdown[NR_CPUS]; 85 86 static cpumask_t irq_enabled_cpus; 87 88 #define WD_TIMO 60 /* Default heartbeat = 60 seconds */ 89 90 #define CVMX_GSERX_SCRATCH(offset) (CVMX_ADD_IO_SEG(0x0001180090000020ull) + ((offset) & 15) * 0x1000000ull) 91 92 static int heartbeat = WD_TIMO; 93 module_param(heartbeat, int, 0444); 94 MODULE_PARM_DESC(heartbeat, 95 "Watchdog heartbeat in seconds. (0 < heartbeat, default=" 96 __MODULE_STRING(WD_TIMO) ")"); 97 98 static bool nowayout = WATCHDOG_NOWAYOUT; 99 module_param(nowayout, bool, 0444); 100 MODULE_PARM_DESC(nowayout, 101 "Watchdog cannot be stopped once started (default=" 102 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 103 104 static int disable; 105 module_param(disable, int, 0444); 106 MODULE_PARM_DESC(disable, 107 "Disable the watchdog entirely (default=0)"); 108 109 static struct cvmx_boot_vector_element *octeon_wdt_bootvector; 110 111 void octeon_wdt_nmi_stage2(void); 112 113 static int cpu2core(int cpu) 114 { 115 #ifdef CONFIG_SMP 116 return cpu_logical_map(cpu) & 0x3f; 117 #else 118 return cvmx_get_core_num(); 119 #endif 120 } 121 122 /** 123 * Poke the watchdog when an interrupt is received 124 * 125 * @cpl: 126 * @dev_id: 127 * 128 * Returns 129 */ 130 static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id) 131 { 132 int cpu = raw_smp_processor_id(); 133 unsigned int core = cpu2core(cpu); 134 int node = cpu_to_node(cpu); 135 136 if (do_countdown) { 137 if (per_cpu_countdown[cpu] > 0) { 138 /* We're alive, poke the watchdog */ 139 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); 140 per_cpu_countdown[cpu]--; 141 } else { 142 /* Bad news, you are about to reboot. */ 143 disable_irq_nosync(cpl); 144 cpumask_clear_cpu(cpu, &irq_enabled_cpus); 145 } 146 } else { 147 /* Not open, just ping away... */ 148 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); 149 } 150 return IRQ_HANDLED; 151 } 152 153 /* From setup.c */ 154 extern int prom_putchar(char c); 155 156 /** 157 * Write a string to the uart 158 * 159 * @str: String to write 160 */ 161 static void octeon_wdt_write_string(const char *str) 162 { 163 /* Just loop writing one byte at a time */ 164 while (*str) 165 prom_putchar(*str++); 166 } 167 168 /** 169 * Write a hex number out of the uart 170 * 171 * @value: Number to display 172 * @digits: Number of digits to print (1 to 16) 173 */ 174 static void octeon_wdt_write_hex(u64 value, int digits) 175 { 176 int d; 177 int v; 178 179 for (d = 0; d < digits; d++) { 180 v = (value >> ((digits - d - 1) * 4)) & 0xf; 181 if (v >= 10) 182 prom_putchar('a' + v - 10); 183 else 184 prom_putchar('0' + v); 185 } 186 } 187 188 static const char reg_name[][3] = { 189 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", 190 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", 191 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 192 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 193 }; 194 195 /** 196 * NMI stage 3 handler. NMIs are handled in the following manner: 197 * 1) The first NMI handler enables CVMSEG and transfers from 198 * the bootbus region into normal memory. It is careful to not 199 * destroy any registers. 200 * 2) The second stage handler uses CVMSEG to save the registers 201 * and create a stack for C code. It then calls the third level 202 * handler with one argument, a pointer to the register values. 203 * 3) The third, and final, level handler is the following C 204 * function that prints out some useful infomration. 205 * 206 * @reg: Pointer to register state before the NMI 207 */ 208 void octeon_wdt_nmi_stage3(u64 reg[32]) 209 { 210 u64 i; 211 212 unsigned int coreid = cvmx_get_core_num(); 213 /* 214 * Save status and cause early to get them before any changes 215 * might happen. 216 */ 217 u64 cp0_cause = read_c0_cause(); 218 u64 cp0_status = read_c0_status(); 219 u64 cp0_error_epc = read_c0_errorepc(); 220 u64 cp0_epc = read_c0_epc(); 221 222 /* Delay so output from all cores output is not jumbled together. */ 223 udelay(85000 * coreid); 224 225 octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x"); 226 octeon_wdt_write_hex(coreid, 2); 227 octeon_wdt_write_string(" ***\r\n"); 228 for (i = 0; i < 32; i++) { 229 octeon_wdt_write_string("\t"); 230 octeon_wdt_write_string(reg_name[i]); 231 octeon_wdt_write_string("\t0x"); 232 octeon_wdt_write_hex(reg[i], 16); 233 if (i & 1) 234 octeon_wdt_write_string("\r\n"); 235 } 236 octeon_wdt_write_string("\terr_epc\t0x"); 237 octeon_wdt_write_hex(cp0_error_epc, 16); 238 239 octeon_wdt_write_string("\tepc\t0x"); 240 octeon_wdt_write_hex(cp0_epc, 16); 241 octeon_wdt_write_string("\r\n"); 242 243 octeon_wdt_write_string("\tstatus\t0x"); 244 octeon_wdt_write_hex(cp0_status, 16); 245 octeon_wdt_write_string("\tcause\t0x"); 246 octeon_wdt_write_hex(cp0_cause, 16); 247 octeon_wdt_write_string("\r\n"); 248 249 /* The CIU register is different for each Octeon model. */ 250 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { 251 octeon_wdt_write_string("\tsrc_wd\t0x"); 252 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_WDOG(coreid)), 16); 253 octeon_wdt_write_string("\ten_wd\t0x"); 254 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_WDOG(coreid)), 16); 255 octeon_wdt_write_string("\r\n"); 256 octeon_wdt_write_string("\tsrc_rml\t0x"); 257 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_RML(coreid)), 16); 258 octeon_wdt_write_string("\ten_rml\t0x"); 259 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_RML(coreid)), 16); 260 octeon_wdt_write_string("\r\n"); 261 octeon_wdt_write_string("\tsum\t0x"); 262 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)), 16); 263 octeon_wdt_write_string("\r\n"); 264 } else if (!octeon_has_feature(OCTEON_FEATURE_CIU3)) { 265 octeon_wdt_write_string("\tsum0\t0x"); 266 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16); 267 octeon_wdt_write_string("\ten0\t0x"); 268 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16); 269 octeon_wdt_write_string("\r\n"); 270 } 271 272 octeon_wdt_write_string("*** Chip soft reset soon ***\r\n"); 273 274 /* 275 * G-30204: We must trigger a soft reset before watchdog 276 * does an incomplete job of doing it. 277 */ 278 if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX)) { 279 u64 scr; 280 unsigned int node = cvmx_get_node_num(); 281 unsigned int lcore = cvmx_get_local_core_num(); 282 union cvmx_ciu_wdogx ciu_wdog; 283 284 /* 285 * Wait for other cores to print out information, but 286 * not too long. Do the soft reset before watchdog 287 * can trigger it. 288 */ 289 do { 290 ciu_wdog.u64 = cvmx_read_csr_node(node, CVMX_CIU_WDOGX(lcore)); 291 } while (ciu_wdog.s.cnt > 0x10000); 292 293 scr = cvmx_read_csr_node(0, CVMX_GSERX_SCRATCH(0)); 294 scr |= 1 << 11; /* Indicate watchdog in bit 11 */ 295 cvmx_write_csr_node(0, CVMX_GSERX_SCRATCH(0), scr); 296 cvmx_write_csr_node(0, CVMX_RST_SOFT_RST, 1); 297 } 298 } 299 300 static int octeon_wdt_cpu_to_irq(int cpu) 301 { 302 unsigned int coreid; 303 int node; 304 int irq; 305 306 coreid = cpu2core(cpu); 307 node = cpu_to_node(cpu); 308 309 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) { 310 struct irq_domain *domain; 311 int hwirq; 312 313 domain = octeon_irq_get_block_domain(node, 314 WD_BLOCK_NUMBER); 315 hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | coreid; 316 irq = irq_find_mapping(domain, hwirq); 317 } else { 318 irq = OCTEON_IRQ_WDOG0 + coreid; 319 } 320 return irq; 321 } 322 323 static int octeon_wdt_cpu_pre_down(unsigned int cpu) 324 { 325 unsigned int core; 326 int node; 327 union cvmx_ciu_wdogx ciu_wdog; 328 329 core = cpu2core(cpu); 330 331 node = cpu_to_node(cpu); 332 333 /* Poke the watchdog to clear out its state */ 334 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); 335 336 /* Disable the hardware. */ 337 ciu_wdog.u64 = 0; 338 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64); 339 340 free_irq(octeon_wdt_cpu_to_irq(cpu), octeon_wdt_poke_irq); 341 return 0; 342 } 343 344 static int octeon_wdt_cpu_online(unsigned int cpu) 345 { 346 unsigned int core; 347 unsigned int irq; 348 union cvmx_ciu_wdogx ciu_wdog; 349 int node; 350 struct irq_domain *domain; 351 int hwirq; 352 353 core = cpu2core(cpu); 354 node = cpu_to_node(cpu); 355 356 octeon_wdt_bootvector[core].target_ptr = (u64)octeon_wdt_nmi_stage2; 357 358 /* Disable it before doing anything with the interrupts. */ 359 ciu_wdog.u64 = 0; 360 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64); 361 362 per_cpu_countdown[cpu] = countdown_reset; 363 364 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) { 365 /* Must get the domain for the watchdog block */ 366 domain = octeon_irq_get_block_domain(node, WD_BLOCK_NUMBER); 367 368 /* Get a irq for the wd intsn (hardware interrupt) */ 369 hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | core; 370 irq = irq_create_mapping(domain, hwirq); 371 irqd_set_trigger_type(irq_get_irq_data(irq), 372 IRQ_TYPE_EDGE_RISING); 373 } else 374 irq = OCTEON_IRQ_WDOG0 + core; 375 376 if (request_irq(irq, octeon_wdt_poke_irq, 377 IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq)) 378 panic("octeon_wdt: Couldn't obtain irq %d", irq); 379 380 /* Must set the irq affinity here */ 381 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) { 382 cpumask_t mask; 383 384 cpumask_clear(&mask); 385 cpumask_set_cpu(cpu, &mask); 386 irq_set_affinity(irq, &mask); 387 } 388 389 cpumask_set_cpu(cpu, &irq_enabled_cpus); 390 391 /* Poke the watchdog to clear out its state */ 392 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); 393 394 /* Finally enable the watchdog now that all handlers are installed */ 395 ciu_wdog.u64 = 0; 396 ciu_wdog.s.len = timeout_cnt; 397 ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */ 398 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64); 399 400 return 0; 401 } 402 403 static int octeon_wdt_ping(struct watchdog_device __always_unused *wdog) 404 { 405 int cpu; 406 int coreid; 407 int node; 408 409 if (disable) 410 return 0; 411 412 for_each_online_cpu(cpu) { 413 coreid = cpu2core(cpu); 414 node = cpu_to_node(cpu); 415 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1); 416 per_cpu_countdown[cpu] = countdown_reset; 417 if ((countdown_reset || !do_countdown) && 418 !cpumask_test_cpu(cpu, &irq_enabled_cpus)) { 419 /* We have to enable the irq */ 420 enable_irq(octeon_wdt_cpu_to_irq(cpu)); 421 cpumask_set_cpu(cpu, &irq_enabled_cpus); 422 } 423 } 424 return 0; 425 } 426 427 static void octeon_wdt_calc_parameters(int t) 428 { 429 unsigned int periods; 430 431 timeout_sec = max_timeout_sec; 432 433 434 /* 435 * Find the largest interrupt period, that can evenly divide 436 * the requested heartbeat time. 437 */ 438 while ((t % timeout_sec) != 0) 439 timeout_sec--; 440 441 periods = t / timeout_sec; 442 443 /* 444 * The last two periods are after the irq is disabled, and 445 * then to the nmi, so we subtract them off. 446 */ 447 448 countdown_reset = periods > 2 ? periods - 2 : 0; 449 heartbeat = t; 450 timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * timeout_sec) >> 8; 451 } 452 453 static int octeon_wdt_set_timeout(struct watchdog_device *wdog, 454 unsigned int t) 455 { 456 int cpu; 457 int coreid; 458 union cvmx_ciu_wdogx ciu_wdog; 459 int node; 460 461 if (t <= 0) 462 return -1; 463 464 octeon_wdt_calc_parameters(t); 465 466 if (disable) 467 return 0; 468 469 for_each_online_cpu(cpu) { 470 coreid = cpu2core(cpu); 471 node = cpu_to_node(cpu); 472 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1); 473 ciu_wdog.u64 = 0; 474 ciu_wdog.s.len = timeout_cnt; 475 ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */ 476 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(coreid), ciu_wdog.u64); 477 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1); 478 } 479 octeon_wdt_ping(wdog); /* Get the irqs back on. */ 480 return 0; 481 } 482 483 static int octeon_wdt_start(struct watchdog_device *wdog) 484 { 485 octeon_wdt_ping(wdog); 486 do_countdown = 1; 487 return 0; 488 } 489 490 static int octeon_wdt_stop(struct watchdog_device *wdog) 491 { 492 do_countdown = 0; 493 octeon_wdt_ping(wdog); 494 return 0; 495 } 496 497 static const struct watchdog_info octeon_wdt_info = { 498 .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, 499 .identity = "OCTEON", 500 }; 501 502 static const struct watchdog_ops octeon_wdt_ops = { 503 .owner = THIS_MODULE, 504 .start = octeon_wdt_start, 505 .stop = octeon_wdt_stop, 506 .ping = octeon_wdt_ping, 507 .set_timeout = octeon_wdt_set_timeout, 508 }; 509 510 static struct watchdog_device octeon_wdt = { 511 .info = &octeon_wdt_info, 512 .ops = &octeon_wdt_ops, 513 }; 514 515 static enum cpuhp_state octeon_wdt_online; 516 /** 517 * Module/ driver initialization. 518 * 519 * Returns Zero on success 520 */ 521 static int __init octeon_wdt_init(void) 522 { 523 int ret; 524 525 octeon_wdt_bootvector = cvmx_boot_vector_get(); 526 if (!octeon_wdt_bootvector) { 527 pr_err("Error: Cannot allocate boot vector.\n"); 528 return -ENOMEM; 529 } 530 531 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 532 divisor = 0x200; 533 else if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 534 divisor = 0x400; 535 else 536 divisor = 0x100; 537 538 /* 539 * Watchdog time expiration length = The 16 bits of LEN 540 * represent the most significant bits of a 24 bit decrementer 541 * that decrements every divisor cycle. 542 * 543 * Try for a timeout of 5 sec, if that fails a smaller number 544 * of even seconds, 545 */ 546 max_timeout_sec = 6; 547 do { 548 max_timeout_sec--; 549 timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * max_timeout_sec) >> 8; 550 } while (timeout_cnt > 65535); 551 552 BUG_ON(timeout_cnt == 0); 553 554 octeon_wdt_calc_parameters(heartbeat); 555 556 pr_info("Initial granularity %d Sec\n", timeout_sec); 557 558 octeon_wdt.timeout = timeout_sec; 559 octeon_wdt.max_timeout = UINT_MAX; 560 561 watchdog_set_nowayout(&octeon_wdt, nowayout); 562 563 ret = watchdog_register_device(&octeon_wdt); 564 if (ret) { 565 pr_err("watchdog_register_device() failed: %d\n", ret); 566 return ret; 567 } 568 569 if (disable) { 570 pr_notice("disabled\n"); 571 return 0; 572 } 573 574 cpumask_clear(&irq_enabled_cpus); 575 576 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "watchdog/octeon:online", 577 octeon_wdt_cpu_online, octeon_wdt_cpu_pre_down); 578 if (ret < 0) 579 goto err; 580 octeon_wdt_online = ret; 581 return 0; 582 err: 583 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0); 584 watchdog_unregister_device(&octeon_wdt); 585 return ret; 586 } 587 588 /** 589 * Module / driver shutdown 590 */ 591 static void __exit octeon_wdt_cleanup(void) 592 { 593 watchdog_unregister_device(&octeon_wdt); 594 595 if (disable) 596 return; 597 598 cpuhp_remove_state(octeon_wdt_online); 599 600 /* 601 * Disable the boot-bus memory, the code it points to is soon 602 * to go missing. 603 */ 604 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0); 605 } 606 607 MODULE_LICENSE("GPL"); 608 MODULE_AUTHOR("Cavium Inc. <support@cavium.com>"); 609 MODULE_DESCRIPTION("Cavium Inc. OCTEON Watchdog driver."); 610 module_init(octeon_wdt_init); 611 module_exit(octeon_wdt_cleanup); 612