1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Octeon Watchdog driver 4 * 5 * Copyright (C) 2007-2017 Cavium, Inc. 6 * 7 * Converted to use WATCHDOG_CORE by Aaro Koskinen <aaro.koskinen@iki.fi>. 8 * 9 * Some parts derived from wdt.c 10 * 11 * (c) Copyright 1996-1997 Alan Cox <alan@lxorguk.ukuu.org.uk>, 12 * All Rights Reserved. 13 * 14 * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide 15 * warranty for any of this software. This material is provided 16 * "AS-IS" and at no charge. 17 * 18 * (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk> 19 * 20 * The OCTEON watchdog has a maximum timeout of 2^32 * io_clock. 21 * For most systems this is less than 10 seconds, so to allow for 22 * software to request longer watchdog heartbeats, we maintain software 23 * counters to count multiples of the base rate. If the system locks 24 * up in such a manner that we can not run the software counters, the 25 * only result is a watchdog reset sooner than was requested. But 26 * that is OK, because in this case userspace would likely not be able 27 * to do anything anyhow. 28 * 29 * The hardware watchdog interval we call the period. The OCTEON 30 * watchdog goes through several stages, after the first period an 31 * irq is asserted, then if it is not reset, after the next period NMI 32 * is asserted, then after an additional period a chip wide soft reset. 33 * So for the software counters, we reset watchdog after each period 34 * and decrement the counter. But for the last two periods we need to 35 * let the watchdog progress to the NMI stage so we disable the irq 36 * and let it proceed. Once in the NMI, we print the register state 37 * to the serial port and then wait for the reset. 38 * 39 * A watchdog is maintained for each CPU in the system, that way if 40 * one CPU suffers a lockup, we also get a register dump and reset. 41 * The userspace ping resets the watchdog on all CPUs. 42 * 43 * Before userspace opens the watchdog device, we still run the 44 * watchdogs to catch any lockups that may be kernel related. 45 * 46 */ 47 48 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 49 50 #include <linux/interrupt.h> 51 #include <linux/watchdog.h> 52 #include <linux/cpumask.h> 53 #include <linux/module.h> 54 #include <linux/delay.h> 55 #include <linux/cpu.h> 56 #include <linux/irq.h> 57 58 #include <asm/mipsregs.h> 59 #include <asm/uasm.h> 60 61 #include <asm/octeon/octeon.h> 62 #include <asm/octeon/cvmx-boot-vector.h> 63 #include <asm/octeon/cvmx-ciu2-defs.h> 64 #include <asm/octeon/cvmx-rst-defs.h> 65 66 /* Watchdog interrupt major block number (8 MSBs of intsn) */ 67 #define WD_BLOCK_NUMBER 0x01 68 69 static int divisor; 70 71 /* The count needed to achieve timeout_sec. */ 72 static unsigned int timeout_cnt; 73 74 /* The maximum period supported. */ 75 static unsigned int max_timeout_sec; 76 77 /* The current period. */ 78 static unsigned int timeout_sec; 79 80 /* Set to non-zero when userspace countdown mode active */ 81 static bool do_countdown; 82 static unsigned int countdown_reset; 83 static unsigned int per_cpu_countdown[NR_CPUS]; 84 85 static cpumask_t irq_enabled_cpus; 86 87 #define WD_TIMO 60 /* Default heartbeat = 60 seconds */ 88 89 #define CVMX_GSERX_SCRATCH(offset) (CVMX_ADD_IO_SEG(0x0001180090000020ull) + ((offset) & 15) * 0x1000000ull) 90 91 static int heartbeat = WD_TIMO; 92 module_param(heartbeat, int, 0444); 93 MODULE_PARM_DESC(heartbeat, 94 "Watchdog heartbeat in seconds. (0 < heartbeat, default=" 95 __MODULE_STRING(WD_TIMO) ")"); 96 97 static bool nowayout = WATCHDOG_NOWAYOUT; 98 module_param(nowayout, bool, 0444); 99 MODULE_PARM_DESC(nowayout, 100 "Watchdog cannot be stopped once started (default=" 101 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 102 103 static int disable; 104 module_param(disable, int, 0444); 105 MODULE_PARM_DESC(disable, 106 "Disable the watchdog entirely (default=0)"); 107 108 static struct cvmx_boot_vector_element *octeon_wdt_bootvector; 109 110 void octeon_wdt_nmi_stage2(void); 111 112 static int cpu2core(int cpu) 113 { 114 #ifdef CONFIG_SMP 115 return cpu_logical_map(cpu) & 0x3f; 116 #else 117 return cvmx_get_core_num(); 118 #endif 119 } 120 121 /** 122 * Poke the watchdog when an interrupt is received 123 * 124 * @cpl: 125 * @dev_id: 126 * 127 * Returns 128 */ 129 static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id) 130 { 131 int cpu = raw_smp_processor_id(); 132 unsigned int core = cpu2core(cpu); 133 int node = cpu_to_node(cpu); 134 135 if (do_countdown) { 136 if (per_cpu_countdown[cpu] > 0) { 137 /* We're alive, poke the watchdog */ 138 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); 139 per_cpu_countdown[cpu]--; 140 } else { 141 /* Bad news, you are about to reboot. */ 142 disable_irq_nosync(cpl); 143 cpumask_clear_cpu(cpu, &irq_enabled_cpus); 144 } 145 } else { 146 /* Not open, just ping away... */ 147 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); 148 } 149 return IRQ_HANDLED; 150 } 151 152 /* From setup.c */ 153 extern int prom_putchar(char c); 154 155 /** 156 * Write a string to the uart 157 * 158 * @str: String to write 159 */ 160 static void octeon_wdt_write_string(const char *str) 161 { 162 /* Just loop writing one byte at a time */ 163 while (*str) 164 prom_putchar(*str++); 165 } 166 167 /** 168 * Write a hex number out of the uart 169 * 170 * @value: Number to display 171 * @digits: Number of digits to print (1 to 16) 172 */ 173 static void octeon_wdt_write_hex(u64 value, int digits) 174 { 175 int d; 176 int v; 177 178 for (d = 0; d < digits; d++) { 179 v = (value >> ((digits - d - 1) * 4)) & 0xf; 180 if (v >= 10) 181 prom_putchar('a' + v - 10); 182 else 183 prom_putchar('0' + v); 184 } 185 } 186 187 static const char reg_name[][3] = { 188 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", 189 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", 190 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 191 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 192 }; 193 194 /** 195 * NMI stage 3 handler. NMIs are handled in the following manner: 196 * 1) The first NMI handler enables CVMSEG and transfers from 197 * the bootbus region into normal memory. It is careful to not 198 * destroy any registers. 199 * 2) The second stage handler uses CVMSEG to save the registers 200 * and create a stack for C code. It then calls the third level 201 * handler with one argument, a pointer to the register values. 202 * 3) The third, and final, level handler is the following C 203 * function that prints out some useful infomration. 204 * 205 * @reg: Pointer to register state before the NMI 206 */ 207 void octeon_wdt_nmi_stage3(u64 reg[32]) 208 { 209 u64 i; 210 211 unsigned int coreid = cvmx_get_core_num(); 212 /* 213 * Save status and cause early to get them before any changes 214 * might happen. 215 */ 216 u64 cp0_cause = read_c0_cause(); 217 u64 cp0_status = read_c0_status(); 218 u64 cp0_error_epc = read_c0_errorepc(); 219 u64 cp0_epc = read_c0_epc(); 220 221 /* Delay so output from all cores output is not jumbled together. */ 222 udelay(85000 * coreid); 223 224 octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x"); 225 octeon_wdt_write_hex(coreid, 2); 226 octeon_wdt_write_string(" ***\r\n"); 227 for (i = 0; i < 32; i++) { 228 octeon_wdt_write_string("\t"); 229 octeon_wdt_write_string(reg_name[i]); 230 octeon_wdt_write_string("\t0x"); 231 octeon_wdt_write_hex(reg[i], 16); 232 if (i & 1) 233 octeon_wdt_write_string("\r\n"); 234 } 235 octeon_wdt_write_string("\terr_epc\t0x"); 236 octeon_wdt_write_hex(cp0_error_epc, 16); 237 238 octeon_wdt_write_string("\tepc\t0x"); 239 octeon_wdt_write_hex(cp0_epc, 16); 240 octeon_wdt_write_string("\r\n"); 241 242 octeon_wdt_write_string("\tstatus\t0x"); 243 octeon_wdt_write_hex(cp0_status, 16); 244 octeon_wdt_write_string("\tcause\t0x"); 245 octeon_wdt_write_hex(cp0_cause, 16); 246 octeon_wdt_write_string("\r\n"); 247 248 /* The CIU register is different for each Octeon model. */ 249 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { 250 octeon_wdt_write_string("\tsrc_wd\t0x"); 251 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_WDOG(coreid)), 16); 252 octeon_wdt_write_string("\ten_wd\t0x"); 253 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_WDOG(coreid)), 16); 254 octeon_wdt_write_string("\r\n"); 255 octeon_wdt_write_string("\tsrc_rml\t0x"); 256 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_RML(coreid)), 16); 257 octeon_wdt_write_string("\ten_rml\t0x"); 258 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_RML(coreid)), 16); 259 octeon_wdt_write_string("\r\n"); 260 octeon_wdt_write_string("\tsum\t0x"); 261 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)), 16); 262 octeon_wdt_write_string("\r\n"); 263 } else if (!octeon_has_feature(OCTEON_FEATURE_CIU3)) { 264 octeon_wdt_write_string("\tsum0\t0x"); 265 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16); 266 octeon_wdt_write_string("\ten0\t0x"); 267 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16); 268 octeon_wdt_write_string("\r\n"); 269 } 270 271 octeon_wdt_write_string("*** Chip soft reset soon ***\r\n"); 272 273 /* 274 * G-30204: We must trigger a soft reset before watchdog 275 * does an incomplete job of doing it. 276 */ 277 if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX)) { 278 u64 scr; 279 unsigned int node = cvmx_get_node_num(); 280 unsigned int lcore = cvmx_get_local_core_num(); 281 union cvmx_ciu_wdogx ciu_wdog; 282 283 /* 284 * Wait for other cores to print out information, but 285 * not too long. Do the soft reset before watchdog 286 * can trigger it. 287 */ 288 do { 289 ciu_wdog.u64 = cvmx_read_csr_node(node, CVMX_CIU_WDOGX(lcore)); 290 } while (ciu_wdog.s.cnt > 0x10000); 291 292 scr = cvmx_read_csr_node(0, CVMX_GSERX_SCRATCH(0)); 293 scr |= 1 << 11; /* Indicate watchdog in bit 11 */ 294 cvmx_write_csr_node(0, CVMX_GSERX_SCRATCH(0), scr); 295 cvmx_write_csr_node(0, CVMX_RST_SOFT_RST, 1); 296 } 297 } 298 299 static int octeon_wdt_cpu_to_irq(int cpu) 300 { 301 unsigned int coreid; 302 int node; 303 int irq; 304 305 coreid = cpu2core(cpu); 306 node = cpu_to_node(cpu); 307 308 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) { 309 struct irq_domain *domain; 310 int hwirq; 311 312 domain = octeon_irq_get_block_domain(node, 313 WD_BLOCK_NUMBER); 314 hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | coreid; 315 irq = irq_find_mapping(domain, hwirq); 316 } else { 317 irq = OCTEON_IRQ_WDOG0 + coreid; 318 } 319 return irq; 320 } 321 322 static int octeon_wdt_cpu_pre_down(unsigned int cpu) 323 { 324 unsigned int core; 325 int node; 326 union cvmx_ciu_wdogx ciu_wdog; 327 328 core = cpu2core(cpu); 329 330 node = cpu_to_node(cpu); 331 332 /* Poke the watchdog to clear out its state */ 333 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); 334 335 /* Disable the hardware. */ 336 ciu_wdog.u64 = 0; 337 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64); 338 339 free_irq(octeon_wdt_cpu_to_irq(cpu), octeon_wdt_poke_irq); 340 return 0; 341 } 342 343 static int octeon_wdt_cpu_online(unsigned int cpu) 344 { 345 unsigned int core; 346 unsigned int irq; 347 union cvmx_ciu_wdogx ciu_wdog; 348 int node; 349 struct irq_domain *domain; 350 int hwirq; 351 352 core = cpu2core(cpu); 353 node = cpu_to_node(cpu); 354 355 octeon_wdt_bootvector[core].target_ptr = (u64)octeon_wdt_nmi_stage2; 356 357 /* Disable it before doing anything with the interrupts. */ 358 ciu_wdog.u64 = 0; 359 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64); 360 361 per_cpu_countdown[cpu] = countdown_reset; 362 363 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) { 364 /* Must get the domain for the watchdog block */ 365 domain = octeon_irq_get_block_domain(node, WD_BLOCK_NUMBER); 366 367 /* Get a irq for the wd intsn (hardware interrupt) */ 368 hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | core; 369 irq = irq_create_mapping(domain, hwirq); 370 irqd_set_trigger_type(irq_get_irq_data(irq), 371 IRQ_TYPE_EDGE_RISING); 372 } else 373 irq = OCTEON_IRQ_WDOG0 + core; 374 375 if (request_irq(irq, octeon_wdt_poke_irq, 376 IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq)) 377 panic("octeon_wdt: Couldn't obtain irq %d", irq); 378 379 /* Must set the irq affinity here */ 380 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) { 381 cpumask_t mask; 382 383 cpumask_clear(&mask); 384 cpumask_set_cpu(cpu, &mask); 385 irq_set_affinity(irq, &mask); 386 } 387 388 cpumask_set_cpu(cpu, &irq_enabled_cpus); 389 390 /* Poke the watchdog to clear out its state */ 391 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); 392 393 /* Finally enable the watchdog now that all handlers are installed */ 394 ciu_wdog.u64 = 0; 395 ciu_wdog.s.len = timeout_cnt; 396 ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */ 397 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64); 398 399 return 0; 400 } 401 402 static int octeon_wdt_ping(struct watchdog_device __always_unused *wdog) 403 { 404 int cpu; 405 int coreid; 406 int node; 407 408 if (disable) 409 return 0; 410 411 for_each_online_cpu(cpu) { 412 coreid = cpu2core(cpu); 413 node = cpu_to_node(cpu); 414 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1); 415 per_cpu_countdown[cpu] = countdown_reset; 416 if ((countdown_reset || !do_countdown) && 417 !cpumask_test_cpu(cpu, &irq_enabled_cpus)) { 418 /* We have to enable the irq */ 419 enable_irq(octeon_wdt_cpu_to_irq(cpu)); 420 cpumask_set_cpu(cpu, &irq_enabled_cpus); 421 } 422 } 423 return 0; 424 } 425 426 static void octeon_wdt_calc_parameters(int t) 427 { 428 unsigned int periods; 429 430 timeout_sec = max_timeout_sec; 431 432 433 /* 434 * Find the largest interrupt period, that can evenly divide 435 * the requested heartbeat time. 436 */ 437 while ((t % timeout_sec) != 0) 438 timeout_sec--; 439 440 periods = t / timeout_sec; 441 442 /* 443 * The last two periods are after the irq is disabled, and 444 * then to the nmi, so we subtract them off. 445 */ 446 447 countdown_reset = periods > 2 ? periods - 2 : 0; 448 heartbeat = t; 449 timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * timeout_sec) >> 8; 450 } 451 452 static int octeon_wdt_set_timeout(struct watchdog_device *wdog, 453 unsigned int t) 454 { 455 int cpu; 456 int coreid; 457 union cvmx_ciu_wdogx ciu_wdog; 458 int node; 459 460 if (t <= 0) 461 return -1; 462 463 octeon_wdt_calc_parameters(t); 464 465 if (disable) 466 return 0; 467 468 for_each_online_cpu(cpu) { 469 coreid = cpu2core(cpu); 470 node = cpu_to_node(cpu); 471 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1); 472 ciu_wdog.u64 = 0; 473 ciu_wdog.s.len = timeout_cnt; 474 ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */ 475 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(coreid), ciu_wdog.u64); 476 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1); 477 } 478 octeon_wdt_ping(wdog); /* Get the irqs back on. */ 479 return 0; 480 } 481 482 static int octeon_wdt_start(struct watchdog_device *wdog) 483 { 484 octeon_wdt_ping(wdog); 485 do_countdown = 1; 486 return 0; 487 } 488 489 static int octeon_wdt_stop(struct watchdog_device *wdog) 490 { 491 do_countdown = 0; 492 octeon_wdt_ping(wdog); 493 return 0; 494 } 495 496 static const struct watchdog_info octeon_wdt_info = { 497 .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, 498 .identity = "OCTEON", 499 }; 500 501 static const struct watchdog_ops octeon_wdt_ops = { 502 .owner = THIS_MODULE, 503 .start = octeon_wdt_start, 504 .stop = octeon_wdt_stop, 505 .ping = octeon_wdt_ping, 506 .set_timeout = octeon_wdt_set_timeout, 507 }; 508 509 static struct watchdog_device octeon_wdt = { 510 .info = &octeon_wdt_info, 511 .ops = &octeon_wdt_ops, 512 }; 513 514 static enum cpuhp_state octeon_wdt_online; 515 /** 516 * Module/ driver initialization. 517 * 518 * Returns Zero on success 519 */ 520 static int __init octeon_wdt_init(void) 521 { 522 int ret; 523 524 octeon_wdt_bootvector = cvmx_boot_vector_get(); 525 if (!octeon_wdt_bootvector) { 526 pr_err("Error: Cannot allocate boot vector.\n"); 527 return -ENOMEM; 528 } 529 530 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 531 divisor = 0x200; 532 else if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 533 divisor = 0x400; 534 else 535 divisor = 0x100; 536 537 /* 538 * Watchdog time expiration length = The 16 bits of LEN 539 * represent the most significant bits of a 24 bit decrementer 540 * that decrements every divisor cycle. 541 * 542 * Try for a timeout of 5 sec, if that fails a smaller number 543 * of even seconds, 544 */ 545 max_timeout_sec = 6; 546 do { 547 max_timeout_sec--; 548 timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * max_timeout_sec) >> 8; 549 } while (timeout_cnt > 65535); 550 551 BUG_ON(timeout_cnt == 0); 552 553 octeon_wdt_calc_parameters(heartbeat); 554 555 pr_info("Initial granularity %d Sec\n", timeout_sec); 556 557 octeon_wdt.timeout = timeout_sec; 558 octeon_wdt.max_timeout = UINT_MAX; 559 560 watchdog_set_nowayout(&octeon_wdt, nowayout); 561 562 ret = watchdog_register_device(&octeon_wdt); 563 if (ret) { 564 pr_err("watchdog_register_device() failed: %d\n", ret); 565 return ret; 566 } 567 568 if (disable) { 569 pr_notice("disabled\n"); 570 return 0; 571 } 572 573 cpumask_clear(&irq_enabled_cpus); 574 575 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "watchdog/octeon:online", 576 octeon_wdt_cpu_online, octeon_wdt_cpu_pre_down); 577 if (ret < 0) 578 goto err; 579 octeon_wdt_online = ret; 580 return 0; 581 err: 582 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0); 583 watchdog_unregister_device(&octeon_wdt); 584 return ret; 585 } 586 587 /** 588 * Module / driver shutdown 589 */ 590 static void __exit octeon_wdt_cleanup(void) 591 { 592 watchdog_unregister_device(&octeon_wdt); 593 594 if (disable) 595 return; 596 597 cpuhp_remove_state(octeon_wdt_online); 598 599 /* 600 * Disable the boot-bus memory, the code it points to is soon 601 * to go missing. 602 */ 603 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0); 604 } 605 606 MODULE_LICENSE("GPL"); 607 MODULE_AUTHOR("Cavium Inc. <support@cavium.com>"); 608 MODULE_DESCRIPTION("Cavium Inc. OCTEON Watchdog driver."); 609 module_init(octeon_wdt_init); 610 module_exit(octeon_wdt_cleanup); 611