1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * nv_tco: TCO timer driver for nVidia chipsets. 4 * 5 * (c) Copyright 2005 Google Inc., All Rights Reserved. 6 * 7 * Supported Chipsets: 8 * - MCP51/MCP55 9 * 10 * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights 11 * Reserved. 12 * https://www.kernelconcepts.de 13 * 14 * Neither kernel concepts nor Nils Faerber admit liability nor provide 15 * warranty for any of this software. This material is provided 16 * "AS-IS" and at no charge. 17 * 18 * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de> 19 * developed for 20 * Jentro AG, Haar/Munich (Germany) 21 * 22 * TCO timer driver for NV chipsets 23 * based on softdog.c by Alan Cox <alan@redhat.com> 24 */ 25 26 /* 27 * Some address definitions for the TCO 28 */ 29 30 #define TCO_RLD(base) ((base) + 0x00) /* TCO Timer Reload and Current Value */ 31 #define TCO_TMR(base) ((base) + 0x01) /* TCO Timer Initial Value */ 32 33 #define TCO_STS(base) ((base) + 0x04) /* TCO Status Register */ 34 /* 35 * TCO Boot Status bit: set on TCO reset, reset by software or standby 36 * power-good (survives reboots), unfortunately this bit is never 37 * set. 38 */ 39 # define TCO_STS_BOOT_STS (1 << 9) 40 /* 41 * first and 2nd timeout status bits, these also survive a warm boot, 42 * and they work, so we use them. 43 */ 44 # define TCO_STS_TCO_INT_STS (1 << 1) 45 # define TCO_STS_TCO2TO_STS (1 << 10) 46 # define TCO_STS_RESET (TCO_STS_BOOT_STS | TCO_STS_TCO2TO_STS | \ 47 TCO_STS_TCO_INT_STS) 48 49 #define TCO_CNT(base) ((base) + 0x08) /* TCO Control Register */ 50 # define TCO_CNT_TCOHALT (1 << 12) 51 52 #define MCP51_SMBUS_SETUP_B 0xe8 53 # define MCP51_SMBUS_SETUP_B_TCO_REBOOT (1 << 25) 54 55 /* 56 * The SMI_EN register is at the base io address + 0x04, 57 * while TCOBASE is + 0x40. 58 */ 59 #define MCP51_SMI_EN(base) ((base) - 0x40 + 0x04) 60 # define MCP51_SMI_EN_TCO ((1 << 4) | (1 << 5)) 61