1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Mediatek Watchdog Driver 4 * 5 * Copyright (C) 2014 Matthias Brugger 6 * 7 * Matthias Brugger <matthias.bgg@gmail.com> 8 * 9 * Based on sunxi_wdt.c 10 */ 11 12 #include <dt-bindings/reset/mt2712-resets.h> 13 #include <dt-bindings/reset/mediatek,mt6795-resets.h> 14 #include <dt-bindings/reset/mt7986-resets.h> 15 #include <dt-bindings/reset/mt8183-resets.h> 16 #include <dt-bindings/reset/mt8186-resets.h> 17 #include <dt-bindings/reset/mt8188-resets.h> 18 #include <dt-bindings/reset/mt8192-resets.h> 19 #include <dt-bindings/reset/mt8195-resets.h> 20 #include <linux/delay.h> 21 #include <linux/err.h> 22 #include <linux/init.h> 23 #include <linux/io.h> 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/moduleparam.h> 27 #include <linux/of.h> 28 #include <linux/of_device.h> 29 #include <linux/platform_device.h> 30 #include <linux/reset-controller.h> 31 #include <linux/types.h> 32 #include <linux/watchdog.h> 33 #include <linux/interrupt.h> 34 35 #define WDT_MAX_TIMEOUT 31 36 #define WDT_MIN_TIMEOUT 2 37 #define WDT_LENGTH_TIMEOUT(n) ((n) << 5) 38 39 #define WDT_LENGTH 0x04 40 #define WDT_LENGTH_KEY 0x8 41 42 #define WDT_RST 0x08 43 #define WDT_RST_RELOAD 0x1971 44 45 #define WDT_MODE 0x00 46 #define WDT_MODE_EN (1 << 0) 47 #define WDT_MODE_EXT_POL_LOW (0 << 1) 48 #define WDT_MODE_EXT_POL_HIGH (1 << 1) 49 #define WDT_MODE_EXRST_EN (1 << 2) 50 #define WDT_MODE_IRQ_EN (1 << 3) 51 #define WDT_MODE_AUTO_START (1 << 4) 52 #define WDT_MODE_DUAL_EN (1 << 6) 53 #define WDT_MODE_KEY 0x22000000 54 55 #define WDT_SWRST 0x14 56 #define WDT_SWRST_KEY 0x1209 57 58 #define WDT_SWSYSRST 0x18U 59 #define WDT_SWSYS_RST_KEY 0x88000000 60 61 #define DRV_NAME "mtk-wdt" 62 #define DRV_VERSION "1.0" 63 64 static bool nowayout = WATCHDOG_NOWAYOUT; 65 static unsigned int timeout; 66 67 struct mtk_wdt_dev { 68 struct watchdog_device wdt_dev; 69 void __iomem *wdt_base; 70 spinlock_t lock; /* protects WDT_SWSYSRST reg */ 71 struct reset_controller_dev rcdev; 72 bool disable_wdt_extrst; 73 }; 74 75 struct mtk_wdt_data { 76 int toprgu_sw_rst_num; 77 }; 78 79 static const struct mtk_wdt_data mt2712_data = { 80 .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM, 81 }; 82 83 static const struct mtk_wdt_data mt6795_data = { 84 .toprgu_sw_rst_num = MT6795_TOPRGU_SW_RST_NUM, 85 }; 86 87 static const struct mtk_wdt_data mt7986_data = { 88 .toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM, 89 }; 90 91 static const struct mtk_wdt_data mt8183_data = { 92 .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, 93 }; 94 95 static const struct mtk_wdt_data mt8186_data = { 96 .toprgu_sw_rst_num = MT8186_TOPRGU_SW_RST_NUM, 97 }; 98 99 static const struct mtk_wdt_data mt8188_data = { 100 .toprgu_sw_rst_num = MT8188_TOPRGU_SW_RST_NUM, 101 }; 102 103 static const struct mtk_wdt_data mt8192_data = { 104 .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM, 105 }; 106 107 static const struct mtk_wdt_data mt8195_data = { 108 .toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM, 109 }; 110 111 static int toprgu_reset_update(struct reset_controller_dev *rcdev, 112 unsigned long id, bool assert) 113 { 114 unsigned int tmp; 115 unsigned long flags; 116 struct mtk_wdt_dev *data = 117 container_of(rcdev, struct mtk_wdt_dev, rcdev); 118 119 spin_lock_irqsave(&data->lock, flags); 120 121 tmp = readl(data->wdt_base + WDT_SWSYSRST); 122 if (assert) 123 tmp |= BIT(id); 124 else 125 tmp &= ~BIT(id); 126 tmp |= WDT_SWSYS_RST_KEY; 127 writel(tmp, data->wdt_base + WDT_SWSYSRST); 128 129 spin_unlock_irqrestore(&data->lock, flags); 130 131 return 0; 132 } 133 134 static int toprgu_reset_assert(struct reset_controller_dev *rcdev, 135 unsigned long id) 136 { 137 return toprgu_reset_update(rcdev, id, true); 138 } 139 140 static int toprgu_reset_deassert(struct reset_controller_dev *rcdev, 141 unsigned long id) 142 { 143 return toprgu_reset_update(rcdev, id, false); 144 } 145 146 static int toprgu_reset(struct reset_controller_dev *rcdev, 147 unsigned long id) 148 { 149 int ret; 150 151 ret = toprgu_reset_assert(rcdev, id); 152 if (ret) 153 return ret; 154 155 return toprgu_reset_deassert(rcdev, id); 156 } 157 158 static const struct reset_control_ops toprgu_reset_ops = { 159 .assert = toprgu_reset_assert, 160 .deassert = toprgu_reset_deassert, 161 .reset = toprgu_reset, 162 }; 163 164 static int toprgu_register_reset_controller(struct platform_device *pdev, 165 int rst_num) 166 { 167 int ret; 168 struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev); 169 170 spin_lock_init(&mtk_wdt->lock); 171 172 mtk_wdt->rcdev.owner = THIS_MODULE; 173 mtk_wdt->rcdev.nr_resets = rst_num; 174 mtk_wdt->rcdev.ops = &toprgu_reset_ops; 175 mtk_wdt->rcdev.of_node = pdev->dev.of_node; 176 ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev); 177 if (ret != 0) 178 dev_err(&pdev->dev, 179 "couldn't register wdt reset controller: %d\n", ret); 180 return ret; 181 } 182 183 static int mtk_wdt_restart(struct watchdog_device *wdt_dev, 184 unsigned long action, void *data) 185 { 186 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 187 void __iomem *wdt_base; 188 189 wdt_base = mtk_wdt->wdt_base; 190 191 while (1) { 192 writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST); 193 mdelay(5); 194 } 195 196 return 0; 197 } 198 199 static int mtk_wdt_ping(struct watchdog_device *wdt_dev) 200 { 201 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 202 void __iomem *wdt_base = mtk_wdt->wdt_base; 203 204 iowrite32(WDT_RST_RELOAD, wdt_base + WDT_RST); 205 206 return 0; 207 } 208 209 static int mtk_wdt_set_timeout(struct watchdog_device *wdt_dev, 210 unsigned int timeout) 211 { 212 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 213 void __iomem *wdt_base = mtk_wdt->wdt_base; 214 u32 reg; 215 216 wdt_dev->timeout = timeout; 217 /* 218 * In dual mode, irq will be triggered at timeout / 2 219 * the real timeout occurs at timeout 220 */ 221 if (wdt_dev->pretimeout) 222 wdt_dev->pretimeout = timeout / 2; 223 224 /* 225 * One bit is the value of 512 ticks 226 * The clock has 32 KHz 227 */ 228 reg = WDT_LENGTH_TIMEOUT((timeout - wdt_dev->pretimeout) << 6) 229 | WDT_LENGTH_KEY; 230 iowrite32(reg, wdt_base + WDT_LENGTH); 231 232 mtk_wdt_ping(wdt_dev); 233 234 return 0; 235 } 236 237 static void mtk_wdt_init(struct watchdog_device *wdt_dev) 238 { 239 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 240 void __iomem *wdt_base; 241 242 wdt_base = mtk_wdt->wdt_base; 243 244 if (readl(wdt_base + WDT_MODE) & WDT_MODE_EN) { 245 set_bit(WDOG_HW_RUNNING, &wdt_dev->status); 246 mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout); 247 } 248 } 249 250 static int mtk_wdt_stop(struct watchdog_device *wdt_dev) 251 { 252 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 253 void __iomem *wdt_base = mtk_wdt->wdt_base; 254 u32 reg; 255 256 reg = readl(wdt_base + WDT_MODE); 257 reg &= ~WDT_MODE_EN; 258 reg |= WDT_MODE_KEY; 259 iowrite32(reg, wdt_base + WDT_MODE); 260 261 return 0; 262 } 263 264 static int mtk_wdt_start(struct watchdog_device *wdt_dev) 265 { 266 u32 reg; 267 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 268 void __iomem *wdt_base = mtk_wdt->wdt_base; 269 int ret; 270 271 ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout); 272 if (ret < 0) 273 return ret; 274 275 reg = ioread32(wdt_base + WDT_MODE); 276 if (wdt_dev->pretimeout) 277 reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); 278 else 279 reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); 280 if (mtk_wdt->disable_wdt_extrst) 281 reg &= ~WDT_MODE_EXRST_EN; 282 reg |= (WDT_MODE_EN | WDT_MODE_KEY); 283 iowrite32(reg, wdt_base + WDT_MODE); 284 285 return 0; 286 } 287 288 static int mtk_wdt_set_pretimeout(struct watchdog_device *wdd, 289 unsigned int timeout) 290 { 291 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdd); 292 void __iomem *wdt_base = mtk_wdt->wdt_base; 293 u32 reg = ioread32(wdt_base + WDT_MODE); 294 295 if (timeout && !wdd->pretimeout) { 296 wdd->pretimeout = wdd->timeout / 2; 297 reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); 298 } else if (!timeout && wdd->pretimeout) { 299 wdd->pretimeout = 0; 300 reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); 301 } else { 302 return 0; 303 } 304 305 reg |= WDT_MODE_KEY; 306 iowrite32(reg, wdt_base + WDT_MODE); 307 308 return mtk_wdt_set_timeout(wdd, wdd->timeout); 309 } 310 311 static irqreturn_t mtk_wdt_isr(int irq, void *arg) 312 { 313 struct watchdog_device *wdd = arg; 314 315 watchdog_notify_pretimeout(wdd); 316 317 return IRQ_HANDLED; 318 } 319 320 static const struct watchdog_info mtk_wdt_info = { 321 .identity = DRV_NAME, 322 .options = WDIOF_SETTIMEOUT | 323 WDIOF_KEEPALIVEPING | 324 WDIOF_MAGICCLOSE, 325 }; 326 327 static const struct watchdog_info mtk_wdt_pt_info = { 328 .identity = DRV_NAME, 329 .options = WDIOF_SETTIMEOUT | 330 WDIOF_PRETIMEOUT | 331 WDIOF_KEEPALIVEPING | 332 WDIOF_MAGICCLOSE, 333 }; 334 335 static const struct watchdog_ops mtk_wdt_ops = { 336 .owner = THIS_MODULE, 337 .start = mtk_wdt_start, 338 .stop = mtk_wdt_stop, 339 .ping = mtk_wdt_ping, 340 .set_timeout = mtk_wdt_set_timeout, 341 .set_pretimeout = mtk_wdt_set_pretimeout, 342 .restart = mtk_wdt_restart, 343 }; 344 345 static int mtk_wdt_probe(struct platform_device *pdev) 346 { 347 struct device *dev = &pdev->dev; 348 struct mtk_wdt_dev *mtk_wdt; 349 const struct mtk_wdt_data *wdt_data; 350 int err, irq; 351 352 mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL); 353 if (!mtk_wdt) 354 return -ENOMEM; 355 356 platform_set_drvdata(pdev, mtk_wdt); 357 358 mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0); 359 if (IS_ERR(mtk_wdt->wdt_base)) 360 return PTR_ERR(mtk_wdt->wdt_base); 361 362 irq = platform_get_irq_optional(pdev, 0); 363 if (irq > 0) { 364 err = devm_request_irq(&pdev->dev, irq, mtk_wdt_isr, 0, "wdt_bark", 365 &mtk_wdt->wdt_dev); 366 if (err) 367 return err; 368 369 mtk_wdt->wdt_dev.info = &mtk_wdt_pt_info; 370 mtk_wdt->wdt_dev.pretimeout = WDT_MAX_TIMEOUT / 2; 371 } else { 372 if (irq == -EPROBE_DEFER) 373 return -EPROBE_DEFER; 374 375 mtk_wdt->wdt_dev.info = &mtk_wdt_info; 376 } 377 378 mtk_wdt->wdt_dev.ops = &mtk_wdt_ops; 379 mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT; 380 mtk_wdt->wdt_dev.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT * 1000; 381 mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT; 382 mtk_wdt->wdt_dev.parent = dev; 383 384 watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev); 385 watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout); 386 watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128); 387 388 watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt); 389 390 mtk_wdt_init(&mtk_wdt->wdt_dev); 391 392 watchdog_stop_on_reboot(&mtk_wdt->wdt_dev); 393 err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev); 394 if (unlikely(err)) 395 return err; 396 397 dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n", 398 mtk_wdt->wdt_dev.timeout, nowayout); 399 400 wdt_data = of_device_get_match_data(dev); 401 if (wdt_data) { 402 err = toprgu_register_reset_controller(pdev, 403 wdt_data->toprgu_sw_rst_num); 404 if (err) 405 return err; 406 } 407 408 mtk_wdt->disable_wdt_extrst = 409 of_property_read_bool(dev->of_node, "mediatek,disable-extrst"); 410 411 return 0; 412 } 413 414 static int mtk_wdt_suspend(struct device *dev) 415 { 416 struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev); 417 418 if (watchdog_active(&mtk_wdt->wdt_dev)) 419 mtk_wdt_stop(&mtk_wdt->wdt_dev); 420 421 return 0; 422 } 423 424 static int mtk_wdt_resume(struct device *dev) 425 { 426 struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev); 427 428 if (watchdog_active(&mtk_wdt->wdt_dev)) { 429 mtk_wdt_start(&mtk_wdt->wdt_dev); 430 mtk_wdt_ping(&mtk_wdt->wdt_dev); 431 } 432 433 return 0; 434 } 435 436 static const struct of_device_id mtk_wdt_dt_ids[] = { 437 { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, 438 { .compatible = "mediatek,mt6589-wdt" }, 439 { .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data }, 440 { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data }, 441 { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, 442 { .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data }, 443 { .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data }, 444 { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data }, 445 { .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data }, 446 { /* sentinel */ } 447 }; 448 MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids); 449 450 static DEFINE_SIMPLE_DEV_PM_OPS(mtk_wdt_pm_ops, 451 mtk_wdt_suspend, mtk_wdt_resume); 452 453 static struct platform_driver mtk_wdt_driver = { 454 .probe = mtk_wdt_probe, 455 .driver = { 456 .name = DRV_NAME, 457 .pm = pm_sleep_ptr(&mtk_wdt_pm_ops), 458 .of_match_table = mtk_wdt_dt_ids, 459 }, 460 }; 461 462 module_platform_driver(mtk_wdt_driver); 463 464 module_param(timeout, uint, 0); 465 MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds"); 466 467 module_param(nowayout, bool, 0); 468 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" 469 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 470 471 MODULE_LICENSE("GPL"); 472 MODULE_AUTHOR("Matthias Brugger <matthias.bgg@gmail.com>"); 473 MODULE_DESCRIPTION("Mediatek WatchDog Timer Driver"); 474 MODULE_VERSION(DRV_VERSION); 475