1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Mediatek Watchdog Driver 4 * 5 * Copyright (C) 2014 Matthias Brugger 6 * 7 * Matthias Brugger <matthias.bgg@gmail.com> 8 * 9 * Based on sunxi_wdt.c 10 */ 11 12 #include <dt-bindings/reset/mt2712-resets.h> 13 #include <dt-bindings/reset/mt8183-resets.h> 14 #include <dt-bindings/reset/mt8192-resets.h> 15 #include <dt-bindings/reset/mt8195-resets.h> 16 #include <linux/delay.h> 17 #include <linux/err.h> 18 #include <linux/init.h> 19 #include <linux/io.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/platform_device.h> 26 #include <linux/reset-controller.h> 27 #include <linux/types.h> 28 #include <linux/watchdog.h> 29 #include <linux/interrupt.h> 30 31 #define WDT_MAX_TIMEOUT 31 32 #define WDT_MIN_TIMEOUT 2 33 #define WDT_LENGTH_TIMEOUT(n) ((n) << 5) 34 35 #define WDT_LENGTH 0x04 36 #define WDT_LENGTH_KEY 0x8 37 38 #define WDT_RST 0x08 39 #define WDT_RST_RELOAD 0x1971 40 41 #define WDT_MODE 0x00 42 #define WDT_MODE_EN (1 << 0) 43 #define WDT_MODE_EXT_POL_LOW (0 << 1) 44 #define WDT_MODE_EXT_POL_HIGH (1 << 1) 45 #define WDT_MODE_EXRST_EN (1 << 2) 46 #define WDT_MODE_IRQ_EN (1 << 3) 47 #define WDT_MODE_AUTO_START (1 << 4) 48 #define WDT_MODE_DUAL_EN (1 << 6) 49 #define WDT_MODE_KEY 0x22000000 50 51 #define WDT_SWRST 0x14 52 #define WDT_SWRST_KEY 0x1209 53 54 #define WDT_SWSYSRST 0x18U 55 #define WDT_SWSYS_RST_KEY 0x88000000 56 57 #define DRV_NAME "mtk-wdt" 58 #define DRV_VERSION "1.0" 59 60 static bool nowayout = WATCHDOG_NOWAYOUT; 61 static unsigned int timeout; 62 63 struct mtk_wdt_dev { 64 struct watchdog_device wdt_dev; 65 void __iomem *wdt_base; 66 spinlock_t lock; /* protects WDT_SWSYSRST reg */ 67 struct reset_controller_dev rcdev; 68 bool disable_wdt_extrst; 69 }; 70 71 struct mtk_wdt_data { 72 int toprgu_sw_rst_num; 73 }; 74 75 static const struct mtk_wdt_data mt2712_data = { 76 .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM, 77 }; 78 79 static const struct mtk_wdt_data mt8183_data = { 80 .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, 81 }; 82 83 static const struct mtk_wdt_data mt8192_data = { 84 .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM, 85 }; 86 87 static const struct mtk_wdt_data mt8195_data = { 88 .toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM, 89 }; 90 91 static int toprgu_reset_update(struct reset_controller_dev *rcdev, 92 unsigned long id, bool assert) 93 { 94 unsigned int tmp; 95 unsigned long flags; 96 struct mtk_wdt_dev *data = 97 container_of(rcdev, struct mtk_wdt_dev, rcdev); 98 99 spin_lock_irqsave(&data->lock, flags); 100 101 tmp = readl(data->wdt_base + WDT_SWSYSRST); 102 if (assert) 103 tmp |= BIT(id); 104 else 105 tmp &= ~BIT(id); 106 tmp |= WDT_SWSYS_RST_KEY; 107 writel(tmp, data->wdt_base + WDT_SWSYSRST); 108 109 spin_unlock_irqrestore(&data->lock, flags); 110 111 return 0; 112 } 113 114 static int toprgu_reset_assert(struct reset_controller_dev *rcdev, 115 unsigned long id) 116 { 117 return toprgu_reset_update(rcdev, id, true); 118 } 119 120 static int toprgu_reset_deassert(struct reset_controller_dev *rcdev, 121 unsigned long id) 122 { 123 return toprgu_reset_update(rcdev, id, false); 124 } 125 126 static int toprgu_reset(struct reset_controller_dev *rcdev, 127 unsigned long id) 128 { 129 int ret; 130 131 ret = toprgu_reset_assert(rcdev, id); 132 if (ret) 133 return ret; 134 135 return toprgu_reset_deassert(rcdev, id); 136 } 137 138 static const struct reset_control_ops toprgu_reset_ops = { 139 .assert = toprgu_reset_assert, 140 .deassert = toprgu_reset_deassert, 141 .reset = toprgu_reset, 142 }; 143 144 static int toprgu_register_reset_controller(struct platform_device *pdev, 145 int rst_num) 146 { 147 int ret; 148 struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev); 149 150 spin_lock_init(&mtk_wdt->lock); 151 152 mtk_wdt->rcdev.owner = THIS_MODULE; 153 mtk_wdt->rcdev.nr_resets = rst_num; 154 mtk_wdt->rcdev.ops = &toprgu_reset_ops; 155 mtk_wdt->rcdev.of_node = pdev->dev.of_node; 156 ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev); 157 if (ret != 0) 158 dev_err(&pdev->dev, 159 "couldn't register wdt reset controller: %d\n", ret); 160 return ret; 161 } 162 163 static int mtk_wdt_restart(struct watchdog_device *wdt_dev, 164 unsigned long action, void *data) 165 { 166 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 167 void __iomem *wdt_base; 168 169 wdt_base = mtk_wdt->wdt_base; 170 171 while (1) { 172 writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST); 173 mdelay(5); 174 } 175 176 return 0; 177 } 178 179 static int mtk_wdt_ping(struct watchdog_device *wdt_dev) 180 { 181 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 182 void __iomem *wdt_base = mtk_wdt->wdt_base; 183 184 iowrite32(WDT_RST_RELOAD, wdt_base + WDT_RST); 185 186 return 0; 187 } 188 189 static int mtk_wdt_set_timeout(struct watchdog_device *wdt_dev, 190 unsigned int timeout) 191 { 192 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 193 void __iomem *wdt_base = mtk_wdt->wdt_base; 194 u32 reg; 195 196 wdt_dev->timeout = timeout; 197 /* 198 * In dual mode, irq will be triggered at timeout / 2 199 * the real timeout occurs at timeout 200 */ 201 if (wdt_dev->pretimeout) 202 wdt_dev->pretimeout = timeout / 2; 203 204 /* 205 * One bit is the value of 512 ticks 206 * The clock has 32 KHz 207 */ 208 reg = WDT_LENGTH_TIMEOUT((timeout - wdt_dev->pretimeout) << 6) 209 | WDT_LENGTH_KEY; 210 iowrite32(reg, wdt_base + WDT_LENGTH); 211 212 mtk_wdt_ping(wdt_dev); 213 214 return 0; 215 } 216 217 static void mtk_wdt_init(struct watchdog_device *wdt_dev) 218 { 219 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 220 void __iomem *wdt_base; 221 222 wdt_base = mtk_wdt->wdt_base; 223 224 if (readl(wdt_base + WDT_MODE) & WDT_MODE_EN) { 225 set_bit(WDOG_HW_RUNNING, &wdt_dev->status); 226 mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout); 227 } 228 } 229 230 static int mtk_wdt_stop(struct watchdog_device *wdt_dev) 231 { 232 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 233 void __iomem *wdt_base = mtk_wdt->wdt_base; 234 u32 reg; 235 236 reg = readl(wdt_base + WDT_MODE); 237 reg &= ~WDT_MODE_EN; 238 reg |= WDT_MODE_KEY; 239 iowrite32(reg, wdt_base + WDT_MODE); 240 241 return 0; 242 } 243 244 static int mtk_wdt_start(struct watchdog_device *wdt_dev) 245 { 246 u32 reg; 247 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 248 void __iomem *wdt_base = mtk_wdt->wdt_base; 249 int ret; 250 251 ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout); 252 if (ret < 0) 253 return ret; 254 255 reg = ioread32(wdt_base + WDT_MODE); 256 if (wdt_dev->pretimeout) 257 reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); 258 else 259 reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); 260 if (mtk_wdt->disable_wdt_extrst) 261 reg &= ~WDT_MODE_EXRST_EN; 262 reg |= (WDT_MODE_EN | WDT_MODE_KEY); 263 iowrite32(reg, wdt_base + WDT_MODE); 264 265 return 0; 266 } 267 268 static int mtk_wdt_set_pretimeout(struct watchdog_device *wdd, 269 unsigned int timeout) 270 { 271 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdd); 272 void __iomem *wdt_base = mtk_wdt->wdt_base; 273 u32 reg = ioread32(wdt_base + WDT_MODE); 274 275 if (timeout && !wdd->pretimeout) { 276 wdd->pretimeout = wdd->timeout / 2; 277 reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); 278 } else if (!timeout && wdd->pretimeout) { 279 wdd->pretimeout = 0; 280 reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); 281 } else { 282 return 0; 283 } 284 285 reg |= WDT_MODE_KEY; 286 iowrite32(reg, wdt_base + WDT_MODE); 287 288 return mtk_wdt_set_timeout(wdd, wdd->timeout); 289 } 290 291 static irqreturn_t mtk_wdt_isr(int irq, void *arg) 292 { 293 struct watchdog_device *wdd = arg; 294 295 watchdog_notify_pretimeout(wdd); 296 297 return IRQ_HANDLED; 298 } 299 300 static const struct watchdog_info mtk_wdt_info = { 301 .identity = DRV_NAME, 302 .options = WDIOF_SETTIMEOUT | 303 WDIOF_KEEPALIVEPING | 304 WDIOF_MAGICCLOSE, 305 }; 306 307 static const struct watchdog_info mtk_wdt_pt_info = { 308 .identity = DRV_NAME, 309 .options = WDIOF_SETTIMEOUT | 310 WDIOF_PRETIMEOUT | 311 WDIOF_KEEPALIVEPING | 312 WDIOF_MAGICCLOSE, 313 }; 314 315 static const struct watchdog_ops mtk_wdt_ops = { 316 .owner = THIS_MODULE, 317 .start = mtk_wdt_start, 318 .stop = mtk_wdt_stop, 319 .ping = mtk_wdt_ping, 320 .set_timeout = mtk_wdt_set_timeout, 321 .set_pretimeout = mtk_wdt_set_pretimeout, 322 .restart = mtk_wdt_restart, 323 }; 324 325 static int mtk_wdt_probe(struct platform_device *pdev) 326 { 327 struct device *dev = &pdev->dev; 328 struct mtk_wdt_dev *mtk_wdt; 329 const struct mtk_wdt_data *wdt_data; 330 int err, irq; 331 332 mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL); 333 if (!mtk_wdt) 334 return -ENOMEM; 335 336 platform_set_drvdata(pdev, mtk_wdt); 337 338 mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0); 339 if (IS_ERR(mtk_wdt->wdt_base)) 340 return PTR_ERR(mtk_wdt->wdt_base); 341 342 irq = platform_get_irq(pdev, 0); 343 if (irq > 0) { 344 err = devm_request_irq(&pdev->dev, irq, mtk_wdt_isr, 0, "wdt_bark", 345 &mtk_wdt->wdt_dev); 346 if (err) 347 return err; 348 349 mtk_wdt->wdt_dev.info = &mtk_wdt_pt_info; 350 mtk_wdt->wdt_dev.pretimeout = WDT_MAX_TIMEOUT / 2; 351 } else { 352 if (irq == -EPROBE_DEFER) 353 return -EPROBE_DEFER; 354 355 mtk_wdt->wdt_dev.info = &mtk_wdt_info; 356 } 357 358 mtk_wdt->wdt_dev.ops = &mtk_wdt_ops; 359 mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT; 360 mtk_wdt->wdt_dev.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT * 1000; 361 mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT; 362 mtk_wdt->wdt_dev.parent = dev; 363 364 watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev); 365 watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout); 366 watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128); 367 368 watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt); 369 370 mtk_wdt_init(&mtk_wdt->wdt_dev); 371 372 watchdog_stop_on_reboot(&mtk_wdt->wdt_dev); 373 err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev); 374 if (unlikely(err)) 375 return err; 376 377 dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n", 378 mtk_wdt->wdt_dev.timeout, nowayout); 379 380 wdt_data = of_device_get_match_data(dev); 381 if (wdt_data) { 382 err = toprgu_register_reset_controller(pdev, 383 wdt_data->toprgu_sw_rst_num); 384 if (err) 385 return err; 386 } 387 388 mtk_wdt->disable_wdt_extrst = 389 of_property_read_bool(dev->of_node, "mediatek,disable-extrst"); 390 391 return 0; 392 } 393 394 #ifdef CONFIG_PM_SLEEP 395 static int mtk_wdt_suspend(struct device *dev) 396 { 397 struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev); 398 399 if (watchdog_active(&mtk_wdt->wdt_dev)) 400 mtk_wdt_stop(&mtk_wdt->wdt_dev); 401 402 return 0; 403 } 404 405 static int mtk_wdt_resume(struct device *dev) 406 { 407 struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev); 408 409 if (watchdog_active(&mtk_wdt->wdt_dev)) { 410 mtk_wdt_start(&mtk_wdt->wdt_dev); 411 mtk_wdt_ping(&mtk_wdt->wdt_dev); 412 } 413 414 return 0; 415 } 416 #endif 417 418 static const struct of_device_id mtk_wdt_dt_ids[] = { 419 { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, 420 { .compatible = "mediatek,mt6589-wdt" }, 421 { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, 422 { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data }, 423 { .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data }, 424 { /* sentinel */ } 425 }; 426 MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids); 427 428 static const struct dev_pm_ops mtk_wdt_pm_ops = { 429 SET_SYSTEM_SLEEP_PM_OPS(mtk_wdt_suspend, 430 mtk_wdt_resume) 431 }; 432 433 static struct platform_driver mtk_wdt_driver = { 434 .probe = mtk_wdt_probe, 435 .driver = { 436 .name = DRV_NAME, 437 .pm = &mtk_wdt_pm_ops, 438 .of_match_table = mtk_wdt_dt_ids, 439 }, 440 }; 441 442 module_platform_driver(mtk_wdt_driver); 443 444 module_param(timeout, uint, 0); 445 MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds"); 446 447 module_param(nowayout, bool, 0); 448 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" 449 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 450 451 MODULE_LICENSE("GPL"); 452 MODULE_AUTHOR("Matthias Brugger <matthias.bgg@gmail.com>"); 453 MODULE_DESCRIPTION("Mediatek WatchDog Timer Driver"); 454 MODULE_VERSION(DRV_VERSION); 455