1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Mediatek Watchdog Driver 4 * 5 * Copyright (C) 2014 Matthias Brugger 6 * 7 * Matthias Brugger <matthias.bgg@gmail.com> 8 * 9 * Based on sunxi_wdt.c 10 */ 11 12 #include <dt-bindings/reset/mt2712-resets.h> 13 #include <dt-bindings/reset/mt7986-resets.h> 14 #include <dt-bindings/reset/mt8183-resets.h> 15 #include <dt-bindings/reset/mt8186-resets.h> 16 #include <dt-bindings/reset/mt8192-resets.h> 17 #include <dt-bindings/reset/mt8195-resets.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/init.h> 21 #include <linux/io.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/moduleparam.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 #include <linux/platform_device.h> 28 #include <linux/reset-controller.h> 29 #include <linux/types.h> 30 #include <linux/watchdog.h> 31 #include <linux/interrupt.h> 32 33 #define WDT_MAX_TIMEOUT 31 34 #define WDT_MIN_TIMEOUT 2 35 #define WDT_LENGTH_TIMEOUT(n) ((n) << 5) 36 37 #define WDT_LENGTH 0x04 38 #define WDT_LENGTH_KEY 0x8 39 40 #define WDT_RST 0x08 41 #define WDT_RST_RELOAD 0x1971 42 43 #define WDT_MODE 0x00 44 #define WDT_MODE_EN (1 << 0) 45 #define WDT_MODE_EXT_POL_LOW (0 << 1) 46 #define WDT_MODE_EXT_POL_HIGH (1 << 1) 47 #define WDT_MODE_EXRST_EN (1 << 2) 48 #define WDT_MODE_IRQ_EN (1 << 3) 49 #define WDT_MODE_AUTO_START (1 << 4) 50 #define WDT_MODE_DUAL_EN (1 << 6) 51 #define WDT_MODE_KEY 0x22000000 52 53 #define WDT_SWRST 0x14 54 #define WDT_SWRST_KEY 0x1209 55 56 #define WDT_SWSYSRST 0x18U 57 #define WDT_SWSYS_RST_KEY 0x88000000 58 59 #define DRV_NAME "mtk-wdt" 60 #define DRV_VERSION "1.0" 61 62 static bool nowayout = WATCHDOG_NOWAYOUT; 63 static unsigned int timeout; 64 65 struct mtk_wdt_dev { 66 struct watchdog_device wdt_dev; 67 void __iomem *wdt_base; 68 spinlock_t lock; /* protects WDT_SWSYSRST reg */ 69 struct reset_controller_dev rcdev; 70 bool disable_wdt_extrst; 71 }; 72 73 struct mtk_wdt_data { 74 int toprgu_sw_rst_num; 75 }; 76 77 static const struct mtk_wdt_data mt2712_data = { 78 .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM, 79 }; 80 81 static const struct mtk_wdt_data mt7986_data = { 82 .toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM, 83 }; 84 85 static const struct mtk_wdt_data mt8183_data = { 86 .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, 87 }; 88 89 static const struct mtk_wdt_data mt8186_data = { 90 .toprgu_sw_rst_num = MT8186_TOPRGU_SW_RST_NUM, 91 }; 92 93 static const struct mtk_wdt_data mt8192_data = { 94 .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM, 95 }; 96 97 static const struct mtk_wdt_data mt8195_data = { 98 .toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM, 99 }; 100 101 static int toprgu_reset_update(struct reset_controller_dev *rcdev, 102 unsigned long id, bool assert) 103 { 104 unsigned int tmp; 105 unsigned long flags; 106 struct mtk_wdt_dev *data = 107 container_of(rcdev, struct mtk_wdt_dev, rcdev); 108 109 spin_lock_irqsave(&data->lock, flags); 110 111 tmp = readl(data->wdt_base + WDT_SWSYSRST); 112 if (assert) 113 tmp |= BIT(id); 114 else 115 tmp &= ~BIT(id); 116 tmp |= WDT_SWSYS_RST_KEY; 117 writel(tmp, data->wdt_base + WDT_SWSYSRST); 118 119 spin_unlock_irqrestore(&data->lock, flags); 120 121 return 0; 122 } 123 124 static int toprgu_reset_assert(struct reset_controller_dev *rcdev, 125 unsigned long id) 126 { 127 return toprgu_reset_update(rcdev, id, true); 128 } 129 130 static int toprgu_reset_deassert(struct reset_controller_dev *rcdev, 131 unsigned long id) 132 { 133 return toprgu_reset_update(rcdev, id, false); 134 } 135 136 static int toprgu_reset(struct reset_controller_dev *rcdev, 137 unsigned long id) 138 { 139 int ret; 140 141 ret = toprgu_reset_assert(rcdev, id); 142 if (ret) 143 return ret; 144 145 return toprgu_reset_deassert(rcdev, id); 146 } 147 148 static const struct reset_control_ops toprgu_reset_ops = { 149 .assert = toprgu_reset_assert, 150 .deassert = toprgu_reset_deassert, 151 .reset = toprgu_reset, 152 }; 153 154 static int toprgu_register_reset_controller(struct platform_device *pdev, 155 int rst_num) 156 { 157 int ret; 158 struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev); 159 160 spin_lock_init(&mtk_wdt->lock); 161 162 mtk_wdt->rcdev.owner = THIS_MODULE; 163 mtk_wdt->rcdev.nr_resets = rst_num; 164 mtk_wdt->rcdev.ops = &toprgu_reset_ops; 165 mtk_wdt->rcdev.of_node = pdev->dev.of_node; 166 ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev); 167 if (ret != 0) 168 dev_err(&pdev->dev, 169 "couldn't register wdt reset controller: %d\n", ret); 170 return ret; 171 } 172 173 static int mtk_wdt_restart(struct watchdog_device *wdt_dev, 174 unsigned long action, void *data) 175 { 176 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 177 void __iomem *wdt_base; 178 179 wdt_base = mtk_wdt->wdt_base; 180 181 while (1) { 182 writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST); 183 mdelay(5); 184 } 185 186 return 0; 187 } 188 189 static int mtk_wdt_ping(struct watchdog_device *wdt_dev) 190 { 191 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 192 void __iomem *wdt_base = mtk_wdt->wdt_base; 193 194 iowrite32(WDT_RST_RELOAD, wdt_base + WDT_RST); 195 196 return 0; 197 } 198 199 static int mtk_wdt_set_timeout(struct watchdog_device *wdt_dev, 200 unsigned int timeout) 201 { 202 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 203 void __iomem *wdt_base = mtk_wdt->wdt_base; 204 u32 reg; 205 206 wdt_dev->timeout = timeout; 207 /* 208 * In dual mode, irq will be triggered at timeout / 2 209 * the real timeout occurs at timeout 210 */ 211 if (wdt_dev->pretimeout) 212 wdt_dev->pretimeout = timeout / 2; 213 214 /* 215 * One bit is the value of 512 ticks 216 * The clock has 32 KHz 217 */ 218 reg = WDT_LENGTH_TIMEOUT((timeout - wdt_dev->pretimeout) << 6) 219 | WDT_LENGTH_KEY; 220 iowrite32(reg, wdt_base + WDT_LENGTH); 221 222 mtk_wdt_ping(wdt_dev); 223 224 return 0; 225 } 226 227 static void mtk_wdt_init(struct watchdog_device *wdt_dev) 228 { 229 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 230 void __iomem *wdt_base; 231 232 wdt_base = mtk_wdt->wdt_base; 233 234 if (readl(wdt_base + WDT_MODE) & WDT_MODE_EN) { 235 set_bit(WDOG_HW_RUNNING, &wdt_dev->status); 236 mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout); 237 } 238 } 239 240 static int mtk_wdt_stop(struct watchdog_device *wdt_dev) 241 { 242 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 243 void __iomem *wdt_base = mtk_wdt->wdt_base; 244 u32 reg; 245 246 reg = readl(wdt_base + WDT_MODE); 247 reg &= ~WDT_MODE_EN; 248 reg |= WDT_MODE_KEY; 249 iowrite32(reg, wdt_base + WDT_MODE); 250 251 return 0; 252 } 253 254 static int mtk_wdt_start(struct watchdog_device *wdt_dev) 255 { 256 u32 reg; 257 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 258 void __iomem *wdt_base = mtk_wdt->wdt_base; 259 int ret; 260 261 ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout); 262 if (ret < 0) 263 return ret; 264 265 reg = ioread32(wdt_base + WDT_MODE); 266 if (wdt_dev->pretimeout) 267 reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); 268 else 269 reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); 270 if (mtk_wdt->disable_wdt_extrst) 271 reg &= ~WDT_MODE_EXRST_EN; 272 reg |= (WDT_MODE_EN | WDT_MODE_KEY); 273 iowrite32(reg, wdt_base + WDT_MODE); 274 275 return 0; 276 } 277 278 static int mtk_wdt_set_pretimeout(struct watchdog_device *wdd, 279 unsigned int timeout) 280 { 281 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdd); 282 void __iomem *wdt_base = mtk_wdt->wdt_base; 283 u32 reg = ioread32(wdt_base + WDT_MODE); 284 285 if (timeout && !wdd->pretimeout) { 286 wdd->pretimeout = wdd->timeout / 2; 287 reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); 288 } else if (!timeout && wdd->pretimeout) { 289 wdd->pretimeout = 0; 290 reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); 291 } else { 292 return 0; 293 } 294 295 reg |= WDT_MODE_KEY; 296 iowrite32(reg, wdt_base + WDT_MODE); 297 298 return mtk_wdt_set_timeout(wdd, wdd->timeout); 299 } 300 301 static irqreturn_t mtk_wdt_isr(int irq, void *arg) 302 { 303 struct watchdog_device *wdd = arg; 304 305 watchdog_notify_pretimeout(wdd); 306 307 return IRQ_HANDLED; 308 } 309 310 static const struct watchdog_info mtk_wdt_info = { 311 .identity = DRV_NAME, 312 .options = WDIOF_SETTIMEOUT | 313 WDIOF_KEEPALIVEPING | 314 WDIOF_MAGICCLOSE, 315 }; 316 317 static const struct watchdog_info mtk_wdt_pt_info = { 318 .identity = DRV_NAME, 319 .options = WDIOF_SETTIMEOUT | 320 WDIOF_PRETIMEOUT | 321 WDIOF_KEEPALIVEPING | 322 WDIOF_MAGICCLOSE, 323 }; 324 325 static const struct watchdog_ops mtk_wdt_ops = { 326 .owner = THIS_MODULE, 327 .start = mtk_wdt_start, 328 .stop = mtk_wdt_stop, 329 .ping = mtk_wdt_ping, 330 .set_timeout = mtk_wdt_set_timeout, 331 .set_pretimeout = mtk_wdt_set_pretimeout, 332 .restart = mtk_wdt_restart, 333 }; 334 335 static int mtk_wdt_probe(struct platform_device *pdev) 336 { 337 struct device *dev = &pdev->dev; 338 struct mtk_wdt_dev *mtk_wdt; 339 const struct mtk_wdt_data *wdt_data; 340 int err, irq; 341 342 mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL); 343 if (!mtk_wdt) 344 return -ENOMEM; 345 346 platform_set_drvdata(pdev, mtk_wdt); 347 348 mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0); 349 if (IS_ERR(mtk_wdt->wdt_base)) 350 return PTR_ERR(mtk_wdt->wdt_base); 351 352 irq = platform_get_irq_optional(pdev, 0); 353 if (irq > 0) { 354 err = devm_request_irq(&pdev->dev, irq, mtk_wdt_isr, 0, "wdt_bark", 355 &mtk_wdt->wdt_dev); 356 if (err) 357 return err; 358 359 mtk_wdt->wdt_dev.info = &mtk_wdt_pt_info; 360 mtk_wdt->wdt_dev.pretimeout = WDT_MAX_TIMEOUT / 2; 361 } else { 362 if (irq == -EPROBE_DEFER) 363 return -EPROBE_DEFER; 364 365 mtk_wdt->wdt_dev.info = &mtk_wdt_info; 366 } 367 368 mtk_wdt->wdt_dev.ops = &mtk_wdt_ops; 369 mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT; 370 mtk_wdt->wdt_dev.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT * 1000; 371 mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT; 372 mtk_wdt->wdt_dev.parent = dev; 373 374 watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev); 375 watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout); 376 watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128); 377 378 watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt); 379 380 mtk_wdt_init(&mtk_wdt->wdt_dev); 381 382 watchdog_stop_on_reboot(&mtk_wdt->wdt_dev); 383 err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev); 384 if (unlikely(err)) 385 return err; 386 387 dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n", 388 mtk_wdt->wdt_dev.timeout, nowayout); 389 390 wdt_data = of_device_get_match_data(dev); 391 if (wdt_data) { 392 err = toprgu_register_reset_controller(pdev, 393 wdt_data->toprgu_sw_rst_num); 394 if (err) 395 return err; 396 } 397 398 mtk_wdt->disable_wdt_extrst = 399 of_property_read_bool(dev->of_node, "mediatek,disable-extrst"); 400 401 return 0; 402 } 403 404 #ifdef CONFIG_PM_SLEEP 405 static int mtk_wdt_suspend(struct device *dev) 406 { 407 struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev); 408 409 if (watchdog_active(&mtk_wdt->wdt_dev)) 410 mtk_wdt_stop(&mtk_wdt->wdt_dev); 411 412 return 0; 413 } 414 415 static int mtk_wdt_resume(struct device *dev) 416 { 417 struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev); 418 419 if (watchdog_active(&mtk_wdt->wdt_dev)) { 420 mtk_wdt_start(&mtk_wdt->wdt_dev); 421 mtk_wdt_ping(&mtk_wdt->wdt_dev); 422 } 423 424 return 0; 425 } 426 #endif 427 428 static const struct of_device_id mtk_wdt_dt_ids[] = { 429 { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, 430 { .compatible = "mediatek,mt6589-wdt" }, 431 { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data }, 432 { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, 433 { .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data }, 434 { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data }, 435 { .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data }, 436 { /* sentinel */ } 437 }; 438 MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids); 439 440 static const struct dev_pm_ops mtk_wdt_pm_ops = { 441 SET_SYSTEM_SLEEP_PM_OPS(mtk_wdt_suspend, 442 mtk_wdt_resume) 443 }; 444 445 static struct platform_driver mtk_wdt_driver = { 446 .probe = mtk_wdt_probe, 447 .driver = { 448 .name = DRV_NAME, 449 .pm = &mtk_wdt_pm_ops, 450 .of_match_table = mtk_wdt_dt_ids, 451 }, 452 }; 453 454 module_platform_driver(mtk_wdt_driver); 455 456 module_param(timeout, uint, 0); 457 MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds"); 458 459 module_param(nowayout, bool, 0); 460 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" 461 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 462 463 MODULE_LICENSE("GPL"); 464 MODULE_AUTHOR("Matthias Brugger <matthias.bgg@gmail.com>"); 465 MODULE_DESCRIPTION("Mediatek WatchDog Timer Driver"); 466 MODULE_VERSION(DRV_VERSION); 467