1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Mediatek Watchdog Driver 4 * 5 * Copyright (C) 2014 Matthias Brugger 6 * 7 * Matthias Brugger <matthias.bgg@gmail.com> 8 * 9 * Based on sunxi_wdt.c 10 */ 11 12 #include <dt-bindings/reset/mt2712-resets.h> 13 #include <dt-bindings/reset/mediatek,mt6795-resets.h> 14 #include <dt-bindings/reset/mt7986-resets.h> 15 #include <dt-bindings/reset/mt8183-resets.h> 16 #include <dt-bindings/reset/mt8186-resets.h> 17 #include <dt-bindings/reset/mt8188-resets.h> 18 #include <dt-bindings/reset/mt8192-resets.h> 19 #include <dt-bindings/reset/mt8195-resets.h> 20 #include <linux/delay.h> 21 #include <linux/err.h> 22 #include <linux/init.h> 23 #include <linux/io.h> 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/moduleparam.h> 27 #include <linux/of.h> 28 #include <linux/platform_device.h> 29 #include <linux/reset-controller.h> 30 #include <linux/types.h> 31 #include <linux/watchdog.h> 32 #include <linux/interrupt.h> 33 34 #define WDT_MAX_TIMEOUT 31 35 #define WDT_MIN_TIMEOUT 2 36 #define WDT_LENGTH_TIMEOUT(n) ((n) << 5) 37 38 #define WDT_LENGTH 0x04 39 #define WDT_LENGTH_KEY 0x8 40 41 #define WDT_RST 0x08 42 #define WDT_RST_RELOAD 0x1971 43 44 #define WDT_MODE 0x00 45 #define WDT_MODE_EN (1 << 0) 46 #define WDT_MODE_EXT_POL_LOW (0 << 1) 47 #define WDT_MODE_EXT_POL_HIGH (1 << 1) 48 #define WDT_MODE_EXRST_EN (1 << 2) 49 #define WDT_MODE_IRQ_EN (1 << 3) 50 #define WDT_MODE_AUTO_START (1 << 4) 51 #define WDT_MODE_DUAL_EN (1 << 6) 52 #define WDT_MODE_CNT_SEL (1 << 8) 53 #define WDT_MODE_KEY 0x22000000 54 55 #define WDT_SWRST 0x14 56 #define WDT_SWRST_KEY 0x1209 57 58 #define WDT_SWSYSRST 0x18U 59 #define WDT_SWSYS_RST_KEY 0x88000000 60 61 #define DRV_NAME "mtk-wdt" 62 #define DRV_VERSION "1.0" 63 64 static bool nowayout = WATCHDOG_NOWAYOUT; 65 static unsigned int timeout; 66 67 struct mtk_wdt_dev { 68 struct watchdog_device wdt_dev; 69 void __iomem *wdt_base; 70 spinlock_t lock; /* protects WDT_SWSYSRST reg */ 71 struct reset_controller_dev rcdev; 72 bool disable_wdt_extrst; 73 bool reset_by_toprgu; 74 }; 75 76 struct mtk_wdt_data { 77 int toprgu_sw_rst_num; 78 }; 79 80 static const struct mtk_wdt_data mt2712_data = { 81 .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM, 82 }; 83 84 static const struct mtk_wdt_data mt6795_data = { 85 .toprgu_sw_rst_num = MT6795_TOPRGU_SW_RST_NUM, 86 }; 87 88 static const struct mtk_wdt_data mt7986_data = { 89 .toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM, 90 }; 91 92 static const struct mtk_wdt_data mt8183_data = { 93 .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, 94 }; 95 96 static const struct mtk_wdt_data mt8186_data = { 97 .toprgu_sw_rst_num = MT8186_TOPRGU_SW_RST_NUM, 98 }; 99 100 static const struct mtk_wdt_data mt8188_data = { 101 .toprgu_sw_rst_num = MT8188_TOPRGU_SW_RST_NUM, 102 }; 103 104 static const struct mtk_wdt_data mt8192_data = { 105 .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM, 106 }; 107 108 static const struct mtk_wdt_data mt8195_data = { 109 .toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM, 110 }; 111 112 static int toprgu_reset_update(struct reset_controller_dev *rcdev, 113 unsigned long id, bool assert) 114 { 115 unsigned int tmp; 116 unsigned long flags; 117 struct mtk_wdt_dev *data = 118 container_of(rcdev, struct mtk_wdt_dev, rcdev); 119 120 spin_lock_irqsave(&data->lock, flags); 121 122 tmp = readl(data->wdt_base + WDT_SWSYSRST); 123 if (assert) 124 tmp |= BIT(id); 125 else 126 tmp &= ~BIT(id); 127 tmp |= WDT_SWSYS_RST_KEY; 128 writel(tmp, data->wdt_base + WDT_SWSYSRST); 129 130 spin_unlock_irqrestore(&data->lock, flags); 131 132 return 0; 133 } 134 135 static int toprgu_reset_assert(struct reset_controller_dev *rcdev, 136 unsigned long id) 137 { 138 return toprgu_reset_update(rcdev, id, true); 139 } 140 141 static int toprgu_reset_deassert(struct reset_controller_dev *rcdev, 142 unsigned long id) 143 { 144 return toprgu_reset_update(rcdev, id, false); 145 } 146 147 static int toprgu_reset(struct reset_controller_dev *rcdev, 148 unsigned long id) 149 { 150 int ret; 151 152 ret = toprgu_reset_assert(rcdev, id); 153 if (ret) 154 return ret; 155 156 return toprgu_reset_deassert(rcdev, id); 157 } 158 159 static const struct reset_control_ops toprgu_reset_ops = { 160 .assert = toprgu_reset_assert, 161 .deassert = toprgu_reset_deassert, 162 .reset = toprgu_reset, 163 }; 164 165 static int toprgu_register_reset_controller(struct platform_device *pdev, 166 int rst_num) 167 { 168 int ret; 169 struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev); 170 171 spin_lock_init(&mtk_wdt->lock); 172 173 mtk_wdt->rcdev.owner = THIS_MODULE; 174 mtk_wdt->rcdev.nr_resets = rst_num; 175 mtk_wdt->rcdev.ops = &toprgu_reset_ops; 176 mtk_wdt->rcdev.of_node = pdev->dev.of_node; 177 ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev); 178 if (ret != 0) 179 dev_err(&pdev->dev, 180 "couldn't register wdt reset controller: %d\n", ret); 181 return ret; 182 } 183 184 static int mtk_wdt_restart(struct watchdog_device *wdt_dev, 185 unsigned long action, void *data) 186 { 187 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 188 void __iomem *wdt_base; 189 u32 reg; 190 191 wdt_base = mtk_wdt->wdt_base; 192 193 /* Enable reset in order to issue a system reset instead of an IRQ */ 194 reg = readl(wdt_base + WDT_MODE); 195 reg &= ~WDT_MODE_IRQ_EN; 196 writel(reg | WDT_MODE_KEY, wdt_base + WDT_MODE); 197 198 while (1) { 199 writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST); 200 mdelay(5); 201 } 202 203 return 0; 204 } 205 206 static int mtk_wdt_ping(struct watchdog_device *wdt_dev) 207 { 208 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 209 void __iomem *wdt_base = mtk_wdt->wdt_base; 210 211 iowrite32(WDT_RST_RELOAD, wdt_base + WDT_RST); 212 213 return 0; 214 } 215 216 static int mtk_wdt_set_timeout(struct watchdog_device *wdt_dev, 217 unsigned int timeout) 218 { 219 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 220 void __iomem *wdt_base = mtk_wdt->wdt_base; 221 u32 reg; 222 223 wdt_dev->timeout = timeout; 224 /* 225 * In dual mode, irq will be triggered at timeout / 2 226 * the real timeout occurs at timeout 227 */ 228 if (wdt_dev->pretimeout) 229 wdt_dev->pretimeout = timeout / 2; 230 231 /* 232 * One bit is the value of 512 ticks 233 * The clock has 32 KHz 234 */ 235 reg = WDT_LENGTH_TIMEOUT((timeout - wdt_dev->pretimeout) << 6) 236 | WDT_LENGTH_KEY; 237 iowrite32(reg, wdt_base + WDT_LENGTH); 238 239 mtk_wdt_ping(wdt_dev); 240 241 return 0; 242 } 243 244 static void mtk_wdt_init(struct watchdog_device *wdt_dev) 245 { 246 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 247 void __iomem *wdt_base; 248 249 wdt_base = mtk_wdt->wdt_base; 250 251 if (readl(wdt_base + WDT_MODE) & WDT_MODE_EN) { 252 set_bit(WDOG_HW_RUNNING, &wdt_dev->status); 253 mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout); 254 } 255 } 256 257 static int mtk_wdt_stop(struct watchdog_device *wdt_dev) 258 { 259 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 260 void __iomem *wdt_base = mtk_wdt->wdt_base; 261 u32 reg; 262 263 reg = readl(wdt_base + WDT_MODE); 264 reg &= ~WDT_MODE_EN; 265 reg |= WDT_MODE_KEY; 266 iowrite32(reg, wdt_base + WDT_MODE); 267 268 return 0; 269 } 270 271 static int mtk_wdt_start(struct watchdog_device *wdt_dev) 272 { 273 u32 reg; 274 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev); 275 void __iomem *wdt_base = mtk_wdt->wdt_base; 276 int ret; 277 278 ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout); 279 if (ret < 0) 280 return ret; 281 282 reg = ioread32(wdt_base + WDT_MODE); 283 if (wdt_dev->pretimeout) 284 reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); 285 else 286 reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); 287 if (mtk_wdt->disable_wdt_extrst) 288 reg &= ~WDT_MODE_EXRST_EN; 289 if (mtk_wdt->reset_by_toprgu) 290 reg |= WDT_MODE_CNT_SEL; 291 reg |= (WDT_MODE_EN | WDT_MODE_KEY); 292 iowrite32(reg, wdt_base + WDT_MODE); 293 294 return 0; 295 } 296 297 static int mtk_wdt_set_pretimeout(struct watchdog_device *wdd, 298 unsigned int timeout) 299 { 300 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdd); 301 void __iomem *wdt_base = mtk_wdt->wdt_base; 302 u32 reg = ioread32(wdt_base + WDT_MODE); 303 304 if (timeout && !wdd->pretimeout) { 305 wdd->pretimeout = wdd->timeout / 2; 306 reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); 307 } else if (!timeout && wdd->pretimeout) { 308 wdd->pretimeout = 0; 309 reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); 310 } else { 311 return 0; 312 } 313 314 reg |= WDT_MODE_KEY; 315 iowrite32(reg, wdt_base + WDT_MODE); 316 317 return mtk_wdt_set_timeout(wdd, wdd->timeout); 318 } 319 320 static irqreturn_t mtk_wdt_isr(int irq, void *arg) 321 { 322 struct watchdog_device *wdd = arg; 323 324 watchdog_notify_pretimeout(wdd); 325 326 return IRQ_HANDLED; 327 } 328 329 static const struct watchdog_info mtk_wdt_info = { 330 .identity = DRV_NAME, 331 .options = WDIOF_SETTIMEOUT | 332 WDIOF_KEEPALIVEPING | 333 WDIOF_MAGICCLOSE, 334 }; 335 336 static const struct watchdog_info mtk_wdt_pt_info = { 337 .identity = DRV_NAME, 338 .options = WDIOF_SETTIMEOUT | 339 WDIOF_PRETIMEOUT | 340 WDIOF_KEEPALIVEPING | 341 WDIOF_MAGICCLOSE, 342 }; 343 344 static const struct watchdog_ops mtk_wdt_ops = { 345 .owner = THIS_MODULE, 346 .start = mtk_wdt_start, 347 .stop = mtk_wdt_stop, 348 .ping = mtk_wdt_ping, 349 .set_timeout = mtk_wdt_set_timeout, 350 .set_pretimeout = mtk_wdt_set_pretimeout, 351 .restart = mtk_wdt_restart, 352 }; 353 354 static int mtk_wdt_probe(struct platform_device *pdev) 355 { 356 struct device *dev = &pdev->dev; 357 struct mtk_wdt_dev *mtk_wdt; 358 const struct mtk_wdt_data *wdt_data; 359 int err, irq; 360 361 mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL); 362 if (!mtk_wdt) 363 return -ENOMEM; 364 365 platform_set_drvdata(pdev, mtk_wdt); 366 367 mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0); 368 if (IS_ERR(mtk_wdt->wdt_base)) 369 return PTR_ERR(mtk_wdt->wdt_base); 370 371 irq = platform_get_irq_optional(pdev, 0); 372 if (irq > 0) { 373 err = devm_request_irq(&pdev->dev, irq, mtk_wdt_isr, 0, "wdt_bark", 374 &mtk_wdt->wdt_dev); 375 if (err) 376 return err; 377 378 mtk_wdt->wdt_dev.info = &mtk_wdt_pt_info; 379 mtk_wdt->wdt_dev.pretimeout = WDT_MAX_TIMEOUT / 2; 380 } else { 381 if (irq == -EPROBE_DEFER) 382 return -EPROBE_DEFER; 383 384 mtk_wdt->wdt_dev.info = &mtk_wdt_info; 385 } 386 387 mtk_wdt->wdt_dev.ops = &mtk_wdt_ops; 388 mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT; 389 mtk_wdt->wdt_dev.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT * 1000; 390 mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT; 391 mtk_wdt->wdt_dev.parent = dev; 392 393 watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev); 394 watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout); 395 watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128); 396 397 watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt); 398 399 mtk_wdt_init(&mtk_wdt->wdt_dev); 400 401 watchdog_stop_on_reboot(&mtk_wdt->wdt_dev); 402 err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev); 403 if (unlikely(err)) 404 return err; 405 406 dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n", 407 mtk_wdt->wdt_dev.timeout, nowayout); 408 409 wdt_data = of_device_get_match_data(dev); 410 if (wdt_data) { 411 err = toprgu_register_reset_controller(pdev, 412 wdt_data->toprgu_sw_rst_num); 413 if (err) 414 return err; 415 } 416 417 mtk_wdt->disable_wdt_extrst = 418 of_property_read_bool(dev->of_node, "mediatek,disable-extrst"); 419 420 mtk_wdt->reset_by_toprgu = 421 of_property_read_bool(dev->of_node, "mediatek,reset-by-toprgu"); 422 423 return 0; 424 } 425 426 static int mtk_wdt_suspend(struct device *dev) 427 { 428 struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev); 429 430 if (watchdog_active(&mtk_wdt->wdt_dev)) 431 mtk_wdt_stop(&mtk_wdt->wdt_dev); 432 433 return 0; 434 } 435 436 static int mtk_wdt_resume(struct device *dev) 437 { 438 struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev); 439 440 if (watchdog_active(&mtk_wdt->wdt_dev)) { 441 mtk_wdt_start(&mtk_wdt->wdt_dev); 442 mtk_wdt_ping(&mtk_wdt->wdt_dev); 443 } 444 445 return 0; 446 } 447 448 static const struct of_device_id mtk_wdt_dt_ids[] = { 449 { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, 450 { .compatible = "mediatek,mt6589-wdt" }, 451 { .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data }, 452 { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data }, 453 { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, 454 { .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data }, 455 { .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data }, 456 { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data }, 457 { .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data }, 458 { /* sentinel */ } 459 }; 460 MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids); 461 462 static DEFINE_SIMPLE_DEV_PM_OPS(mtk_wdt_pm_ops, 463 mtk_wdt_suspend, mtk_wdt_resume); 464 465 static struct platform_driver mtk_wdt_driver = { 466 .probe = mtk_wdt_probe, 467 .driver = { 468 .name = DRV_NAME, 469 .pm = pm_sleep_ptr(&mtk_wdt_pm_ops), 470 .of_match_table = mtk_wdt_dt_ids, 471 }, 472 }; 473 474 module_platform_driver(mtk_wdt_driver); 475 476 module_param(timeout, uint, 0); 477 MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds"); 478 479 module_param(nowayout, bool, 0); 480 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" 481 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 482 483 MODULE_LICENSE("GPL"); 484 MODULE_AUTHOR("Matthias Brugger <matthias.bgg@gmail.com>"); 485 MODULE_DESCRIPTION("Mediatek WatchDog Timer Driver"); 486 MODULE_VERSION(DRV_VERSION); 487