1 /* 2 * Ralink MT7621/MT7628 built-in hardware watchdog timer 3 * 4 * Copyright (C) 2014 John Crispin <john@phrozen.org> 5 * 6 * This driver was based on: drivers/watchdog/rt2880_wdt.c 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published 10 * by the Free Software Foundation. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/reset.h> 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/watchdog.h> 18 #include <linux/moduleparam.h> 19 #include <linux/platform_device.h> 20 #include <linux/mod_devicetable.h> 21 22 #include <asm/mach-ralink/ralink_regs.h> 23 24 #define SYSC_RSTSTAT 0x38 25 #define WDT_RST_CAUSE BIT(1) 26 27 #define RALINK_WDT_TIMEOUT 30 28 29 #define TIMER_REG_TMRSTAT 0x00 30 #define TIMER_REG_TMR1LOAD 0x24 31 #define TIMER_REG_TMR1CTL 0x20 32 33 #define TMR1CTL_ENABLE BIT(7) 34 #define TMR1CTL_RESTART BIT(9) 35 #define TMR1CTL_PRESCALE_SHIFT 16 36 37 static void __iomem *mt7621_wdt_base; 38 static struct reset_control *mt7621_wdt_reset; 39 40 static bool nowayout = WATCHDOG_NOWAYOUT; 41 module_param(nowayout, bool, 0); 42 MODULE_PARM_DESC(nowayout, 43 "Watchdog cannot be stopped once started (default=" 44 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 45 46 static inline void rt_wdt_w32(unsigned reg, u32 val) 47 { 48 iowrite32(val, mt7621_wdt_base + reg); 49 } 50 51 static inline u32 rt_wdt_r32(unsigned reg) 52 { 53 return ioread32(mt7621_wdt_base + reg); 54 } 55 56 static int mt7621_wdt_ping(struct watchdog_device *w) 57 { 58 rt_wdt_w32(TIMER_REG_TMRSTAT, TMR1CTL_RESTART); 59 60 return 0; 61 } 62 63 static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t) 64 { 65 w->timeout = t; 66 rt_wdt_w32(TIMER_REG_TMR1LOAD, t * 1000); 67 mt7621_wdt_ping(w); 68 69 return 0; 70 } 71 72 static int mt7621_wdt_start(struct watchdog_device *w) 73 { 74 u32 t; 75 76 /* set the prescaler to 1ms == 1000us */ 77 rt_wdt_w32(TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT); 78 79 mt7621_wdt_set_timeout(w, w->timeout); 80 81 t = rt_wdt_r32(TIMER_REG_TMR1CTL); 82 t |= TMR1CTL_ENABLE; 83 rt_wdt_w32(TIMER_REG_TMR1CTL, t); 84 85 return 0; 86 } 87 88 static int mt7621_wdt_stop(struct watchdog_device *w) 89 { 90 u32 t; 91 92 mt7621_wdt_ping(w); 93 94 t = rt_wdt_r32(TIMER_REG_TMR1CTL); 95 t &= ~TMR1CTL_ENABLE; 96 rt_wdt_w32(TIMER_REG_TMR1CTL, t); 97 98 return 0; 99 } 100 101 static int mt7621_wdt_bootcause(void) 102 { 103 if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE) 104 return WDIOF_CARDRESET; 105 106 return 0; 107 } 108 109 static int mt7621_wdt_is_running(struct watchdog_device *w) 110 { 111 return !!(rt_wdt_r32(TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE); 112 } 113 114 static const struct watchdog_info mt7621_wdt_info = { 115 .identity = "Mediatek Watchdog", 116 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, 117 }; 118 119 static const struct watchdog_ops mt7621_wdt_ops = { 120 .owner = THIS_MODULE, 121 .start = mt7621_wdt_start, 122 .stop = mt7621_wdt_stop, 123 .ping = mt7621_wdt_ping, 124 .set_timeout = mt7621_wdt_set_timeout, 125 }; 126 127 static struct watchdog_device mt7621_wdt_dev = { 128 .info = &mt7621_wdt_info, 129 .ops = &mt7621_wdt_ops, 130 .min_timeout = 1, 131 .max_timeout = 0xfffful / 1000, 132 }; 133 134 static int mt7621_wdt_probe(struct platform_device *pdev) 135 { 136 struct device *dev = &pdev->dev; 137 mt7621_wdt_base = devm_platform_ioremap_resource(pdev, 0); 138 if (IS_ERR(mt7621_wdt_base)) 139 return PTR_ERR(mt7621_wdt_base); 140 141 mt7621_wdt_reset = devm_reset_control_get_exclusive(dev, NULL); 142 if (!IS_ERR(mt7621_wdt_reset)) 143 reset_control_deassert(mt7621_wdt_reset); 144 145 mt7621_wdt_dev.bootstatus = mt7621_wdt_bootcause(); 146 147 watchdog_init_timeout(&mt7621_wdt_dev, mt7621_wdt_dev.max_timeout, 148 dev); 149 watchdog_set_nowayout(&mt7621_wdt_dev, nowayout); 150 if (mt7621_wdt_is_running(&mt7621_wdt_dev)) { 151 /* 152 * Make sure to apply timeout from watchdog core, taking 153 * the prescaler of this driver here into account (the 154 * boot loader might be using a different prescaler). 155 * 156 * To avoid spurious resets because of different scaling, 157 * we first disable the watchdog, set the new prescaler 158 * and timeout, and then re-enable the watchdog. 159 */ 160 mt7621_wdt_stop(&mt7621_wdt_dev); 161 mt7621_wdt_start(&mt7621_wdt_dev); 162 set_bit(WDOG_HW_RUNNING, &mt7621_wdt_dev.status); 163 } 164 165 return devm_watchdog_register_device(dev, &mt7621_wdt_dev); 166 } 167 168 static void mt7621_wdt_shutdown(struct platform_device *pdev) 169 { 170 mt7621_wdt_stop(&mt7621_wdt_dev); 171 } 172 173 static const struct of_device_id mt7621_wdt_match[] = { 174 { .compatible = "mediatek,mt7621-wdt" }, 175 {}, 176 }; 177 MODULE_DEVICE_TABLE(of, mt7621_wdt_match); 178 179 static struct platform_driver mt7621_wdt_driver = { 180 .probe = mt7621_wdt_probe, 181 .shutdown = mt7621_wdt_shutdown, 182 .driver = { 183 .name = KBUILD_MODNAME, 184 .of_match_table = mt7621_wdt_match, 185 }, 186 }; 187 188 module_platform_driver(mt7621_wdt_driver); 189 190 MODULE_DESCRIPTION("MediaTek MT762x hardware watchdog driver"); 191 MODULE_AUTHOR("John Crispin <john@phrozen.org"); 192 MODULE_LICENSE("GPL v2"); 193