1 /*
2  * mpc8xxx_wdt.c - MPC8xx/MPC83xx/MPC86xx watchdog userspace interface
3  *
4  * Authors: Dave Updegraff <dave@cray.org>
5  *	    Kumar Gala <galak@kernel.crashing.org>
6  *		Attribution: from 83xx_wst: Florian Schirmer <jolt@tuxbox.org>
7  *				..and from sc520_wdt
8  * Copyright (c) 2008  MontaVista Software, Inc.
9  *                     Anton Vorontsov <avorontsov@ru.mvista.com>
10  *
11  * Note: it appears that you can only actually ENABLE or DISABLE the thing
12  * once after POR. Once enabled, you cannot disable, and vice versa.
13  *
14  * This program is free software; you can redistribute  it and/or modify it
15  * under  the terms of  the GNU General  Public License as published by the
16  * Free Software Foundation;  either version 2 of the  License, or (at your
17  * option) any later version.
18  */
19 
20 #include <linux/fs.h>
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/of_address.h>
24 #include <linux/of_platform.h>
25 #include <linux/module.h>
26 #include <linux/watchdog.h>
27 #include <linux/io.h>
28 #include <linux/uaccess.h>
29 #include <sysdev/fsl_soc.h>
30 
31 #define WATCHDOG_TIMEOUT 10
32 
33 struct mpc8xxx_wdt {
34 	__be32 res0;
35 	__be32 swcrr; /* System watchdog control register */
36 #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */
37 #define SWCRR_SWF  0x00000008 /* Software Watchdog Freeze (mpc8xx). */
38 #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
39 #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit.*/
40 #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */
41 	__be32 swcnr; /* System watchdog count register */
42 	u8 res1[2];
43 	__be16 swsrr; /* System watchdog service register */
44 	u8 res2[0xF0];
45 };
46 
47 struct mpc8xxx_wdt_type {
48 	int prescaler;
49 	bool hw_enabled;
50 	u32 rsr_mask;
51 };
52 
53 struct mpc8xxx_wdt_ddata {
54 	struct mpc8xxx_wdt __iomem *base;
55 	struct watchdog_device wdd;
56 	spinlock_t lock;
57 	u16 swtc;
58 };
59 
60 static u16 timeout;
61 module_param(timeout, ushort, 0);
62 MODULE_PARM_DESC(timeout,
63 	"Watchdog timeout in seconds. (1<timeout<65535, default="
64 	__MODULE_STRING(WATCHDOG_TIMEOUT) ")");
65 
66 static bool reset = 1;
67 module_param(reset, bool, 0);
68 MODULE_PARM_DESC(reset,
69 	"Watchdog Interrupt/Reset Mode. 0 = interrupt, 1 = reset");
70 
71 static bool nowayout = WATCHDOG_NOWAYOUT;
72 module_param(nowayout, bool, 0);
73 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
74 		 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
75 
76 static void mpc8xxx_wdt_keepalive(struct mpc8xxx_wdt_ddata *ddata)
77 {
78 	/* Ping the WDT */
79 	spin_lock(&ddata->lock);
80 	out_be16(&ddata->base->swsrr, 0x556c);
81 	out_be16(&ddata->base->swsrr, 0xaa39);
82 	spin_unlock(&ddata->lock);
83 }
84 
85 static int mpc8xxx_wdt_start(struct watchdog_device *w)
86 {
87 	struct mpc8xxx_wdt_ddata *ddata =
88 		container_of(w, struct mpc8xxx_wdt_ddata, wdd);
89 	u32 tmp = in_be32(&ddata->base->swcrr);
90 
91 	/* Good, fire up the show */
92 	tmp &= ~(SWCRR_SWTC | SWCRR_SWF | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR);
93 	tmp |= SWCRR_SWEN | SWCRR_SWPR | (ddata->swtc << 16);
94 
95 	if (reset)
96 		tmp |= SWCRR_SWRI;
97 
98 	out_be32(&ddata->base->swcrr, tmp);
99 
100 	tmp = in_be32(&ddata->base->swcrr);
101 	if (!(tmp & SWCRR_SWEN))
102 		return -EOPNOTSUPP;
103 
104 	ddata->swtc = tmp >> 16;
105 	set_bit(WDOG_HW_RUNNING, &ddata->wdd.status);
106 
107 	return 0;
108 }
109 
110 static int mpc8xxx_wdt_ping(struct watchdog_device *w)
111 {
112 	struct mpc8xxx_wdt_ddata *ddata =
113 		container_of(w, struct mpc8xxx_wdt_ddata, wdd);
114 
115 	mpc8xxx_wdt_keepalive(ddata);
116 	return 0;
117 }
118 
119 static struct watchdog_info mpc8xxx_wdt_info = {
120 	.options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT,
121 	.firmware_version = 1,
122 	.identity = "MPC8xxx",
123 };
124 
125 static struct watchdog_ops mpc8xxx_wdt_ops = {
126 	.owner = THIS_MODULE,
127 	.start = mpc8xxx_wdt_start,
128 	.ping = mpc8xxx_wdt_ping,
129 };
130 
131 static int mpc8xxx_wdt_probe(struct platform_device *ofdev)
132 {
133 	int ret;
134 	struct resource *res;
135 	const struct mpc8xxx_wdt_type *wdt_type;
136 	struct mpc8xxx_wdt_ddata *ddata;
137 	u32 freq = fsl_get_sys_freq();
138 	bool enabled;
139 	struct device *dev = &ofdev->dev;
140 
141 	wdt_type = of_device_get_match_data(dev);
142 	if (!wdt_type)
143 		return -EINVAL;
144 
145 	if (!freq || freq == -1)
146 		return -EINVAL;
147 
148 	ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
149 	if (!ddata)
150 		return -ENOMEM;
151 
152 	ddata->base = devm_platform_ioremap_resource(ofdev, 0);
153 	if (IS_ERR(ddata->base))
154 		return PTR_ERR(ddata->base);
155 
156 	enabled = in_be32(&ddata->base->swcrr) & SWCRR_SWEN;
157 	if (!enabled && wdt_type->hw_enabled) {
158 		dev_info(dev, "could not be enabled in software\n");
159 		return -ENODEV;
160 	}
161 
162 	res = platform_get_resource(ofdev, IORESOURCE_MEM, 1);
163 	if (res) {
164 		bool status;
165 		u32 __iomem *rsr = ioremap(res->start, resource_size(res));
166 
167 		if (!rsr)
168 			return -ENOMEM;
169 
170 		status = in_be32(rsr) & wdt_type->rsr_mask;
171 		ddata->wdd.bootstatus = status ? WDIOF_CARDRESET : 0;
172 		 /* clear reset status bits related to watchdog timer */
173 		out_be32(rsr, wdt_type->rsr_mask);
174 		iounmap(rsr);
175 
176 		dev_info(dev, "Last boot was %scaused by watchdog\n",
177 			 status ? "" : "not ");
178 	}
179 
180 	spin_lock_init(&ddata->lock);
181 
182 	ddata->wdd.info = &mpc8xxx_wdt_info,
183 	ddata->wdd.ops = &mpc8xxx_wdt_ops,
184 
185 	ddata->wdd.timeout = WATCHDOG_TIMEOUT;
186 	watchdog_init_timeout(&ddata->wdd, timeout, dev);
187 
188 	watchdog_set_nowayout(&ddata->wdd, nowayout);
189 
190 	ddata->swtc = min(ddata->wdd.timeout * freq / wdt_type->prescaler,
191 			  0xffffU);
192 
193 	/*
194 	 * If the watchdog was previously enabled or we're running on
195 	 * MPC8xxx, we should ping the wdt from the kernel until the
196 	 * userspace handles it.
197 	 */
198 	if (enabled)
199 		mpc8xxx_wdt_start(&ddata->wdd);
200 
201 	ddata->wdd.max_hw_heartbeat_ms = (ddata->swtc * wdt_type->prescaler) /
202 					 (freq / 1000);
203 	ddata->wdd.min_timeout = ddata->wdd.max_hw_heartbeat_ms / 1000;
204 	if (ddata->wdd.timeout < ddata->wdd.min_timeout)
205 		ddata->wdd.timeout = ddata->wdd.min_timeout;
206 
207 	ret = devm_watchdog_register_device(dev, &ddata->wdd);
208 	if (ret) {
209 		dev_err(dev, "cannot register watchdog device (err=%d)\n",
210 			ret);
211 		return ret;
212 	}
213 
214 	dev_info(dev,
215 		 "WDT driver for MPC8xxx initialized. mode:%s timeout=%d sec\n",
216 		 reset ? "reset" : "interrupt", ddata->wdd.timeout);
217 
218 	platform_set_drvdata(ofdev, ddata);
219 	return 0;
220 }
221 
222 static const struct of_device_id mpc8xxx_wdt_match[] = {
223 	{
224 		.compatible = "mpc83xx_wdt",
225 		.data = &(struct mpc8xxx_wdt_type) {
226 			.prescaler = 0x10000,
227 			.rsr_mask = BIT(3), /* RSR Bit SWRS */
228 		},
229 	},
230 	{
231 		.compatible = "fsl,mpc8610-wdt",
232 		.data = &(struct mpc8xxx_wdt_type) {
233 			.prescaler = 0x10000,
234 			.hw_enabled = true,
235 			.rsr_mask = BIT(20), /* RSTRSCR Bit WDT_RR */
236 		},
237 	},
238 	{
239 		.compatible = "fsl,mpc823-wdt",
240 		.data = &(struct mpc8xxx_wdt_type) {
241 			.prescaler = 0x800,
242 			.hw_enabled = true,
243 			.rsr_mask = BIT(28), /* RSR Bit SWRS */
244 		},
245 	},
246 	{},
247 };
248 MODULE_DEVICE_TABLE(of, mpc8xxx_wdt_match);
249 
250 static struct platform_driver mpc8xxx_wdt_driver = {
251 	.probe		= mpc8xxx_wdt_probe,
252 	.driver = {
253 		.name = "mpc8xxx_wdt",
254 		.of_match_table = mpc8xxx_wdt_match,
255 	},
256 };
257 
258 static int __init mpc8xxx_wdt_init(void)
259 {
260 	return platform_driver_register(&mpc8xxx_wdt_driver);
261 }
262 arch_initcall(mpc8xxx_wdt_init);
263 
264 static void __exit mpc8xxx_wdt_exit(void)
265 {
266 	platform_driver_unregister(&mpc8xxx_wdt_driver);
267 }
268 module_exit(mpc8xxx_wdt_exit);
269 
270 MODULE_AUTHOR("Dave Updegraff, Kumar Gala");
271 MODULE_DESCRIPTION("Driver for watchdog timer in MPC8xx/MPC83xx/MPC86xx "
272 		   "uProcessors");
273 MODULE_LICENSE("GPL");
274