1c60923ddSMichael Shych // SPDX-License-Identifier: GPL-2.0+ 2c60923ddSMichael Shych /* 3c60923ddSMichael Shych * Mellanox watchdog driver 4c60923ddSMichael Shych * 5c60923ddSMichael Shych * Copyright (C) 2019 Mellanox Technologies 6c60923ddSMichael Shych * Copyright (C) 2019 Michael Shych <mshych@mellanox.com> 7c60923ddSMichael Shych */ 8c60923ddSMichael Shych 9c60923ddSMichael Shych #include <linux/bitops.h> 10c60923ddSMichael Shych #include <linux/device.h> 11c60923ddSMichael Shych #include <linux/errno.h> 12c60923ddSMichael Shych #include <linux/log2.h> 13c60923ddSMichael Shych #include <linux/module.h> 14c60923ddSMichael Shych #include <linux/platform_data/mlxreg.h> 15c60923ddSMichael Shych #include <linux/platform_device.h> 16c60923ddSMichael Shych #include <linux/regmap.h> 17c60923ddSMichael Shych #include <linux/spinlock.h> 18c60923ddSMichael Shych #include <linux/types.h> 19c60923ddSMichael Shych #include <linux/watchdog.h> 20c60923ddSMichael Shych 21c60923ddSMichael Shych #define MLXREG_WDT_CLOCK_SCALE 1000 22c60923ddSMichael Shych #define MLXREG_WDT_MAX_TIMEOUT_TYPE1 32 23c60923ddSMichael Shych #define MLXREG_WDT_MAX_TIMEOUT_TYPE2 255 24eee85114SMichael Shych #define MLXREG_WDT_MAX_TIMEOUT_TYPE3 65535 25c60923ddSMichael Shych #define MLXREG_WDT_MIN_TIMEOUT 1 26c60923ddSMichael Shych #define MLXREG_WDT_OPTIONS_BASE (WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE | \ 27c60923ddSMichael Shych WDIOF_SETTIMEOUT) 28c60923ddSMichael Shych 29c60923ddSMichael Shych /** 30c60923ddSMichael Shych * struct mlxreg_wdt - wd private data: 31c60923ddSMichael Shych * 32c60923ddSMichael Shych * @wdd: watchdog device; 33c60923ddSMichael Shych * @device: basic device; 34c60923ddSMichael Shych * @pdata: data received from platform driver; 35c60923ddSMichael Shych * @regmap: register map of parent device; 36c60923ddSMichael Shych * @timeout: defined timeout in sec.; 37c60923ddSMichael Shych * @action_idx: index for direct access to action register; 38c60923ddSMichael Shych * @timeout_idx:index for direct access to TO register; 39c60923ddSMichael Shych * @tleft_idx: index for direct access to time left register; 40c60923ddSMichael Shych * @ping_idx: index for direct access to ping register; 41c60923ddSMichael Shych * @reset_idx: index for direct access to reset cause register; 42c60923ddSMichael Shych * @wd_type: watchdog HW type; 43c60923ddSMichael Shych */ 44c60923ddSMichael Shych struct mlxreg_wdt { 45c60923ddSMichael Shych struct watchdog_device wdd; 46c60923ddSMichael Shych struct mlxreg_core_platform_data *pdata; 47c60923ddSMichael Shych void *regmap; 48c60923ddSMichael Shych int action_idx; 49c60923ddSMichael Shych int timeout_idx; 50c60923ddSMichael Shych int tleft_idx; 51c60923ddSMichael Shych int ping_idx; 52c60923ddSMichael Shych int reset_idx; 53eee85114SMichael Shych int regmap_val_sz; 54c60923ddSMichael Shych enum mlxreg_wdt_type wdt_type; 55c60923ddSMichael Shych }; 56c60923ddSMichael Shych 57c60923ddSMichael Shych static void mlxreg_wdt_check_card_reset(struct mlxreg_wdt *wdt) 58c60923ddSMichael Shych { 59c60923ddSMichael Shych struct mlxreg_core_data *reg_data; 60c60923ddSMichael Shych u32 regval; 61c60923ddSMichael Shych int rc; 62c60923ddSMichael Shych 63c60923ddSMichael Shych if (wdt->reset_idx == -EINVAL) 64c60923ddSMichael Shych return; 65c60923ddSMichael Shych 66c60923ddSMichael Shych if (!(wdt->wdd.info->options & WDIOF_CARDRESET)) 67c60923ddSMichael Shych return; 68c60923ddSMichael Shych 69c60923ddSMichael Shych reg_data = &wdt->pdata->data[wdt->reset_idx]; 70c60923ddSMichael Shych rc = regmap_read(wdt->regmap, reg_data->reg, ®val); 71c60923ddSMichael Shych if (!rc) { 72c60923ddSMichael Shych if (regval & ~reg_data->mask) { 73c60923ddSMichael Shych wdt->wdd.bootstatus = WDIOF_CARDRESET; 74c60923ddSMichael Shych dev_info(wdt->wdd.parent, 75c60923ddSMichael Shych "watchdog previously reset the CPU\n"); 76c60923ddSMichael Shych } 77c60923ddSMichael Shych } 78c60923ddSMichael Shych } 79c60923ddSMichael Shych 80c60923ddSMichael Shych static int mlxreg_wdt_start(struct watchdog_device *wdd) 81c60923ddSMichael Shych { 82c60923ddSMichael Shych struct mlxreg_wdt *wdt = watchdog_get_drvdata(wdd); 83c60923ddSMichael Shych struct mlxreg_core_data *reg_data = &wdt->pdata->data[wdt->action_idx]; 84c60923ddSMichael Shych 85c60923ddSMichael Shych return regmap_update_bits(wdt->regmap, reg_data->reg, ~reg_data->mask, 86c60923ddSMichael Shych BIT(reg_data->bit)); 87c60923ddSMichael Shych } 88c60923ddSMichael Shych 89c60923ddSMichael Shych static int mlxreg_wdt_stop(struct watchdog_device *wdd) 90c60923ddSMichael Shych { 91c60923ddSMichael Shych struct mlxreg_wdt *wdt = watchdog_get_drvdata(wdd); 92c60923ddSMichael Shych struct mlxreg_core_data *reg_data = &wdt->pdata->data[wdt->action_idx]; 93c60923ddSMichael Shych 94c60923ddSMichael Shych return regmap_update_bits(wdt->regmap, reg_data->reg, ~reg_data->mask, 95c60923ddSMichael Shych ~BIT(reg_data->bit)); 96c60923ddSMichael Shych } 97c60923ddSMichael Shych 98c60923ddSMichael Shych static int mlxreg_wdt_ping(struct watchdog_device *wdd) 99c60923ddSMichael Shych { 100c60923ddSMichael Shych struct mlxreg_wdt *wdt = watchdog_get_drvdata(wdd); 101c60923ddSMichael Shych struct mlxreg_core_data *reg_data = &wdt->pdata->data[wdt->ping_idx]; 102c60923ddSMichael Shych 103c60923ddSMichael Shych return regmap_update_bits_base(wdt->regmap, reg_data->reg, 104c60923ddSMichael Shych ~reg_data->mask, BIT(reg_data->bit), 105c60923ddSMichael Shych NULL, false, true); 106c60923ddSMichael Shych } 107c60923ddSMichael Shych 108c60923ddSMichael Shych static int mlxreg_wdt_set_timeout(struct watchdog_device *wdd, 109c60923ddSMichael Shych unsigned int timeout) 110c60923ddSMichael Shych { 111c60923ddSMichael Shych struct mlxreg_wdt *wdt = watchdog_get_drvdata(wdd); 112c60923ddSMichael Shych struct mlxreg_core_data *reg_data = &wdt->pdata->data[wdt->timeout_idx]; 113c60923ddSMichael Shych u32 regval, set_time, hw_timeout; 114c60923ddSMichael Shych int rc; 115c60923ddSMichael Shych 116eee85114SMichael Shych switch (wdt->wdt_type) { 117eee85114SMichael Shych case MLX_WDT_TYPE1: 118c60923ddSMichael Shych rc = regmap_read(wdt->regmap, reg_data->reg, ®val); 119c60923ddSMichael Shych if (rc) 120c60923ddSMichael Shych return rc; 121c60923ddSMichael Shych 122c60923ddSMichael Shych hw_timeout = order_base_2(timeout * MLXREG_WDT_CLOCK_SCALE); 123c60923ddSMichael Shych regval = (regval & reg_data->mask) | hw_timeout; 124c60923ddSMichael Shych /* Rowndown to actual closest number of sec. */ 125c60923ddSMichael Shych set_time = BIT(hw_timeout) / MLXREG_WDT_CLOCK_SCALE; 126eee85114SMichael Shych rc = regmap_write(wdt->regmap, reg_data->reg, regval); 127eee85114SMichael Shych break; 128eee85114SMichael Shych case MLX_WDT_TYPE2: 129c60923ddSMichael Shych set_time = timeout; 130eee85114SMichael Shych rc = regmap_write(wdt->regmap, reg_data->reg, timeout); 131eee85114SMichael Shych break; 132eee85114SMichael Shych case MLX_WDT_TYPE3: 133eee85114SMichael Shych /* WD_TYPE3 has 2B set time register */ 134eee85114SMichael Shych set_time = timeout; 135eee85114SMichael Shych if (wdt->regmap_val_sz == 1) { 136eee85114SMichael Shych regval = timeout & 0xff; 137eee85114SMichael Shych rc = regmap_write(wdt->regmap, reg_data->reg, regval); 138eee85114SMichael Shych if (!rc) { 139eee85114SMichael Shych regval = (timeout & 0xff00) >> 8; 140eee85114SMichael Shych rc = regmap_write(wdt->regmap, 141eee85114SMichael Shych reg_data->reg + 1, regval); 142eee85114SMichael Shych } 143eee85114SMichael Shych } else { 144eee85114SMichael Shych rc = regmap_write(wdt->regmap, reg_data->reg, timeout); 145eee85114SMichael Shych } 146eee85114SMichael Shych break; 147eee85114SMichael Shych default: 148eee85114SMichael Shych return -EINVAL; 149c60923ddSMichael Shych } 150c60923ddSMichael Shych 151c60923ddSMichael Shych wdd->timeout = set_time; 152c60923ddSMichael Shych if (!rc) { 153c60923ddSMichael Shych /* 154c60923ddSMichael Shych * Restart watchdog with new timeout period 155c60923ddSMichael Shych * if watchdog is already started. 156c60923ddSMichael Shych */ 157c60923ddSMichael Shych if (watchdog_active(wdd)) { 158c60923ddSMichael Shych rc = mlxreg_wdt_stop(wdd); 159c60923ddSMichael Shych if (!rc) 160c60923ddSMichael Shych rc = mlxreg_wdt_start(wdd); 161c60923ddSMichael Shych } 162c60923ddSMichael Shych } 163c60923ddSMichael Shych 164c60923ddSMichael Shych return rc; 165c60923ddSMichael Shych } 166c60923ddSMichael Shych 167c60923ddSMichael Shych static unsigned int mlxreg_wdt_get_timeleft(struct watchdog_device *wdd) 168c60923ddSMichael Shych { 169c60923ddSMichael Shych struct mlxreg_wdt *wdt = watchdog_get_drvdata(wdd); 170c60923ddSMichael Shych struct mlxreg_core_data *reg_data = &wdt->pdata->data[wdt->tleft_idx]; 171eee85114SMichael Shych u32 regval, msb, lsb; 172c60923ddSMichael Shych int rc; 173c60923ddSMichael Shych 174eee85114SMichael Shych if (wdt->wdt_type == MLX_WDT_TYPE2) { 175c60923ddSMichael Shych rc = regmap_read(wdt->regmap, reg_data->reg, ®val); 176eee85114SMichael Shych } else { 177eee85114SMichael Shych /* WD_TYPE3 has 2 byte timeleft register */ 178eee85114SMichael Shych if (wdt->regmap_val_sz == 1) { 179eee85114SMichael Shych rc = regmap_read(wdt->regmap, reg_data->reg, &lsb); 180eee85114SMichael Shych if (!rc) { 181eee85114SMichael Shych rc = regmap_read(wdt->regmap, 182eee85114SMichael Shych reg_data->reg + 1, &msb); 183eee85114SMichael Shych regval = (msb & 0xff) << 8 | (lsb & 0xff); 184eee85114SMichael Shych } 185eee85114SMichael Shych } else { 186eee85114SMichael Shych rc = regmap_read(wdt->regmap, reg_data->reg, ®val); 187eee85114SMichael Shych } 188eee85114SMichael Shych } 189eee85114SMichael Shych 190c60923ddSMichael Shych /* Return 0 timeleft in case of failure register read. */ 191c60923ddSMichael Shych return rc == 0 ? regval : 0; 192c60923ddSMichael Shych } 193c60923ddSMichael Shych 194c60923ddSMichael Shych static const struct watchdog_ops mlxreg_wdt_ops_type1 = { 195c60923ddSMichael Shych .start = mlxreg_wdt_start, 196c60923ddSMichael Shych .stop = mlxreg_wdt_stop, 197c60923ddSMichael Shych .ping = mlxreg_wdt_ping, 198c60923ddSMichael Shych .set_timeout = mlxreg_wdt_set_timeout, 199c60923ddSMichael Shych .owner = THIS_MODULE, 200c60923ddSMichael Shych }; 201c60923ddSMichael Shych 202c60923ddSMichael Shych static const struct watchdog_ops mlxreg_wdt_ops_type2 = { 203c60923ddSMichael Shych .start = mlxreg_wdt_start, 204c60923ddSMichael Shych .stop = mlxreg_wdt_stop, 205c60923ddSMichael Shych .ping = mlxreg_wdt_ping, 206c60923ddSMichael Shych .set_timeout = mlxreg_wdt_set_timeout, 207c60923ddSMichael Shych .get_timeleft = mlxreg_wdt_get_timeleft, 208c60923ddSMichael Shych .owner = THIS_MODULE, 209c60923ddSMichael Shych }; 210c60923ddSMichael Shych 211c60923ddSMichael Shych static const struct watchdog_info mlxreg_wdt_main_info = { 212c60923ddSMichael Shych .options = MLXREG_WDT_OPTIONS_BASE 213c60923ddSMichael Shych | WDIOF_CARDRESET, 214c60923ddSMichael Shych .identity = "mlx-wdt-main", 215c60923ddSMichael Shych }; 216c60923ddSMichael Shych 217c60923ddSMichael Shych static const struct watchdog_info mlxreg_wdt_aux_info = { 218c60923ddSMichael Shych .options = MLXREG_WDT_OPTIONS_BASE 219c60923ddSMichael Shych | WDIOF_ALARMONLY, 220c60923ddSMichael Shych .identity = "mlx-wdt-aux", 221c60923ddSMichael Shych }; 222c60923ddSMichael Shych 223c60923ddSMichael Shych static void mlxreg_wdt_config(struct mlxreg_wdt *wdt, 224c60923ddSMichael Shych struct mlxreg_core_platform_data *pdata) 225c60923ddSMichael Shych { 226c60923ddSMichael Shych struct mlxreg_core_data *data = pdata->data; 227c60923ddSMichael Shych int i; 228c60923ddSMichael Shych 229c60923ddSMichael Shych wdt->reset_idx = -EINVAL; 230c60923ddSMichael Shych for (i = 0; i < pdata->counter; i++, data++) { 231c60923ddSMichael Shych if (strnstr(data->label, "action", sizeof(data->label))) 232c60923ddSMichael Shych wdt->action_idx = i; 233c60923ddSMichael Shych else if (strnstr(data->label, "timeout", sizeof(data->label))) 234c60923ddSMichael Shych wdt->timeout_idx = i; 235c60923ddSMichael Shych else if (strnstr(data->label, "timeleft", sizeof(data->label))) 236c60923ddSMichael Shych wdt->tleft_idx = i; 237c60923ddSMichael Shych else if (strnstr(data->label, "ping", sizeof(data->label))) 238c60923ddSMichael Shych wdt->ping_idx = i; 239c60923ddSMichael Shych else if (strnstr(data->label, "reset", sizeof(data->label))) 240c60923ddSMichael Shych wdt->reset_idx = i; 241c60923ddSMichael Shych } 242c60923ddSMichael Shych 243c60923ddSMichael Shych wdt->pdata = pdata; 244c60923ddSMichael Shych if (strnstr(pdata->identity, mlxreg_wdt_main_info.identity, 245c60923ddSMichael Shych sizeof(mlxreg_wdt_main_info.identity))) 246c60923ddSMichael Shych wdt->wdd.info = &mlxreg_wdt_main_info; 247c60923ddSMichael Shych else 248c60923ddSMichael Shych wdt->wdd.info = &mlxreg_wdt_aux_info; 249c60923ddSMichael Shych 250c60923ddSMichael Shych wdt->wdt_type = pdata->version; 251eee85114SMichael Shych switch (wdt->wdt_type) { 252eee85114SMichael Shych case MLX_WDT_TYPE1: 253c60923ddSMichael Shych wdt->wdd.ops = &mlxreg_wdt_ops_type1; 254c60923ddSMichael Shych wdt->wdd.max_timeout = MLXREG_WDT_MAX_TIMEOUT_TYPE1; 255eee85114SMichael Shych break; 256eee85114SMichael Shych case MLX_WDT_TYPE2: 257eee85114SMichael Shych wdt->wdd.ops = &mlxreg_wdt_ops_type2; 258eee85114SMichael Shych wdt->wdd.max_timeout = MLXREG_WDT_MAX_TIMEOUT_TYPE2; 259eee85114SMichael Shych break; 260eee85114SMichael Shych case MLX_WDT_TYPE3: 261eee85114SMichael Shych wdt->wdd.ops = &mlxreg_wdt_ops_type2; 262eee85114SMichael Shych wdt->wdd.max_timeout = MLXREG_WDT_MAX_TIMEOUT_TYPE3; 263eee85114SMichael Shych break; 264eee85114SMichael Shych default: 265eee85114SMichael Shych break; 266c60923ddSMichael Shych } 267eee85114SMichael Shych 268c60923ddSMichael Shych wdt->wdd.min_timeout = MLXREG_WDT_MIN_TIMEOUT; 269c60923ddSMichael Shych } 270c60923ddSMichael Shych 271c60923ddSMichael Shych static int mlxreg_wdt_init_timeout(struct mlxreg_wdt *wdt, 272c60923ddSMichael Shych struct mlxreg_core_platform_data *pdata) 273c60923ddSMichael Shych { 274c60923ddSMichael Shych u32 timeout; 275c60923ddSMichael Shych 276c60923ddSMichael Shych timeout = pdata->data[wdt->timeout_idx].health_cntr; 277c60923ddSMichael Shych return mlxreg_wdt_set_timeout(&wdt->wdd, timeout); 278c60923ddSMichael Shych } 279c60923ddSMichael Shych 280c60923ddSMichael Shych static int mlxreg_wdt_probe(struct platform_device *pdev) 281c60923ddSMichael Shych { 282099e3039SGuenter Roeck struct device *dev = &pdev->dev; 283c60923ddSMichael Shych struct mlxreg_core_platform_data *pdata; 284c60923ddSMichael Shych struct mlxreg_wdt *wdt; 285c60923ddSMichael Shych int rc; 286c60923ddSMichael Shych 287099e3039SGuenter Roeck pdata = dev_get_platdata(dev); 288c60923ddSMichael Shych if (!pdata) { 289099e3039SGuenter Roeck dev_err(dev, "Failed to get platform data.\n"); 290c60923ddSMichael Shych return -EINVAL; 291c60923ddSMichael Shych } 292099e3039SGuenter Roeck wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); 293c60923ddSMichael Shych if (!wdt) 294c60923ddSMichael Shych return -ENOMEM; 295c60923ddSMichael Shych 296099e3039SGuenter Roeck wdt->wdd.parent = dev; 297c60923ddSMichael Shych wdt->regmap = pdata->regmap; 298eee85114SMichael Shych rc = regmap_get_val_bytes(wdt->regmap); 299eee85114SMichael Shych if (rc < 0) 300eee85114SMichael Shych return -EINVAL; 301eee85114SMichael Shych 302eee85114SMichael Shych wdt->regmap_val_sz = rc; 303c60923ddSMichael Shych mlxreg_wdt_config(wdt, pdata); 304c60923ddSMichael Shych 305c60923ddSMichael Shych if ((pdata->features & MLXREG_CORE_WD_FEATURE_NOWAYOUT)) 306c60923ddSMichael Shych watchdog_set_nowayout(&wdt->wdd, WATCHDOG_NOWAYOUT); 307c60923ddSMichael Shych watchdog_stop_on_reboot(&wdt->wdd); 308c60923ddSMichael Shych watchdog_stop_on_unregister(&wdt->wdd); 309c60923ddSMichael Shych watchdog_set_drvdata(&wdt->wdd, wdt); 310c60923ddSMichael Shych rc = mlxreg_wdt_init_timeout(wdt, pdata); 311c60923ddSMichael Shych if (rc) 312c60923ddSMichael Shych goto register_error; 313c60923ddSMichael Shych 314c60923ddSMichael Shych if ((pdata->features & MLXREG_CORE_WD_FEATURE_START_AT_BOOT)) { 315c60923ddSMichael Shych rc = mlxreg_wdt_start(&wdt->wdd); 316c60923ddSMichael Shych if (rc) 317c60923ddSMichael Shych goto register_error; 318c60923ddSMichael Shych set_bit(WDOG_HW_RUNNING, &wdt->wdd.status); 319c60923ddSMichael Shych } 320c60923ddSMichael Shych mlxreg_wdt_check_card_reset(wdt); 321099e3039SGuenter Roeck rc = devm_watchdog_register_device(dev, &wdt->wdd); 322c60923ddSMichael Shych 323c60923ddSMichael Shych register_error: 324c60923ddSMichael Shych if (rc) 325099e3039SGuenter Roeck dev_err(dev, "Cannot register watchdog device (err=%d)\n", rc); 326c60923ddSMichael Shych return rc; 327c60923ddSMichael Shych } 328c60923ddSMichael Shych 329c60923ddSMichael Shych static struct platform_driver mlxreg_wdt_driver = { 330c60923ddSMichael Shych .probe = mlxreg_wdt_probe, 331c60923ddSMichael Shych .driver = { 332c60923ddSMichael Shych .name = "mlx-wdt", 333c60923ddSMichael Shych }, 334c60923ddSMichael Shych }; 335c60923ddSMichael Shych 336c60923ddSMichael Shych module_platform_driver(mlxreg_wdt_driver); 337c60923ddSMichael Shych 338c60923ddSMichael Shych MODULE_AUTHOR("Michael Shych <michaelsh@mellanox.com>"); 339c60923ddSMichael Shych MODULE_DESCRIPTION("Mellanox watchdog driver"); 340c60923ddSMichael Shych MODULE_LICENSE("GPL"); 341c60923ddSMichael Shych MODULE_ALIAS("platform:mlx-wdt"); 342