1 /* 2 * Watchdog driver for IMX2 and later processors 3 * 4 * Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de> 5 * Copyright (C) 2014 Freescale Semiconductor, Inc. 6 * 7 * some parts adapted by similar drivers from Darius Augulis and Vladimir 8 * Zapolskiy, additional improvements by Wim Van Sebroeck. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published by 12 * the Free Software Foundation. 13 * 14 * NOTE: MX1 has a slightly different Watchdog than MX2 and later: 15 * 16 * MX1: MX2+: 17 * ---- ----- 18 * Registers: 32-bit 16-bit 19 * Stopable timer: Yes No 20 * Need to enable clk: No Yes 21 * Halt on suspend: Manual Can be automatic 22 */ 23 24 #include <linux/clk.h> 25 #include <linux/delay.h> 26 #include <linux/init.h> 27 #include <linux/io.h> 28 #include <linux/jiffies.h> 29 #include <linux/kernel.h> 30 #include <linux/module.h> 31 #include <linux/moduleparam.h> 32 #include <linux/notifier.h> 33 #include <linux/of_address.h> 34 #include <linux/platform_device.h> 35 #include <linux/reboot.h> 36 #include <linux/regmap.h> 37 #include <linux/timer.h> 38 #include <linux/watchdog.h> 39 40 #define DRIVER_NAME "imx2-wdt" 41 42 #define IMX2_WDT_WCR 0x00 /* Control Register */ 43 #define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */ 44 #define IMX2_WDT_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */ 45 #define IMX2_WDT_WCR_WDE (1 << 2) /* -> Watchdog Enable */ 46 #define IMX2_WDT_WCR_WDZST (1 << 0) /* -> Watchdog timer Suspend */ 47 48 #define IMX2_WDT_WSR 0x02 /* Service Register */ 49 #define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */ 50 #define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */ 51 52 #define IMX2_WDT_WRSR 0x04 /* Reset Status Register */ 53 #define IMX2_WDT_WRSR_TOUT (1 << 1) /* -> Reset due to Timeout */ 54 55 #define IMX2_WDT_MAX_TIME 128 56 #define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */ 57 58 #define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8) 59 60 struct imx2_wdt_device { 61 struct clk *clk; 62 struct regmap *regmap; 63 struct timer_list timer; /* Pings the watchdog when closed */ 64 struct watchdog_device wdog; 65 struct notifier_block restart_handler; 66 }; 67 68 static bool nowayout = WATCHDOG_NOWAYOUT; 69 module_param(nowayout, bool, 0); 70 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" 71 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 72 73 74 static unsigned timeout = IMX2_WDT_DEFAULT_TIME; 75 module_param(timeout, uint, 0); 76 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default=" 77 __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")"); 78 79 static const struct watchdog_info imx2_wdt_info = { 80 .identity = "imx2+ watchdog", 81 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, 82 }; 83 84 static int imx2_restart_handler(struct notifier_block *this, unsigned long mode, 85 void *cmd) 86 { 87 unsigned int wcr_enable = IMX2_WDT_WCR_WDE; 88 struct imx2_wdt_device *wdev = container_of(this, 89 struct imx2_wdt_device, 90 restart_handler); 91 /* Assert SRS signal */ 92 regmap_write(wdev->regmap, 0, wcr_enable); 93 /* 94 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be 95 * written twice), we add another two writes to ensure there must be at 96 * least two writes happen in the same one 32kHz clock period. We save 97 * the target check here, since the writes shouldn't be a huge burden 98 * for other platforms. 99 */ 100 regmap_write(wdev->regmap, 0, wcr_enable); 101 regmap_write(wdev->regmap, 0, wcr_enable); 102 103 /* wait for reset to assert... */ 104 mdelay(500); 105 106 return NOTIFY_DONE; 107 } 108 109 static inline void imx2_wdt_setup(struct watchdog_device *wdog) 110 { 111 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 112 u32 val; 113 114 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val); 115 116 /* Suspend timer in low power mode, write once-only */ 117 val |= IMX2_WDT_WCR_WDZST; 118 /* Strip the old watchdog Time-Out value */ 119 val &= ~IMX2_WDT_WCR_WT; 120 /* Generate reset if WDOG times out */ 121 val &= ~IMX2_WDT_WCR_WRE; 122 /* Keep Watchdog Disabled */ 123 val &= ~IMX2_WDT_WCR_WDE; 124 /* Set the watchdog's Time-Out value */ 125 val |= WDOG_SEC_TO_COUNT(wdog->timeout); 126 127 regmap_write(wdev->regmap, IMX2_WDT_WCR, val); 128 129 /* enable the watchdog */ 130 val |= IMX2_WDT_WCR_WDE; 131 regmap_write(wdev->regmap, IMX2_WDT_WCR, val); 132 } 133 134 static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev) 135 { 136 u32 val; 137 138 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val); 139 140 return val & IMX2_WDT_WCR_WDE; 141 } 142 143 static int imx2_wdt_ping(struct watchdog_device *wdog) 144 { 145 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 146 147 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1); 148 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2); 149 return 0; 150 } 151 152 static void imx2_wdt_timer_ping(unsigned long arg) 153 { 154 struct watchdog_device *wdog = (struct watchdog_device *)arg; 155 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 156 157 /* ping it every wdog->timeout / 2 seconds to prevent reboot */ 158 imx2_wdt_ping(wdog); 159 mod_timer(&wdev->timer, jiffies + wdog->timeout * HZ / 2); 160 } 161 162 static int imx2_wdt_set_timeout(struct watchdog_device *wdog, 163 unsigned int new_timeout) 164 { 165 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 166 167 regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT, 168 WDOG_SEC_TO_COUNT(new_timeout)); 169 return 0; 170 } 171 172 static int imx2_wdt_start(struct watchdog_device *wdog) 173 { 174 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 175 176 if (imx2_wdt_is_running(wdev)) { 177 /* delete the timer that pings the watchdog after close */ 178 del_timer_sync(&wdev->timer); 179 imx2_wdt_set_timeout(wdog, wdog->timeout); 180 } else 181 imx2_wdt_setup(wdog); 182 183 return imx2_wdt_ping(wdog); 184 } 185 186 static int imx2_wdt_stop(struct watchdog_device *wdog) 187 { 188 /* 189 * We don't need a clk_disable, it cannot be disabled once started. 190 * We use a timer to ping the watchdog while /dev/watchdog is closed 191 */ 192 imx2_wdt_timer_ping((unsigned long)wdog); 193 return 0; 194 } 195 196 static inline void imx2_wdt_ping_if_active(struct watchdog_device *wdog) 197 { 198 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 199 200 if (imx2_wdt_is_running(wdev)) { 201 imx2_wdt_set_timeout(wdog, wdog->timeout); 202 imx2_wdt_timer_ping((unsigned long)wdog); 203 } 204 } 205 206 static struct watchdog_ops imx2_wdt_ops = { 207 .owner = THIS_MODULE, 208 .start = imx2_wdt_start, 209 .stop = imx2_wdt_stop, 210 .ping = imx2_wdt_ping, 211 .set_timeout = imx2_wdt_set_timeout, 212 }; 213 214 static struct regmap_config imx2_wdt_regmap_config = { 215 .reg_bits = 16, 216 .reg_stride = 2, 217 .val_bits = 16, 218 .max_register = 0x8, 219 }; 220 221 static int __init imx2_wdt_probe(struct platform_device *pdev) 222 { 223 struct imx2_wdt_device *wdev; 224 struct watchdog_device *wdog; 225 struct resource *res; 226 void __iomem *base; 227 int ret; 228 u32 val; 229 230 wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL); 231 if (!wdev) 232 return -ENOMEM; 233 234 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 235 base = devm_ioremap_resource(&pdev->dev, res); 236 if (IS_ERR(base)) 237 return PTR_ERR(base); 238 239 wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base, 240 &imx2_wdt_regmap_config); 241 if (IS_ERR(wdev->regmap)) { 242 dev_err(&pdev->dev, "regmap init failed\n"); 243 return PTR_ERR(wdev->regmap); 244 } 245 246 wdev->clk = devm_clk_get(&pdev->dev, NULL); 247 if (IS_ERR(wdev->clk)) { 248 dev_err(&pdev->dev, "can't get Watchdog clock\n"); 249 return PTR_ERR(wdev->clk); 250 } 251 252 wdog = &wdev->wdog; 253 wdog->info = &imx2_wdt_info; 254 wdog->ops = &imx2_wdt_ops; 255 wdog->min_timeout = 1; 256 wdog->max_timeout = IMX2_WDT_MAX_TIME; 257 258 clk_prepare_enable(wdev->clk); 259 260 regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val); 261 wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0; 262 263 wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME); 264 if (wdog->timeout != timeout) 265 dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n", 266 timeout, wdog->timeout); 267 268 platform_set_drvdata(pdev, wdog); 269 watchdog_set_drvdata(wdog, wdev); 270 watchdog_set_nowayout(wdog, nowayout); 271 watchdog_init_timeout(wdog, timeout, &pdev->dev); 272 273 setup_timer(&wdev->timer, imx2_wdt_timer_ping, (unsigned long)wdog); 274 275 imx2_wdt_ping_if_active(wdog); 276 277 ret = watchdog_register_device(wdog); 278 if (ret) { 279 dev_err(&pdev->dev, "cannot register watchdog device\n"); 280 return ret; 281 } 282 283 wdev->restart_handler.notifier_call = imx2_restart_handler; 284 wdev->restart_handler.priority = 128; 285 ret = register_restart_handler(&wdev->restart_handler); 286 if (ret) 287 dev_err(&pdev->dev, "cannot register restart handler\n"); 288 289 dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n", 290 wdog->timeout, nowayout); 291 292 return 0; 293 } 294 295 static int __exit imx2_wdt_remove(struct platform_device *pdev) 296 { 297 struct watchdog_device *wdog = platform_get_drvdata(pdev); 298 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 299 300 unregister_restart_handler(&wdev->restart_handler); 301 302 watchdog_unregister_device(wdog); 303 304 if (imx2_wdt_is_running(wdev)) { 305 del_timer_sync(&wdev->timer); 306 imx2_wdt_ping(wdog); 307 dev_crit(&pdev->dev, "Device removed: Expect reboot!\n"); 308 } 309 return 0; 310 } 311 312 static void imx2_wdt_shutdown(struct platform_device *pdev) 313 { 314 struct watchdog_device *wdog = platform_get_drvdata(pdev); 315 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 316 317 if (imx2_wdt_is_running(wdev)) { 318 /* 319 * We are running, we need to delete the timer but will 320 * give max timeout before reboot will take place 321 */ 322 del_timer_sync(&wdev->timer); 323 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME); 324 imx2_wdt_ping(wdog); 325 dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n"); 326 } 327 } 328 329 #ifdef CONFIG_PM_SLEEP 330 /* Disable watchdog if it is active during suspend */ 331 static int imx2_wdt_suspend(struct device *dev) 332 { 333 struct watchdog_device *wdog = dev_get_drvdata(dev); 334 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 335 336 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME); 337 imx2_wdt_ping(wdog); 338 339 /* Watchdog has been stopped but IP block is still running */ 340 if (!watchdog_active(wdog) && imx2_wdt_is_running(wdev)) 341 del_timer_sync(&wdev->timer); 342 343 clk_disable_unprepare(wdev->clk); 344 345 return 0; 346 } 347 348 /* Enable watchdog and configure it if necessary */ 349 static int imx2_wdt_resume(struct device *dev) 350 { 351 struct watchdog_device *wdog = dev_get_drvdata(dev); 352 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 353 354 clk_prepare_enable(wdev->clk); 355 356 if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) { 357 /* Resumes from deep sleep we need restart 358 * the watchdog again. 359 */ 360 imx2_wdt_setup(wdog); 361 imx2_wdt_set_timeout(wdog, wdog->timeout); 362 imx2_wdt_ping(wdog); 363 } else if (imx2_wdt_is_running(wdev)) { 364 imx2_wdt_ping(wdog); 365 mod_timer(&wdev->timer, jiffies + wdog->timeout * HZ / 2); 366 } 367 368 return 0; 369 } 370 #endif 371 372 static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend, 373 imx2_wdt_resume); 374 375 static const struct of_device_id imx2_wdt_dt_ids[] = { 376 { .compatible = "fsl,imx21-wdt", }, 377 { /* sentinel */ } 378 }; 379 MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids); 380 381 static struct platform_driver imx2_wdt_driver = { 382 .remove = __exit_p(imx2_wdt_remove), 383 .shutdown = imx2_wdt_shutdown, 384 .driver = { 385 .name = DRIVER_NAME, 386 .pm = &imx2_wdt_pm_ops, 387 .of_match_table = imx2_wdt_dt_ids, 388 }, 389 }; 390 391 module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe); 392 393 MODULE_AUTHOR("Wolfram Sang"); 394 MODULE_DESCRIPTION("Watchdog driver for IMX2 and later"); 395 MODULE_LICENSE("GPL v2"); 396 MODULE_ALIAS("platform:" DRIVER_NAME); 397