1 /* 2 * Watchdog driver for IMX2 and later processors 3 * 4 * Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de> 5 * Copyright (C) 2014 Freescale Semiconductor, Inc. 6 * 7 * some parts adapted by similar drivers from Darius Augulis and Vladimir 8 * Zapolskiy, additional improvements by Wim Van Sebroeck. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published by 12 * the Free Software Foundation. 13 * 14 * NOTE: MX1 has a slightly different Watchdog than MX2 and later: 15 * 16 * MX1: MX2+: 17 * ---- ----- 18 * Registers: 32-bit 16-bit 19 * Stopable timer: Yes No 20 * Need to enable clk: No Yes 21 * Halt on suspend: Manual Can be automatic 22 */ 23 24 #include <linux/clk.h> 25 #include <linux/delay.h> 26 #include <linux/init.h> 27 #include <linux/io.h> 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/moduleparam.h> 31 #include <linux/of_address.h> 32 #include <linux/platform_device.h> 33 #include <linux/regmap.h> 34 #include <linux/watchdog.h> 35 36 #define DRIVER_NAME "imx2-wdt" 37 38 #define IMX2_WDT_WCR 0x00 /* Control Register */ 39 #define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */ 40 #define IMX2_WDT_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */ 41 #define IMX2_WDT_WCR_WDE (1 << 2) /* -> Watchdog Enable */ 42 #define IMX2_WDT_WCR_WDZST (1 << 0) /* -> Watchdog timer Suspend */ 43 44 #define IMX2_WDT_WSR 0x02 /* Service Register */ 45 #define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */ 46 #define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */ 47 48 #define IMX2_WDT_WRSR 0x04 /* Reset Status Register */ 49 #define IMX2_WDT_WRSR_TOUT (1 << 1) /* -> Reset due to Timeout */ 50 51 #define IMX2_WDT_WMCR 0x08 /* Misc Register */ 52 53 #define IMX2_WDT_MAX_TIME 128 54 #define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */ 55 56 #define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8) 57 58 struct imx2_wdt_device { 59 struct clk *clk; 60 struct regmap *regmap; 61 struct watchdog_device wdog; 62 }; 63 64 static bool nowayout = WATCHDOG_NOWAYOUT; 65 module_param(nowayout, bool, 0); 66 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" 67 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 68 69 70 static unsigned timeout = IMX2_WDT_DEFAULT_TIME; 71 module_param(timeout, uint, 0); 72 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default=" 73 __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")"); 74 75 static const struct watchdog_info imx2_wdt_info = { 76 .identity = "imx2+ watchdog", 77 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, 78 }; 79 80 static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action, 81 void *data) 82 { 83 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 84 unsigned int wcr_enable = IMX2_WDT_WCR_WDE; 85 86 /* Assert SRS signal */ 87 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable); 88 /* 89 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be 90 * written twice), we add another two writes to ensure there must be at 91 * least two writes happen in the same one 32kHz clock period. We save 92 * the target check here, since the writes shouldn't be a huge burden 93 * for other platforms. 94 */ 95 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable); 96 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable); 97 98 /* wait for reset to assert... */ 99 mdelay(500); 100 101 return 0; 102 } 103 104 static inline void imx2_wdt_setup(struct watchdog_device *wdog) 105 { 106 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 107 u32 val; 108 109 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val); 110 111 /* Suspend timer in low power mode, write once-only */ 112 val |= IMX2_WDT_WCR_WDZST; 113 /* Strip the old watchdog Time-Out value */ 114 val &= ~IMX2_WDT_WCR_WT; 115 /* Generate reset if WDOG times out */ 116 val &= ~IMX2_WDT_WCR_WRE; 117 /* Keep Watchdog Disabled */ 118 val &= ~IMX2_WDT_WCR_WDE; 119 /* Set the watchdog's Time-Out value */ 120 val |= WDOG_SEC_TO_COUNT(wdog->timeout); 121 122 regmap_write(wdev->regmap, IMX2_WDT_WCR, val); 123 124 /* enable the watchdog */ 125 val |= IMX2_WDT_WCR_WDE; 126 regmap_write(wdev->regmap, IMX2_WDT_WCR, val); 127 } 128 129 static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev) 130 { 131 u32 val; 132 133 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val); 134 135 return val & IMX2_WDT_WCR_WDE; 136 } 137 138 static int imx2_wdt_ping(struct watchdog_device *wdog) 139 { 140 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 141 142 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1); 143 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2); 144 return 0; 145 } 146 147 static int imx2_wdt_set_timeout(struct watchdog_device *wdog, 148 unsigned int new_timeout) 149 { 150 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 151 152 wdog->timeout = new_timeout; 153 154 regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT, 155 WDOG_SEC_TO_COUNT(new_timeout)); 156 return 0; 157 } 158 159 static int imx2_wdt_start(struct watchdog_device *wdog) 160 { 161 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 162 163 if (imx2_wdt_is_running(wdev)) 164 imx2_wdt_set_timeout(wdog, wdog->timeout); 165 else 166 imx2_wdt_setup(wdog); 167 168 set_bit(WDOG_HW_RUNNING, &wdog->status); 169 170 return imx2_wdt_ping(wdog); 171 } 172 173 static const struct watchdog_ops imx2_wdt_ops = { 174 .owner = THIS_MODULE, 175 .start = imx2_wdt_start, 176 .ping = imx2_wdt_ping, 177 .set_timeout = imx2_wdt_set_timeout, 178 .restart = imx2_wdt_restart, 179 }; 180 181 static const struct regmap_config imx2_wdt_regmap_config = { 182 .reg_bits = 16, 183 .reg_stride = 2, 184 .val_bits = 16, 185 .max_register = 0x8, 186 }; 187 188 static int __init imx2_wdt_probe(struct platform_device *pdev) 189 { 190 struct imx2_wdt_device *wdev; 191 struct watchdog_device *wdog; 192 struct resource *res; 193 void __iomem *base; 194 int ret; 195 u32 val; 196 197 wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL); 198 if (!wdev) 199 return -ENOMEM; 200 201 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 202 base = devm_ioremap_resource(&pdev->dev, res); 203 if (IS_ERR(base)) 204 return PTR_ERR(base); 205 206 wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base, 207 &imx2_wdt_regmap_config); 208 if (IS_ERR(wdev->regmap)) { 209 dev_err(&pdev->dev, "regmap init failed\n"); 210 return PTR_ERR(wdev->regmap); 211 } 212 213 wdev->clk = devm_clk_get(&pdev->dev, NULL); 214 if (IS_ERR(wdev->clk)) { 215 dev_err(&pdev->dev, "can't get Watchdog clock\n"); 216 return PTR_ERR(wdev->clk); 217 } 218 219 wdog = &wdev->wdog; 220 wdog->info = &imx2_wdt_info; 221 wdog->ops = &imx2_wdt_ops; 222 wdog->min_timeout = 1; 223 wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000; 224 wdog->parent = &pdev->dev; 225 226 ret = clk_prepare_enable(wdev->clk); 227 if (ret) 228 return ret; 229 230 regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val); 231 wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0; 232 233 wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME); 234 if (wdog->timeout != timeout) 235 dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n", 236 timeout, wdog->timeout); 237 238 platform_set_drvdata(pdev, wdog); 239 watchdog_set_drvdata(wdog, wdev); 240 watchdog_set_nowayout(wdog, nowayout); 241 watchdog_set_restart_priority(wdog, 128); 242 watchdog_init_timeout(wdog, timeout, &pdev->dev); 243 244 if (imx2_wdt_is_running(wdev)) { 245 imx2_wdt_set_timeout(wdog, wdog->timeout); 246 set_bit(WDOG_HW_RUNNING, &wdog->status); 247 } 248 249 /* 250 * Disable the watchdog power down counter at boot. Otherwise the power 251 * down counter will pull down the #WDOG interrupt line for one clock 252 * cycle. 253 */ 254 regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0); 255 256 ret = watchdog_register_device(wdog); 257 if (ret) { 258 dev_err(&pdev->dev, "cannot register watchdog device\n"); 259 goto disable_clk; 260 } 261 262 dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n", 263 wdog->timeout, nowayout); 264 265 return 0; 266 267 disable_clk: 268 clk_disable_unprepare(wdev->clk); 269 return ret; 270 } 271 272 static int __exit imx2_wdt_remove(struct platform_device *pdev) 273 { 274 struct watchdog_device *wdog = platform_get_drvdata(pdev); 275 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 276 277 watchdog_unregister_device(wdog); 278 279 if (imx2_wdt_is_running(wdev)) { 280 imx2_wdt_ping(wdog); 281 dev_crit(&pdev->dev, "Device removed: Expect reboot!\n"); 282 } 283 return 0; 284 } 285 286 static void imx2_wdt_shutdown(struct platform_device *pdev) 287 { 288 struct watchdog_device *wdog = platform_get_drvdata(pdev); 289 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 290 291 if (imx2_wdt_is_running(wdev)) { 292 /* 293 * We are running, configure max timeout before reboot 294 * will take place. 295 */ 296 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME); 297 imx2_wdt_ping(wdog); 298 dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n"); 299 } 300 } 301 302 #ifdef CONFIG_PM_SLEEP 303 /* Disable watchdog if it is active or non-active but still running */ 304 static int imx2_wdt_suspend(struct device *dev) 305 { 306 struct watchdog_device *wdog = dev_get_drvdata(dev); 307 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 308 309 /* The watchdog IP block is running */ 310 if (imx2_wdt_is_running(wdev)) { 311 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME); 312 imx2_wdt_ping(wdog); 313 } 314 315 clk_disable_unprepare(wdev->clk); 316 317 return 0; 318 } 319 320 /* Enable watchdog and configure it if necessary */ 321 static int imx2_wdt_resume(struct device *dev) 322 { 323 struct watchdog_device *wdog = dev_get_drvdata(dev); 324 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 325 int ret; 326 327 ret = clk_prepare_enable(wdev->clk); 328 if (ret) 329 return ret; 330 331 if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) { 332 /* 333 * If the watchdog is still active and resumes 334 * from deep sleep state, need to restart the 335 * watchdog again. 336 */ 337 imx2_wdt_setup(wdog); 338 } 339 if (imx2_wdt_is_running(wdev)) { 340 imx2_wdt_set_timeout(wdog, wdog->timeout); 341 imx2_wdt_ping(wdog); 342 } 343 344 return 0; 345 } 346 #endif 347 348 static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend, 349 imx2_wdt_resume); 350 351 static const struct of_device_id imx2_wdt_dt_ids[] = { 352 { .compatible = "fsl,imx21-wdt", }, 353 { /* sentinel */ } 354 }; 355 MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids); 356 357 static struct platform_driver imx2_wdt_driver = { 358 .remove = __exit_p(imx2_wdt_remove), 359 .shutdown = imx2_wdt_shutdown, 360 .driver = { 361 .name = DRIVER_NAME, 362 .pm = &imx2_wdt_pm_ops, 363 .of_match_table = imx2_wdt_dt_ids, 364 }, 365 }; 366 367 module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe); 368 369 MODULE_AUTHOR("Wolfram Sang"); 370 MODULE_DESCRIPTION("Watchdog driver for IMX2 and later"); 371 MODULE_LICENSE("GPL v2"); 372 MODULE_ALIAS("platform:" DRIVER_NAME); 373