1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Watchdog driver for IMX2 and later processors 4 * 5 * Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <kernel@pengutronix.de> 6 * Copyright (C) 2014 Freescale Semiconductor, Inc. 7 * 8 * some parts adapted by similar drivers from Darius Augulis and Vladimir 9 * Zapolskiy, additional improvements by Wim Van Sebroeck. 10 * 11 * NOTE: MX1 has a slightly different Watchdog than MX2 and later: 12 * 13 * MX1: MX2+: 14 * ---- ----- 15 * Registers: 32-bit 16-bit 16 * Stopable timer: Yes No 17 * Need to enable clk: No Yes 18 * Halt on suspend: Manual Can be automatic 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/delay.h> 23 #include <linux/init.h> 24 #include <linux/interrupt.h> 25 #include <linux/io.h> 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/moduleparam.h> 29 #include <linux/of_address.h> 30 #include <linux/of_device.h> 31 #include <linux/platform_device.h> 32 #include <linux/regmap.h> 33 #include <linux/watchdog.h> 34 35 #define DRIVER_NAME "imx2-wdt" 36 37 #define IMX2_WDT_WCR 0x00 /* Control Register */ 38 #define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */ 39 #define IMX2_WDT_WCR_WDW BIT(7) /* -> Watchdog disable for WAIT */ 40 #define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */ 41 #define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */ 42 #define IMX2_WDT_WCR_WRE BIT(3) /* -> WDOG Reset Enable */ 43 #define IMX2_WDT_WCR_WDE BIT(2) /* -> Watchdog Enable */ 44 #define IMX2_WDT_WCR_WDZST BIT(0) /* -> Watchdog timer Suspend */ 45 46 #define IMX2_WDT_WSR 0x02 /* Service Register */ 47 #define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */ 48 #define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */ 49 50 #define IMX2_WDT_WRSR 0x04 /* Reset Status Register */ 51 #define IMX2_WDT_WRSR_TOUT BIT(1) /* -> Reset due to Timeout */ 52 53 #define IMX2_WDT_WICR 0x06 /* Interrupt Control Register */ 54 #define IMX2_WDT_WICR_WIE BIT(15) /* -> Interrupt Enable */ 55 #define IMX2_WDT_WICR_WTIS BIT(14) /* -> Interrupt Status */ 56 #define IMX2_WDT_WICR_WICT 0xFF /* -> Interrupt Count Timeout */ 57 58 #define IMX2_WDT_WMCR 0x08 /* Misc Register */ 59 60 #define IMX2_WDT_MAX_TIME 128U 61 #define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */ 62 63 #define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8) 64 65 struct imx2_wdt_data { 66 bool wdw_supported; 67 }; 68 69 struct imx2_wdt_device { 70 struct clk *clk; 71 struct regmap *regmap; 72 struct watchdog_device wdog; 73 const struct imx2_wdt_data *data; 74 bool ext_reset; 75 bool clk_is_on; 76 bool no_ping; 77 bool sleep_wait; 78 }; 79 80 static bool nowayout = WATCHDOG_NOWAYOUT; 81 module_param(nowayout, bool, 0); 82 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" 83 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 84 85 static unsigned timeout; 86 module_param(timeout, uint, 0); 87 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default=" 88 __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")"); 89 90 static const struct watchdog_info imx2_wdt_info = { 91 .identity = "imx2+ watchdog", 92 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, 93 }; 94 95 static const struct watchdog_info imx2_wdt_pretimeout_info = { 96 .identity = "imx2+ watchdog", 97 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | 98 WDIOF_PRETIMEOUT, 99 }; 100 101 static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action, 102 void *data) 103 { 104 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 105 unsigned int wcr_enable = IMX2_WDT_WCR_WDE; 106 107 /* Use internal reset or external - not both */ 108 if (wdev->ext_reset) 109 wcr_enable |= IMX2_WDT_WCR_SRS; /* do not assert int reset */ 110 else 111 wcr_enable |= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */ 112 113 /* Assert SRS signal */ 114 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable); 115 /* 116 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be 117 * written twice), we add another two writes to ensure there must be at 118 * least two writes happen in the same one 32kHz clock period. We save 119 * the target check here, since the writes shouldn't be a huge burden 120 * for other platforms. 121 */ 122 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable); 123 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable); 124 125 /* wait for reset to assert... */ 126 mdelay(500); 127 128 return 0; 129 } 130 131 static inline void imx2_wdt_setup(struct watchdog_device *wdog) 132 { 133 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 134 u32 val; 135 136 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val); 137 138 /* Suspend timer in low power mode, write once-only */ 139 val |= IMX2_WDT_WCR_WDZST; 140 /* Suspend timer in low power WAIT mode, write once-only */ 141 if (wdev->sleep_wait) 142 val |= IMX2_WDT_WCR_WDW; 143 /* Strip the old watchdog Time-Out value */ 144 val &= ~IMX2_WDT_WCR_WT; 145 /* Generate internal chip-level reset if WDOG times out */ 146 if (!wdev->ext_reset) 147 val &= ~IMX2_WDT_WCR_WRE; 148 /* Or if external-reset assert WDOG_B reset only on time-out */ 149 else 150 val |= IMX2_WDT_WCR_WRE; 151 /* Keep Watchdog Disabled */ 152 val &= ~IMX2_WDT_WCR_WDE; 153 /* Set the watchdog's Time-Out value */ 154 val |= WDOG_SEC_TO_COUNT(wdog->timeout); 155 156 regmap_write(wdev->regmap, IMX2_WDT_WCR, val); 157 158 /* enable the watchdog */ 159 val |= IMX2_WDT_WCR_WDE; 160 regmap_write(wdev->regmap, IMX2_WDT_WCR, val); 161 } 162 163 static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev) 164 { 165 u32 val; 166 167 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val); 168 169 return val & IMX2_WDT_WCR_WDE; 170 } 171 172 static int imx2_wdt_ping(struct watchdog_device *wdog) 173 { 174 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 175 176 if (!wdev->clk_is_on) 177 return 0; 178 179 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1); 180 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2); 181 return 0; 182 } 183 184 static void __imx2_wdt_set_timeout(struct watchdog_device *wdog, 185 unsigned int new_timeout) 186 { 187 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 188 189 regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT, 190 WDOG_SEC_TO_COUNT(new_timeout)); 191 } 192 193 static int imx2_wdt_set_timeout(struct watchdog_device *wdog, 194 unsigned int new_timeout) 195 { 196 unsigned int actual; 197 198 actual = min(new_timeout, IMX2_WDT_MAX_TIME); 199 __imx2_wdt_set_timeout(wdog, actual); 200 wdog->timeout = new_timeout; 201 return 0; 202 } 203 204 static int imx2_wdt_set_pretimeout(struct watchdog_device *wdog, 205 unsigned int new_pretimeout) 206 { 207 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 208 209 if (new_pretimeout >= IMX2_WDT_MAX_TIME) 210 return -EINVAL; 211 212 wdog->pretimeout = new_pretimeout; 213 214 regmap_update_bits(wdev->regmap, IMX2_WDT_WICR, 215 IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT, 216 IMX2_WDT_WICR_WIE | (new_pretimeout << 1)); 217 return 0; 218 } 219 220 static irqreturn_t imx2_wdt_isr(int irq, void *wdog_arg) 221 { 222 struct watchdog_device *wdog = wdog_arg; 223 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 224 225 regmap_write_bits(wdev->regmap, IMX2_WDT_WICR, 226 IMX2_WDT_WICR_WTIS, IMX2_WDT_WICR_WTIS); 227 228 watchdog_notify_pretimeout(wdog); 229 230 return IRQ_HANDLED; 231 } 232 233 static int imx2_wdt_start(struct watchdog_device *wdog) 234 { 235 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 236 237 if (imx2_wdt_is_running(wdev)) 238 imx2_wdt_set_timeout(wdog, wdog->timeout); 239 else 240 imx2_wdt_setup(wdog); 241 242 set_bit(WDOG_HW_RUNNING, &wdog->status); 243 244 return imx2_wdt_ping(wdog); 245 } 246 247 static const struct watchdog_ops imx2_wdt_ops = { 248 .owner = THIS_MODULE, 249 .start = imx2_wdt_start, 250 .ping = imx2_wdt_ping, 251 .set_timeout = imx2_wdt_set_timeout, 252 .set_pretimeout = imx2_wdt_set_pretimeout, 253 .restart = imx2_wdt_restart, 254 }; 255 256 static const struct regmap_config imx2_wdt_regmap_config = { 257 .reg_bits = 16, 258 .reg_stride = 2, 259 .val_bits = 16, 260 .max_register = 0x8, 261 }; 262 263 static void imx2_wdt_action(void *data) 264 { 265 clk_disable_unprepare(data); 266 } 267 268 static int __init imx2_wdt_probe(struct platform_device *pdev) 269 { 270 struct device *dev = &pdev->dev; 271 struct imx2_wdt_device *wdev; 272 struct watchdog_device *wdog; 273 void __iomem *base; 274 int ret; 275 u32 val; 276 277 wdev = devm_kzalloc(dev, sizeof(*wdev), GFP_KERNEL); 278 if (!wdev) 279 return -ENOMEM; 280 281 base = devm_platform_ioremap_resource(pdev, 0); 282 if (IS_ERR(base)) 283 return PTR_ERR(base); 284 285 wdev->regmap = devm_regmap_init_mmio_clk(dev, NULL, base, 286 &imx2_wdt_regmap_config); 287 if (IS_ERR(wdev->regmap)) { 288 dev_err(dev, "regmap init failed\n"); 289 return PTR_ERR(wdev->regmap); 290 } 291 292 wdev->clk = devm_clk_get(dev, NULL); 293 if (IS_ERR(wdev->clk)) { 294 dev_err(dev, "can't get Watchdog clock\n"); 295 return PTR_ERR(wdev->clk); 296 } 297 298 wdog = &wdev->wdog; 299 wdog->info = &imx2_wdt_info; 300 wdog->ops = &imx2_wdt_ops; 301 wdog->min_timeout = 1; 302 wdog->timeout = IMX2_WDT_DEFAULT_TIME; 303 wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000; 304 wdog->parent = dev; 305 306 wdev->data = of_device_get_match_data(dev); 307 308 ret = platform_get_irq(pdev, 0); 309 if (ret > 0) 310 if (!devm_request_irq(dev, ret, imx2_wdt_isr, 0, 311 dev_name(dev), wdog)) 312 wdog->info = &imx2_wdt_pretimeout_info; 313 314 ret = clk_prepare_enable(wdev->clk); 315 if (ret) 316 return ret; 317 318 ret = devm_add_action_or_reset(dev, imx2_wdt_action, wdev->clk); 319 if (ret) 320 return ret; 321 322 wdev->clk_is_on = true; 323 324 regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val); 325 wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0; 326 327 wdev->ext_reset = of_property_read_bool(dev->of_node, 328 "fsl,ext-reset-output"); 329 330 if (of_property_read_bool(dev->of_node, "fsl,suspend-in-wait")) { 331 if (!wdev->data->wdw_supported) { 332 dev_err(dev, "suspend-in-wait not supported\n"); 333 return -EINVAL; 334 } 335 wdev->sleep_wait = true; 336 } 337 338 /* 339 * The i.MX7D doesn't support low power mode, so we need to ping the watchdog 340 * during suspend. Interaction with "fsl,suspend-in-wait" is unknown! 341 */ 342 wdev->no_ping = !of_device_is_compatible(dev->of_node, "fsl,imx7d-wdt"); 343 platform_set_drvdata(pdev, wdog); 344 watchdog_set_drvdata(wdog, wdev); 345 watchdog_set_nowayout(wdog, nowayout); 346 watchdog_set_restart_priority(wdog, 128); 347 watchdog_init_timeout(wdog, timeout, dev); 348 if (wdev->no_ping) 349 watchdog_stop_ping_on_suspend(wdog); 350 351 if (imx2_wdt_is_running(wdev)) { 352 imx2_wdt_set_timeout(wdog, wdog->timeout); 353 set_bit(WDOG_HW_RUNNING, &wdog->status); 354 } 355 356 /* 357 * Disable the watchdog power down counter at boot. Otherwise the power 358 * down counter will pull down the #WDOG interrupt line for one clock 359 * cycle. 360 */ 361 regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0); 362 363 return devm_watchdog_register_device(dev, wdog); 364 } 365 366 static void imx2_wdt_shutdown(struct platform_device *pdev) 367 { 368 struct watchdog_device *wdog = platform_get_drvdata(pdev); 369 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 370 371 if (imx2_wdt_is_running(wdev)) { 372 /* 373 * We are running, configure max timeout before reboot 374 * will take place. 375 */ 376 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME); 377 imx2_wdt_ping(wdog); 378 dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n"); 379 } 380 } 381 382 /* Disable watchdog if it is active or non-active but still running */ 383 static int __maybe_unused imx2_wdt_suspend(struct device *dev) 384 { 385 struct watchdog_device *wdog = dev_get_drvdata(dev); 386 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 387 388 /* The watchdog IP block is running */ 389 if (imx2_wdt_is_running(wdev)) { 390 /* 391 * Don't update wdog->timeout, we'll restore the current value 392 * during resume. 393 */ 394 __imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME); 395 imx2_wdt_ping(wdog); 396 } 397 398 if (wdev->no_ping) { 399 clk_disable_unprepare(wdev->clk); 400 401 wdev->clk_is_on = false; 402 } 403 404 return 0; 405 } 406 407 /* Enable watchdog and configure it if necessary */ 408 static int __maybe_unused imx2_wdt_resume(struct device *dev) 409 { 410 struct watchdog_device *wdog = dev_get_drvdata(dev); 411 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); 412 int ret; 413 414 if (wdev->no_ping) { 415 ret = clk_prepare_enable(wdev->clk); 416 417 if (ret) 418 return ret; 419 420 wdev->clk_is_on = true; 421 } 422 423 if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) { 424 /* 425 * If the watchdog is still active and resumes 426 * from deep sleep state, need to restart the 427 * watchdog again. 428 */ 429 imx2_wdt_setup(wdog); 430 } 431 if (imx2_wdt_is_running(wdev)) { 432 imx2_wdt_set_timeout(wdog, wdog->timeout); 433 imx2_wdt_ping(wdog); 434 } 435 436 return 0; 437 } 438 439 static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend, 440 imx2_wdt_resume); 441 442 struct imx2_wdt_data imx_wdt = { 443 .wdw_supported = true, 444 }; 445 446 struct imx2_wdt_data imx_wdt_legacy = { 447 .wdw_supported = false, 448 }; 449 450 static const struct of_device_id imx2_wdt_dt_ids[] = { 451 { .compatible = "fsl,imx21-wdt", .data = &imx_wdt_legacy }, 452 { .compatible = "fsl,imx25-wdt", .data = &imx_wdt }, 453 { .compatible = "fsl,imx27-wdt", .data = &imx_wdt_legacy }, 454 { .compatible = "fsl,imx31-wdt", .data = &imx_wdt_legacy }, 455 { .compatible = "fsl,imx35-wdt", .data = &imx_wdt }, 456 { .compatible = "fsl,imx50-wdt", .data = &imx_wdt }, 457 { .compatible = "fsl,imx51-wdt", .data = &imx_wdt }, 458 { .compatible = "fsl,imx53-wdt", .data = &imx_wdt }, 459 { .compatible = "fsl,imx6q-wdt", .data = &imx_wdt }, 460 { .compatible = "fsl,imx6sl-wdt", .data = &imx_wdt }, 461 { .compatible = "fsl,imx6sll-wdt", .data = &imx_wdt }, 462 { .compatible = "fsl,imx6sx-wdt", .data = &imx_wdt }, 463 { .compatible = "fsl,imx6ul-wdt", .data = &imx_wdt }, 464 { .compatible = "fsl,imx7d-wdt", .data = &imx_wdt }, 465 { .compatible = "fsl,imx8mm-wdt", .data = &imx_wdt }, 466 { .compatible = "fsl,imx8mn-wdt", .data = &imx_wdt }, 467 { .compatible = "fsl,imx8mp-wdt", .data = &imx_wdt }, 468 { .compatible = "fsl,imx8mq-wdt", .data = &imx_wdt }, 469 { .compatible = "fsl,ls1012a-wdt", .data = &imx_wdt_legacy }, 470 { .compatible = "fsl,ls1043a-wdt", .data = &imx_wdt_legacy }, 471 { .compatible = "fsl,vf610-wdt", .data = &imx_wdt }, 472 { /* sentinel */ } 473 }; 474 MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids); 475 476 static struct platform_driver imx2_wdt_driver = { 477 .shutdown = imx2_wdt_shutdown, 478 .driver = { 479 .name = DRIVER_NAME, 480 .pm = &imx2_wdt_pm_ops, 481 .of_match_table = imx2_wdt_dt_ids, 482 }, 483 }; 484 485 module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe); 486 487 MODULE_AUTHOR("Wolfram Sang"); 488 MODULE_DESCRIPTION("Watchdog driver for IMX2 and later"); 489 MODULE_LICENSE("GPL v2"); 490 MODULE_ALIAS("platform:" DRIVER_NAME); 491