1 /* 2 * Imagination Technologies PowerDown Controller Watchdog Timer. 3 * 4 * Copyright (c) 2014 Imagination Technologies Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 * 10 * Based on drivers/watchdog/sunxi_wdt.c Copyright (c) 2013 Carlo Caione 11 * 2012 Henrik Nordstrom 12 * 13 * Notes 14 * ----- 15 * The timeout value is rounded to the next power of two clock cycles. 16 * This is configured using the PDC_WDT_CONFIG register, according to this 17 * formula: 18 * 19 * timeout = 2^(delay + 1) clock cycles 20 * 21 * Where 'delay' is the value written in PDC_WDT_CONFIG register. 22 * 23 * Therefore, the hardware only allows to program watchdog timeouts, expressed 24 * as a power of two number of watchdog clock cycles. The current implementation 25 * guarantees that the actual watchdog timeout will be _at least_ the value 26 * programmed in the imgpdg_wdt driver. 27 * 28 * The following table shows how the user-configured timeout relates 29 * to the actual hardware timeout (watchdog clock @ 40000 Hz): 30 * 31 * input timeout | WD_DELAY | actual timeout 32 * ----------------------------------- 33 * 10 | 18 | 13 seconds 34 * 20 | 19 | 26 seconds 35 * 30 | 20 | 52 seconds 36 * 60 | 21 | 104 seconds 37 * 38 * Albeit coarse, this granularity would suffice most watchdog uses. 39 * If the platform allows it, the user should be able to change the watchdog 40 * clock rate and achieve a finer timeout granularity. 41 */ 42 43 #include <linux/clk.h> 44 #include <linux/io.h> 45 #include <linux/log2.h> 46 #include <linux/module.h> 47 #include <linux/mod_devicetable.h> 48 #include <linux/platform_device.h> 49 #include <linux/slab.h> 50 #include <linux/watchdog.h> 51 52 /* registers */ 53 #define PDC_WDT_SOFT_RESET 0x00 54 #define PDC_WDT_CONFIG 0x04 55 #define PDC_WDT_CONFIG_ENABLE BIT(31) 56 #define PDC_WDT_CONFIG_DELAY_MASK 0x1f 57 58 #define PDC_WDT_TICKLE1 0x08 59 #define PDC_WDT_TICKLE1_MAGIC 0xabcd1234 60 #define PDC_WDT_TICKLE2 0x0c 61 #define PDC_WDT_TICKLE2_MAGIC 0x4321dcba 62 63 #define PDC_WDT_TICKLE_STATUS_MASK 0x7 64 #define PDC_WDT_TICKLE_STATUS_SHIFT 0 65 #define PDC_WDT_TICKLE_STATUS_HRESET 0x0 /* Hard reset */ 66 #define PDC_WDT_TICKLE_STATUS_TIMEOUT 0x1 /* Timeout */ 67 #define PDC_WDT_TICKLE_STATUS_TICKLE 0x2 /* Tickled incorrectly */ 68 #define PDC_WDT_TICKLE_STATUS_SRESET 0x3 /* Soft reset */ 69 #define PDC_WDT_TICKLE_STATUS_USER 0x4 /* User reset */ 70 71 /* Timeout values are in seconds */ 72 #define PDC_WDT_MIN_TIMEOUT 1 73 #define PDC_WDT_DEF_TIMEOUT 64 74 75 static int heartbeat; 76 module_param(heartbeat, int, 0); 77 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds " 78 "(default=" __MODULE_STRING(PDC_WDT_DEF_TIMEOUT) ")"); 79 80 static bool nowayout = WATCHDOG_NOWAYOUT; 81 module_param(nowayout, bool, 0); 82 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " 83 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 84 85 struct pdc_wdt_dev { 86 struct watchdog_device wdt_dev; 87 struct clk *wdt_clk; 88 struct clk *sys_clk; 89 void __iomem *base; 90 }; 91 92 static int pdc_wdt_keepalive(struct watchdog_device *wdt_dev) 93 { 94 struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev); 95 96 writel(PDC_WDT_TICKLE1_MAGIC, wdt->base + PDC_WDT_TICKLE1); 97 writel(PDC_WDT_TICKLE2_MAGIC, wdt->base + PDC_WDT_TICKLE2); 98 99 return 0; 100 } 101 102 static int pdc_wdt_stop(struct watchdog_device *wdt_dev) 103 { 104 unsigned int val; 105 struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev); 106 107 val = readl(wdt->base + PDC_WDT_CONFIG); 108 val &= ~PDC_WDT_CONFIG_ENABLE; 109 writel(val, wdt->base + PDC_WDT_CONFIG); 110 111 /* Must tickle to finish the stop */ 112 pdc_wdt_keepalive(wdt_dev); 113 114 return 0; 115 } 116 117 static void __pdc_wdt_set_timeout(struct pdc_wdt_dev *wdt) 118 { 119 unsigned long clk_rate = clk_get_rate(wdt->wdt_clk); 120 unsigned int val; 121 122 val = readl(wdt->base + PDC_WDT_CONFIG) & ~PDC_WDT_CONFIG_DELAY_MASK; 123 val |= order_base_2(wdt->wdt_dev.timeout * clk_rate) - 1; 124 writel(val, wdt->base + PDC_WDT_CONFIG); 125 } 126 127 static int pdc_wdt_set_timeout(struct watchdog_device *wdt_dev, 128 unsigned int new_timeout) 129 { 130 struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev); 131 132 wdt->wdt_dev.timeout = new_timeout; 133 134 __pdc_wdt_set_timeout(wdt); 135 136 return 0; 137 } 138 139 /* Start the watchdog timer (delay should already be set) */ 140 static int pdc_wdt_start(struct watchdog_device *wdt_dev) 141 { 142 unsigned int val; 143 struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev); 144 145 __pdc_wdt_set_timeout(wdt); 146 147 val = readl(wdt->base + PDC_WDT_CONFIG); 148 val |= PDC_WDT_CONFIG_ENABLE; 149 writel(val, wdt->base + PDC_WDT_CONFIG); 150 151 return 0; 152 } 153 154 static int pdc_wdt_restart(struct watchdog_device *wdt_dev, 155 unsigned long action, void *data) 156 { 157 struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev); 158 159 /* Assert SOFT_RESET */ 160 writel(0x1, wdt->base + PDC_WDT_SOFT_RESET); 161 162 return 0; 163 } 164 165 static const struct watchdog_info pdc_wdt_info = { 166 .identity = "IMG PDC Watchdog", 167 .options = WDIOF_SETTIMEOUT | 168 WDIOF_KEEPALIVEPING | 169 WDIOF_MAGICCLOSE, 170 }; 171 172 static const struct watchdog_ops pdc_wdt_ops = { 173 .owner = THIS_MODULE, 174 .start = pdc_wdt_start, 175 .stop = pdc_wdt_stop, 176 .ping = pdc_wdt_keepalive, 177 .set_timeout = pdc_wdt_set_timeout, 178 .restart = pdc_wdt_restart, 179 }; 180 181 static int pdc_wdt_probe(struct platform_device *pdev) 182 { 183 u64 div; 184 int ret, val; 185 unsigned long clk_rate; 186 struct resource *res; 187 struct pdc_wdt_dev *pdc_wdt; 188 189 pdc_wdt = devm_kzalloc(&pdev->dev, sizeof(*pdc_wdt), GFP_KERNEL); 190 if (!pdc_wdt) 191 return -ENOMEM; 192 193 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 194 pdc_wdt->base = devm_ioremap_resource(&pdev->dev, res); 195 if (IS_ERR(pdc_wdt->base)) 196 return PTR_ERR(pdc_wdt->base); 197 198 pdc_wdt->sys_clk = devm_clk_get(&pdev->dev, "sys"); 199 if (IS_ERR(pdc_wdt->sys_clk)) { 200 dev_err(&pdev->dev, "failed to get the sys clock\n"); 201 return PTR_ERR(pdc_wdt->sys_clk); 202 } 203 204 pdc_wdt->wdt_clk = devm_clk_get(&pdev->dev, "wdt"); 205 if (IS_ERR(pdc_wdt->wdt_clk)) { 206 dev_err(&pdev->dev, "failed to get the wdt clock\n"); 207 return PTR_ERR(pdc_wdt->wdt_clk); 208 } 209 210 ret = clk_prepare_enable(pdc_wdt->sys_clk); 211 if (ret) { 212 dev_err(&pdev->dev, "could not prepare or enable sys clock\n"); 213 return ret; 214 } 215 216 ret = clk_prepare_enable(pdc_wdt->wdt_clk); 217 if (ret) { 218 dev_err(&pdev->dev, "could not prepare or enable wdt clock\n"); 219 goto disable_sys_clk; 220 } 221 222 /* We use the clock rate to calculate the max timeout */ 223 clk_rate = clk_get_rate(pdc_wdt->wdt_clk); 224 if (clk_rate == 0) { 225 dev_err(&pdev->dev, "failed to get clock rate\n"); 226 ret = -EINVAL; 227 goto disable_wdt_clk; 228 } 229 230 if (order_base_2(clk_rate) > PDC_WDT_CONFIG_DELAY_MASK + 1) { 231 dev_err(&pdev->dev, "invalid clock rate\n"); 232 ret = -EINVAL; 233 goto disable_wdt_clk; 234 } 235 236 if (order_base_2(clk_rate) == 0) 237 pdc_wdt->wdt_dev.min_timeout = PDC_WDT_MIN_TIMEOUT + 1; 238 else 239 pdc_wdt->wdt_dev.min_timeout = PDC_WDT_MIN_TIMEOUT; 240 241 pdc_wdt->wdt_dev.info = &pdc_wdt_info; 242 pdc_wdt->wdt_dev.ops = &pdc_wdt_ops; 243 244 div = 1ULL << (PDC_WDT_CONFIG_DELAY_MASK + 1); 245 do_div(div, clk_rate); 246 pdc_wdt->wdt_dev.max_timeout = div; 247 pdc_wdt->wdt_dev.timeout = PDC_WDT_DEF_TIMEOUT; 248 pdc_wdt->wdt_dev.parent = &pdev->dev; 249 watchdog_set_drvdata(&pdc_wdt->wdt_dev, pdc_wdt); 250 251 watchdog_init_timeout(&pdc_wdt->wdt_dev, heartbeat, &pdev->dev); 252 253 pdc_wdt_stop(&pdc_wdt->wdt_dev); 254 255 /* Find what caused the last reset */ 256 val = readl(pdc_wdt->base + PDC_WDT_TICKLE1); 257 val = (val & PDC_WDT_TICKLE_STATUS_MASK) >> PDC_WDT_TICKLE_STATUS_SHIFT; 258 switch (val) { 259 case PDC_WDT_TICKLE_STATUS_TICKLE: 260 case PDC_WDT_TICKLE_STATUS_TIMEOUT: 261 pdc_wdt->wdt_dev.bootstatus |= WDIOF_CARDRESET; 262 dev_info(&pdev->dev, 263 "watchdog module last reset due to timeout\n"); 264 break; 265 case PDC_WDT_TICKLE_STATUS_HRESET: 266 dev_info(&pdev->dev, 267 "watchdog module last reset due to hard reset\n"); 268 break; 269 case PDC_WDT_TICKLE_STATUS_SRESET: 270 dev_info(&pdev->dev, 271 "watchdog module last reset due to soft reset\n"); 272 break; 273 case PDC_WDT_TICKLE_STATUS_USER: 274 dev_info(&pdev->dev, 275 "watchdog module last reset due to user reset\n"); 276 break; 277 default: 278 dev_info(&pdev->dev, 279 "contains an illegal status code (%08x)\n", val); 280 break; 281 } 282 283 watchdog_set_nowayout(&pdc_wdt->wdt_dev, nowayout); 284 watchdog_set_restart_priority(&pdc_wdt->wdt_dev, 128); 285 286 platform_set_drvdata(pdev, pdc_wdt); 287 288 ret = watchdog_register_device(&pdc_wdt->wdt_dev); 289 if (ret) 290 goto disable_wdt_clk; 291 292 return 0; 293 294 disable_wdt_clk: 295 clk_disable_unprepare(pdc_wdt->wdt_clk); 296 disable_sys_clk: 297 clk_disable_unprepare(pdc_wdt->sys_clk); 298 return ret; 299 } 300 301 static void pdc_wdt_shutdown(struct platform_device *pdev) 302 { 303 struct pdc_wdt_dev *pdc_wdt = platform_get_drvdata(pdev); 304 305 pdc_wdt_stop(&pdc_wdt->wdt_dev); 306 } 307 308 static int pdc_wdt_remove(struct platform_device *pdev) 309 { 310 struct pdc_wdt_dev *pdc_wdt = platform_get_drvdata(pdev); 311 312 pdc_wdt_stop(&pdc_wdt->wdt_dev); 313 watchdog_unregister_device(&pdc_wdt->wdt_dev); 314 clk_disable_unprepare(pdc_wdt->wdt_clk); 315 clk_disable_unprepare(pdc_wdt->sys_clk); 316 317 return 0; 318 } 319 320 static const struct of_device_id pdc_wdt_match[] = { 321 { .compatible = "img,pdc-wdt" }, 322 {} 323 }; 324 MODULE_DEVICE_TABLE(of, pdc_wdt_match); 325 326 static struct platform_driver pdc_wdt_driver = { 327 .driver = { 328 .name = "imgpdc-wdt", 329 .of_match_table = pdc_wdt_match, 330 }, 331 .probe = pdc_wdt_probe, 332 .remove = pdc_wdt_remove, 333 .shutdown = pdc_wdt_shutdown, 334 }; 335 module_platform_driver(pdc_wdt_driver); 336 337 MODULE_AUTHOR("Jude Abraham <Jude.Abraham@imgtec.com>"); 338 MODULE_AUTHOR("Naidu Tellapati <Naidu.Tellapati@imgtec.com>"); 339 MODULE_DESCRIPTION("Imagination Technologies PDC Watchdog Timer Driver"); 340 MODULE_LICENSE("GPL v2"); 341