1 /* 2 * intel TCO Watchdog Driver 3 * 4 * (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 * 11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor 12 * provide warranty for any of this software. This material is 13 * provided "AS-IS" and at no charge. 14 * 15 * The TCO watchdog is implemented in the following I/O controller hubs: 16 * (See the intel documentation on http://developer.intel.com.) 17 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO) 18 * document number 290687-002, 298242-027: 82801BA (ICH2) 19 * document number 290733-003, 290739-013: 82801CA (ICH3-S) 20 * document number 290716-001, 290718-007: 82801CAM (ICH3-M) 21 * document number 290744-001, 290745-025: 82801DB (ICH4) 22 * document number 252337-001, 252663-008: 82801DBM (ICH4-M) 23 * document number 273599-001, 273645-002: 82801E (C-ICH) 24 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R) 25 * document number 300641-004, 300884-013: 6300ESB 26 * document number 301473-002, 301474-026: 82801F (ICH6) 27 * document number 313082-001, 313075-006: 631xESB, 632xESB 28 * document number 307013-003, 307014-024: 82801G (ICH7) 29 * document number 322896-001, 322897-001: NM10 30 * document number 313056-003, 313057-017: 82801H (ICH8) 31 * document number 316972-004, 316973-012: 82801I (ICH9) 32 * document number 319973-002, 319974-002: 82801J (ICH10) 33 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH) 34 * document number 320066-003, 320257-008: EP80597 (IICH) 35 * document number 324645-001, 324646-001: Cougar Point (CPT) 36 * document number TBD : Patsburg (PBG) 37 * document number TBD : DH89xxCC 38 * document number TBD : Panther Point 39 * document number TBD : Lynx Point 40 * document number TBD : Lynx Point-LP 41 */ 42 43 /* 44 * Includes, defines, variables, module parameters, ... 45 */ 46 47 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 48 49 /* Module and version information */ 50 #define DRV_NAME "iTCO_wdt" 51 #define DRV_VERSION "1.11" 52 53 /* Includes */ 54 #include <linux/acpi.h> /* For ACPI support */ 55 #include <linux/module.h> /* For module specific items */ 56 #include <linux/moduleparam.h> /* For new moduleparam's */ 57 #include <linux/types.h> /* For standard types (like size_t) */ 58 #include <linux/errno.h> /* For the -ENODEV/... values */ 59 #include <linux/kernel.h> /* For printk/panic/... */ 60 #include <linux/watchdog.h> /* For the watchdog specific items */ 61 #include <linux/init.h> /* For __init/__exit/... */ 62 #include <linux/fs.h> /* For file operations */ 63 #include <linux/platform_device.h> /* For platform_driver framework */ 64 #include <linux/pci.h> /* For pci functions */ 65 #include <linux/ioport.h> /* For io-port access */ 66 #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */ 67 #include <linux/uaccess.h> /* For copy_to_user/put_user/... */ 68 #include <linux/io.h> /* For inb/outb/... */ 69 #include <linux/platform_data/itco_wdt.h> 70 71 #include "iTCO_vendor.h" 72 73 /* Address definitions for the TCO */ 74 /* TCO base address */ 75 #define TCOBASE (iTCO_wdt_private.tco_res->start) 76 /* SMI Control and Enable Register */ 77 #define SMI_EN (iTCO_wdt_private.smi_res->start) 78 79 #define TCO_RLD (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */ 80 #define TCOv1_TMR (TCOBASE + 0x01) /* TCOv1 Timer Initial Value */ 81 #define TCO_DAT_IN (TCOBASE + 0x02) /* TCO Data In Register */ 82 #define TCO_DAT_OUT (TCOBASE + 0x03) /* TCO Data Out Register */ 83 #define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */ 84 #define TCO2_STS (TCOBASE + 0x06) /* TCO2 Status Register */ 85 #define TCO1_CNT (TCOBASE + 0x08) /* TCO1 Control Register */ 86 #define TCO2_CNT (TCOBASE + 0x0a) /* TCO2 Control Register */ 87 #define TCOv2_TMR (TCOBASE + 0x12) /* TCOv2 Timer Initial Value */ 88 89 /* internal variables */ 90 static struct { /* this is private data for the iTCO_wdt device */ 91 /* TCO version/generation */ 92 unsigned int iTCO_version; 93 struct resource *tco_res; 94 struct resource *smi_res; 95 /* 96 * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2), 97 * or memory-mapped PMC register bit 4 (TCO version 3). 98 */ 99 struct resource *gcs_pmc_res; 100 unsigned long __iomem *gcs_pmc; 101 /* the lock for io operations */ 102 spinlock_t io_lock; 103 struct platform_device *dev; 104 /* the PCI-device */ 105 struct pci_dev *pdev; 106 /* whether or not the watchdog has been suspended */ 107 bool suspended; 108 } iTCO_wdt_private; 109 110 /* module parameters */ 111 #define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */ 112 static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */ 113 module_param(heartbeat, int, 0); 114 MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. " 115 "5..76 (TCO v1) or 3..614 (TCO v2), default=" 116 __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); 117 118 static bool nowayout = WATCHDOG_NOWAYOUT; 119 module_param(nowayout, bool, 0); 120 MODULE_PARM_DESC(nowayout, 121 "Watchdog cannot be stopped once started (default=" 122 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 123 124 static int turn_SMI_watchdog_clear_off = 1; 125 module_param(turn_SMI_watchdog_clear_off, int, 0); 126 MODULE_PARM_DESC(turn_SMI_watchdog_clear_off, 127 "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)"); 128 129 /* 130 * Some TCO specific functions 131 */ 132 133 /* 134 * The iTCO v1 and v2's internal timer is stored as ticks which decrement 135 * every 0.6 seconds. v3's internal timer is stored as seconds (some 136 * datasheets incorrectly state 0.6 seconds). 137 */ 138 static inline unsigned int seconds_to_ticks(int secs) 139 { 140 return iTCO_wdt_private.iTCO_version == 3 ? secs : (secs * 10) / 6; 141 } 142 143 static inline unsigned int ticks_to_seconds(int ticks) 144 { 145 return iTCO_wdt_private.iTCO_version == 3 ? ticks : (ticks * 6) / 10; 146 } 147 148 static inline u32 no_reboot_bit(void) 149 { 150 u32 enable_bit; 151 152 switch (iTCO_wdt_private.iTCO_version) { 153 case 5: 154 case 3: 155 enable_bit = 0x00000010; 156 break; 157 case 2: 158 enable_bit = 0x00000020; 159 break; 160 case 4: 161 case 1: 162 default: 163 enable_bit = 0x00000002; 164 break; 165 } 166 167 return enable_bit; 168 } 169 170 static void iTCO_wdt_set_NO_REBOOT_bit(void) 171 { 172 u32 val32; 173 174 /* Set the NO_REBOOT bit: this disables reboots */ 175 if (iTCO_wdt_private.iTCO_version >= 2) { 176 val32 = readl(iTCO_wdt_private.gcs_pmc); 177 val32 |= no_reboot_bit(); 178 writel(val32, iTCO_wdt_private.gcs_pmc); 179 } else if (iTCO_wdt_private.iTCO_version == 1) { 180 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32); 181 val32 |= no_reboot_bit(); 182 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32); 183 } 184 } 185 186 static int iTCO_wdt_unset_NO_REBOOT_bit(void) 187 { 188 u32 enable_bit = no_reboot_bit(); 189 u32 val32 = 0; 190 191 /* Unset the NO_REBOOT bit: this enables reboots */ 192 if (iTCO_wdt_private.iTCO_version >= 2) { 193 val32 = readl(iTCO_wdt_private.gcs_pmc); 194 val32 &= ~enable_bit; 195 writel(val32, iTCO_wdt_private.gcs_pmc); 196 197 val32 = readl(iTCO_wdt_private.gcs_pmc); 198 } else if (iTCO_wdt_private.iTCO_version == 1) { 199 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32); 200 val32 &= ~enable_bit; 201 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32); 202 203 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32); 204 } 205 206 if (val32 & enable_bit) 207 return -EIO; 208 209 return 0; 210 } 211 212 static int iTCO_wdt_start(struct watchdog_device *wd_dev) 213 { 214 unsigned int val; 215 216 spin_lock(&iTCO_wdt_private.io_lock); 217 218 iTCO_vendor_pre_start(iTCO_wdt_private.smi_res, wd_dev->timeout); 219 220 /* disable chipset's NO_REBOOT bit */ 221 if (iTCO_wdt_unset_NO_REBOOT_bit()) { 222 spin_unlock(&iTCO_wdt_private.io_lock); 223 pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n"); 224 return -EIO; 225 } 226 227 /* Force the timer to its reload value by writing to the TCO_RLD 228 register */ 229 if (iTCO_wdt_private.iTCO_version >= 2) 230 outw(0x01, TCO_RLD); 231 else if (iTCO_wdt_private.iTCO_version == 1) 232 outb(0x01, TCO_RLD); 233 234 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */ 235 val = inw(TCO1_CNT); 236 val &= 0xf7ff; 237 outw(val, TCO1_CNT); 238 val = inw(TCO1_CNT); 239 spin_unlock(&iTCO_wdt_private.io_lock); 240 241 if (val & 0x0800) 242 return -1; 243 return 0; 244 } 245 246 static int iTCO_wdt_stop(struct watchdog_device *wd_dev) 247 { 248 unsigned int val; 249 250 spin_lock(&iTCO_wdt_private.io_lock); 251 252 iTCO_vendor_pre_stop(iTCO_wdt_private.smi_res); 253 254 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */ 255 val = inw(TCO1_CNT); 256 val |= 0x0800; 257 outw(val, TCO1_CNT); 258 val = inw(TCO1_CNT); 259 260 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ 261 iTCO_wdt_set_NO_REBOOT_bit(); 262 263 spin_unlock(&iTCO_wdt_private.io_lock); 264 265 if ((val & 0x0800) == 0) 266 return -1; 267 return 0; 268 } 269 270 static int iTCO_wdt_ping(struct watchdog_device *wd_dev) 271 { 272 spin_lock(&iTCO_wdt_private.io_lock); 273 274 iTCO_vendor_pre_keepalive(iTCO_wdt_private.smi_res, wd_dev->timeout); 275 276 /* Reload the timer by writing to the TCO Timer Counter register */ 277 if (iTCO_wdt_private.iTCO_version >= 2) { 278 outw(0x01, TCO_RLD); 279 } else if (iTCO_wdt_private.iTCO_version == 1) { 280 /* Reset the timeout status bit so that the timer 281 * needs to count down twice again before rebooting */ 282 outw(0x0008, TCO1_STS); /* write 1 to clear bit */ 283 284 outb(0x01, TCO_RLD); 285 } 286 287 spin_unlock(&iTCO_wdt_private.io_lock); 288 return 0; 289 } 290 291 static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t) 292 { 293 unsigned int val16; 294 unsigned char val8; 295 unsigned int tmrval; 296 297 tmrval = seconds_to_ticks(t); 298 299 /* For TCO v1 the timer counts down twice before rebooting */ 300 if (iTCO_wdt_private.iTCO_version == 1) 301 tmrval /= 2; 302 303 /* from the specs: */ 304 /* "Values of 0h-3h are ignored and should not be attempted" */ 305 if (tmrval < 0x04) 306 return -EINVAL; 307 if (((iTCO_wdt_private.iTCO_version >= 2) && (tmrval > 0x3ff)) || 308 ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f))) 309 return -EINVAL; 310 311 iTCO_vendor_pre_set_heartbeat(tmrval); 312 313 /* Write new heartbeat to watchdog */ 314 if (iTCO_wdt_private.iTCO_version >= 2) { 315 spin_lock(&iTCO_wdt_private.io_lock); 316 val16 = inw(TCOv2_TMR); 317 val16 &= 0xfc00; 318 val16 |= tmrval; 319 outw(val16, TCOv2_TMR); 320 val16 = inw(TCOv2_TMR); 321 spin_unlock(&iTCO_wdt_private.io_lock); 322 323 if ((val16 & 0x3ff) != tmrval) 324 return -EINVAL; 325 } else if (iTCO_wdt_private.iTCO_version == 1) { 326 spin_lock(&iTCO_wdt_private.io_lock); 327 val8 = inb(TCOv1_TMR); 328 val8 &= 0xc0; 329 val8 |= (tmrval & 0xff); 330 outb(val8, TCOv1_TMR); 331 val8 = inb(TCOv1_TMR); 332 spin_unlock(&iTCO_wdt_private.io_lock); 333 334 if ((val8 & 0x3f) != tmrval) 335 return -EINVAL; 336 } 337 338 wd_dev->timeout = t; 339 return 0; 340 } 341 342 static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev) 343 { 344 unsigned int val16; 345 unsigned char val8; 346 unsigned int time_left = 0; 347 348 /* read the TCO Timer */ 349 if (iTCO_wdt_private.iTCO_version >= 2) { 350 spin_lock(&iTCO_wdt_private.io_lock); 351 val16 = inw(TCO_RLD); 352 val16 &= 0x3ff; 353 spin_unlock(&iTCO_wdt_private.io_lock); 354 355 time_left = ticks_to_seconds(val16); 356 } else if (iTCO_wdt_private.iTCO_version == 1) { 357 spin_lock(&iTCO_wdt_private.io_lock); 358 val8 = inb(TCO_RLD); 359 val8 &= 0x3f; 360 if (!(inw(TCO1_STS) & 0x0008)) 361 val8 += (inb(TCOv1_TMR) & 0x3f); 362 spin_unlock(&iTCO_wdt_private.io_lock); 363 364 time_left = ticks_to_seconds(val8); 365 } 366 return time_left; 367 } 368 369 /* 370 * Kernel Interfaces 371 */ 372 373 static const struct watchdog_info ident = { 374 .options = WDIOF_SETTIMEOUT | 375 WDIOF_KEEPALIVEPING | 376 WDIOF_MAGICCLOSE, 377 .firmware_version = 0, 378 .identity = DRV_NAME, 379 }; 380 381 static const struct watchdog_ops iTCO_wdt_ops = { 382 .owner = THIS_MODULE, 383 .start = iTCO_wdt_start, 384 .stop = iTCO_wdt_stop, 385 .ping = iTCO_wdt_ping, 386 .set_timeout = iTCO_wdt_set_timeout, 387 .get_timeleft = iTCO_wdt_get_timeleft, 388 }; 389 390 static struct watchdog_device iTCO_wdt_watchdog_dev = { 391 .info = &ident, 392 .ops = &iTCO_wdt_ops, 393 }; 394 395 /* 396 * Init & exit routines 397 */ 398 399 static void iTCO_wdt_cleanup(void) 400 { 401 /* Stop the timer before we leave */ 402 if (!nowayout) 403 iTCO_wdt_stop(&iTCO_wdt_watchdog_dev); 404 405 /* Deregister */ 406 watchdog_unregister_device(&iTCO_wdt_watchdog_dev); 407 408 /* release resources */ 409 release_region(iTCO_wdt_private.tco_res->start, 410 resource_size(iTCO_wdt_private.tco_res)); 411 release_region(iTCO_wdt_private.smi_res->start, 412 resource_size(iTCO_wdt_private.smi_res)); 413 if (iTCO_wdt_private.iTCO_version >= 2) { 414 iounmap(iTCO_wdt_private.gcs_pmc); 415 release_mem_region(iTCO_wdt_private.gcs_pmc_res->start, 416 resource_size(iTCO_wdt_private.gcs_pmc_res)); 417 } 418 419 iTCO_wdt_private.tco_res = NULL; 420 iTCO_wdt_private.smi_res = NULL; 421 iTCO_wdt_private.gcs_pmc_res = NULL; 422 iTCO_wdt_private.gcs_pmc = NULL; 423 } 424 425 static int iTCO_wdt_probe(struct platform_device *dev) 426 { 427 int ret = -ENODEV; 428 unsigned long val32; 429 struct itco_wdt_platform_data *pdata = dev_get_platdata(&dev->dev); 430 431 if (!pdata) 432 goto out; 433 434 spin_lock_init(&iTCO_wdt_private.io_lock); 435 436 iTCO_wdt_private.tco_res = 437 platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_TCO); 438 if (!iTCO_wdt_private.tco_res) 439 goto out; 440 441 iTCO_wdt_private.smi_res = 442 platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_SMI); 443 if (!iTCO_wdt_private.smi_res) 444 goto out; 445 446 iTCO_wdt_private.iTCO_version = pdata->version; 447 iTCO_wdt_private.dev = dev; 448 iTCO_wdt_private.pdev = to_pci_dev(dev->dev.parent); 449 450 /* 451 * Get the Memory-Mapped GCS or PMC register, we need it for the 452 * NO_REBOOT flag (TCO v2 and v3). 453 */ 454 if (iTCO_wdt_private.iTCO_version >= 2) { 455 iTCO_wdt_private.gcs_pmc_res = platform_get_resource(dev, 456 IORESOURCE_MEM, 457 ICH_RES_MEM_GCS_PMC); 458 459 if (!iTCO_wdt_private.gcs_pmc_res) 460 goto out; 461 462 if (!request_mem_region(iTCO_wdt_private.gcs_pmc_res->start, 463 resource_size(iTCO_wdt_private.gcs_pmc_res), dev->name)) { 464 ret = -EBUSY; 465 goto out; 466 } 467 iTCO_wdt_private.gcs_pmc = ioremap(iTCO_wdt_private.gcs_pmc_res->start, 468 resource_size(iTCO_wdt_private.gcs_pmc_res)); 469 if (!iTCO_wdt_private.gcs_pmc) { 470 ret = -EIO; 471 goto unreg_gcs_pmc; 472 } 473 } 474 475 /* Check chipset's NO_REBOOT bit */ 476 if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) { 477 pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n"); 478 ret = -ENODEV; /* Cannot reset NO_REBOOT bit */ 479 goto unmap_gcs_pmc; 480 } 481 482 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ 483 iTCO_wdt_set_NO_REBOOT_bit(); 484 485 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */ 486 if (!request_region(iTCO_wdt_private.smi_res->start, 487 resource_size(iTCO_wdt_private.smi_res), dev->name)) { 488 pr_err("I/O address 0x%04llx already in use, device disabled\n", 489 (u64)SMI_EN); 490 ret = -EBUSY; 491 goto unmap_gcs_pmc; 492 } 493 if (turn_SMI_watchdog_clear_off >= iTCO_wdt_private.iTCO_version) { 494 /* 495 * Bit 13: TCO_EN -> 0 496 * Disables TCO logic generating an SMI# 497 */ 498 val32 = inl(SMI_EN); 499 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ 500 outl(val32, SMI_EN); 501 } 502 503 if (!request_region(iTCO_wdt_private.tco_res->start, 504 resource_size(iTCO_wdt_private.tco_res), dev->name)) { 505 pr_err("I/O address 0x%04llx already in use, device disabled\n", 506 (u64)TCOBASE); 507 ret = -EBUSY; 508 goto unreg_smi; 509 } 510 511 pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n", 512 pdata->name, pdata->version, (u64)TCOBASE); 513 514 /* Clear out the (probably old) status */ 515 switch (iTCO_wdt_private.iTCO_version) { 516 case 5: 517 case 4: 518 outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */ 519 outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */ 520 break; 521 case 3: 522 outl(0x20008, TCO1_STS); 523 break; 524 case 2: 525 case 1: 526 default: 527 outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */ 528 outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */ 529 outw(0x0004, TCO2_STS); /* Clear BOOT_STS bit */ 530 break; 531 } 532 533 iTCO_wdt_watchdog_dev.bootstatus = 0; 534 iTCO_wdt_watchdog_dev.timeout = WATCHDOG_TIMEOUT; 535 watchdog_set_nowayout(&iTCO_wdt_watchdog_dev, nowayout); 536 iTCO_wdt_watchdog_dev.parent = &dev->dev; 537 538 /* Make sure the watchdog is not running */ 539 iTCO_wdt_stop(&iTCO_wdt_watchdog_dev); 540 541 /* Check that the heartbeat value is within it's range; 542 if not reset to the default */ 543 if (iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, heartbeat)) { 544 iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, WATCHDOG_TIMEOUT); 545 pr_info("timeout value out of range, using %d\n", 546 WATCHDOG_TIMEOUT); 547 } 548 549 ret = watchdog_register_device(&iTCO_wdt_watchdog_dev); 550 if (ret != 0) { 551 pr_err("cannot register watchdog device (err=%d)\n", ret); 552 goto unreg_tco; 553 } 554 555 pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n", 556 heartbeat, nowayout); 557 558 return 0; 559 560 unreg_tco: 561 release_region(iTCO_wdt_private.tco_res->start, 562 resource_size(iTCO_wdt_private.tco_res)); 563 unreg_smi: 564 release_region(iTCO_wdt_private.smi_res->start, 565 resource_size(iTCO_wdt_private.smi_res)); 566 unmap_gcs_pmc: 567 if (iTCO_wdt_private.iTCO_version >= 2) 568 iounmap(iTCO_wdt_private.gcs_pmc); 569 unreg_gcs_pmc: 570 if (iTCO_wdt_private.iTCO_version >= 2) 571 release_mem_region(iTCO_wdt_private.gcs_pmc_res->start, 572 resource_size(iTCO_wdt_private.gcs_pmc_res)); 573 out: 574 iTCO_wdt_private.tco_res = NULL; 575 iTCO_wdt_private.smi_res = NULL; 576 iTCO_wdt_private.gcs_pmc_res = NULL; 577 iTCO_wdt_private.gcs_pmc = NULL; 578 579 return ret; 580 } 581 582 static int iTCO_wdt_remove(struct platform_device *dev) 583 { 584 if (iTCO_wdt_private.tco_res || iTCO_wdt_private.smi_res) 585 iTCO_wdt_cleanup(); 586 587 return 0; 588 } 589 590 static void iTCO_wdt_shutdown(struct platform_device *dev) 591 { 592 iTCO_wdt_stop(NULL); 593 } 594 595 #ifdef CONFIG_PM_SLEEP 596 /* 597 * Suspend-to-idle requires this, because it stops the ticks and timekeeping, so 598 * the watchdog cannot be pinged while in that state. In ACPI sleep states the 599 * watchdog is stopped by the platform firmware. 600 */ 601 602 #ifdef CONFIG_ACPI 603 static inline bool need_suspend(void) 604 { 605 return acpi_target_system_state() == ACPI_STATE_S0; 606 } 607 #else 608 static inline bool need_suspend(void) { return true; } 609 #endif 610 611 static int iTCO_wdt_suspend_noirq(struct device *dev) 612 { 613 int ret = 0; 614 615 iTCO_wdt_private.suspended = false; 616 if (watchdog_active(&iTCO_wdt_watchdog_dev) && need_suspend()) { 617 ret = iTCO_wdt_stop(&iTCO_wdt_watchdog_dev); 618 if (!ret) 619 iTCO_wdt_private.suspended = true; 620 } 621 return ret; 622 } 623 624 static int iTCO_wdt_resume_noirq(struct device *dev) 625 { 626 if (iTCO_wdt_private.suspended) 627 iTCO_wdt_start(&iTCO_wdt_watchdog_dev); 628 629 return 0; 630 } 631 632 static struct dev_pm_ops iTCO_wdt_pm = { 633 .suspend_noirq = iTCO_wdt_suspend_noirq, 634 .resume_noirq = iTCO_wdt_resume_noirq, 635 }; 636 637 #define ITCO_WDT_PM_OPS (&iTCO_wdt_pm) 638 #else 639 #define ITCO_WDT_PM_OPS NULL 640 #endif /* CONFIG_PM_SLEEP */ 641 642 static struct platform_driver iTCO_wdt_driver = { 643 .probe = iTCO_wdt_probe, 644 .remove = iTCO_wdt_remove, 645 .shutdown = iTCO_wdt_shutdown, 646 .driver = { 647 .name = DRV_NAME, 648 .pm = ITCO_WDT_PM_OPS, 649 }, 650 }; 651 652 static int __init iTCO_wdt_init_module(void) 653 { 654 int err; 655 656 pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION); 657 658 err = platform_driver_register(&iTCO_wdt_driver); 659 if (err) 660 return err; 661 662 return 0; 663 } 664 665 static void __exit iTCO_wdt_cleanup_module(void) 666 { 667 platform_driver_unregister(&iTCO_wdt_driver); 668 pr_info("Watchdog Module Unloaded\n"); 669 } 670 671 module_init(iTCO_wdt_init_module); 672 module_exit(iTCO_wdt_cleanup_module); 673 674 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>"); 675 MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver"); 676 MODULE_VERSION(DRV_VERSION); 677 MODULE_LICENSE("GPL"); 678 MODULE_ALIAS("platform:" DRV_NAME); 679