xref: /openbmc/linux/drivers/watchdog/iTCO_wdt.c (revision b593bce5)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *	intel TCO Watchdog Driver
4  *
5  *	(c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
6  *
7  *	Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
8  *	provide warranty for any of this software. This material is
9  *	provided "AS-IS" and at no charge.
10  *
11  *	The TCO watchdog is implemented in the following I/O controller hubs:
12  *	(See the intel documentation on http://developer.intel.com.)
13  *	document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
14  *	document number 290687-002, 298242-027: 82801BA (ICH2)
15  *	document number 290733-003, 290739-013: 82801CA (ICH3-S)
16  *	document number 290716-001, 290718-007: 82801CAM (ICH3-M)
17  *	document number 290744-001, 290745-025: 82801DB (ICH4)
18  *	document number 252337-001, 252663-008: 82801DBM (ICH4-M)
19  *	document number 273599-001, 273645-002: 82801E (C-ICH)
20  *	document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
21  *	document number 300641-004, 300884-013: 6300ESB
22  *	document number 301473-002, 301474-026: 82801F (ICH6)
23  *	document number 313082-001, 313075-006: 631xESB, 632xESB
24  *	document number 307013-003, 307014-024: 82801G (ICH7)
25  *	document number 322896-001, 322897-001: NM10
26  *	document number 313056-003, 313057-017: 82801H (ICH8)
27  *	document number 316972-004, 316973-012: 82801I (ICH9)
28  *	document number 319973-002, 319974-002: 82801J (ICH10)
29  *	document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
30  *	document number 320066-003, 320257-008: EP80597 (IICH)
31  *	document number 324645-001, 324646-001: Cougar Point (CPT)
32  *	document number TBD                   : Patsburg (PBG)
33  *	document number TBD                   : DH89xxCC
34  *	document number TBD                   : Panther Point
35  *	document number TBD                   : Lynx Point
36  *	document number TBD                   : Lynx Point-LP
37  */
38 
39 /*
40  *	Includes, defines, variables, module parameters, ...
41  */
42 
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 
45 /* Module and version information */
46 #define DRV_NAME	"iTCO_wdt"
47 #define DRV_VERSION	"1.11"
48 
49 /* Includes */
50 #include <linux/acpi.h>			/* For ACPI support */
51 #include <linux/module.h>		/* For module specific items */
52 #include <linux/moduleparam.h>		/* For new moduleparam's */
53 #include <linux/types.h>		/* For standard types (like size_t) */
54 #include <linux/errno.h>		/* For the -ENODEV/... values */
55 #include <linux/kernel.h>		/* For printk/panic/... */
56 #include <linux/watchdog.h>		/* For the watchdog specific items */
57 #include <linux/init.h>			/* For __init/__exit/... */
58 #include <linux/fs.h>			/* For file operations */
59 #include <linux/platform_device.h>	/* For platform_driver framework */
60 #include <linux/pci.h>			/* For pci functions */
61 #include <linux/ioport.h>		/* For io-port access */
62 #include <linux/spinlock.h>		/* For spin_lock/spin_unlock/... */
63 #include <linux/uaccess.h>		/* For copy_to_user/put_user/... */
64 #include <linux/io.h>			/* For inb/outb/... */
65 #include <linux/platform_data/itco_wdt.h>
66 
67 #include "iTCO_vendor.h"
68 
69 /* Address definitions for the TCO */
70 /* TCO base address */
71 #define TCOBASE(p)	((p)->tco_res->start)
72 /* SMI Control and Enable Register */
73 #define SMI_EN(p)	((p)->smi_res->start)
74 
75 #define TCO_RLD(p)	(TCOBASE(p) + 0x00) /* TCO Timer Reload/Curr. Value */
76 #define TCOv1_TMR(p)	(TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/
77 #define TCO_DAT_IN(p)	(TCOBASE(p) + 0x02) /* TCO Data In Register	*/
78 #define TCO_DAT_OUT(p)	(TCOBASE(p) + 0x03) /* TCO Data Out Register	*/
79 #define TCO1_STS(p)	(TCOBASE(p) + 0x04) /* TCO1 Status Register	*/
80 #define TCO2_STS(p)	(TCOBASE(p) + 0x06) /* TCO2 Status Register	*/
81 #define TCO1_CNT(p)	(TCOBASE(p) + 0x08) /* TCO1 Control Register	*/
82 #define TCO2_CNT(p)	(TCOBASE(p) + 0x0a) /* TCO2 Control Register	*/
83 #define TCOv2_TMR(p)	(TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
84 
85 /* internal variables */
86 struct iTCO_wdt_private {
87 	struct watchdog_device wddev;
88 
89 	/* TCO version/generation */
90 	unsigned int iTCO_version;
91 	struct resource *tco_res;
92 	struct resource *smi_res;
93 	/*
94 	 * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2),
95 	 * or memory-mapped PMC register bit 4 (TCO version 3).
96 	 */
97 	struct resource *gcs_pmc_res;
98 	unsigned long __iomem *gcs_pmc;
99 	/* the lock for io operations */
100 	spinlock_t io_lock;
101 	/* the PCI-device */
102 	struct pci_dev *pci_dev;
103 	/* whether or not the watchdog has been suspended */
104 	bool suspended;
105 	/* no reboot API private data */
106 	void *no_reboot_priv;
107 	/* no reboot update function pointer */
108 	int (*update_no_reboot_bit)(void *p, bool set);
109 };
110 
111 /* module parameters */
112 #define WATCHDOG_TIMEOUT 30	/* 30 sec default heartbeat */
113 static int heartbeat = WATCHDOG_TIMEOUT;  /* in seconds */
114 module_param(heartbeat, int, 0);
115 MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
116 	"5..76 (TCO v1) or 3..614 (TCO v2), default="
117 				__MODULE_STRING(WATCHDOG_TIMEOUT) ")");
118 
119 static bool nowayout = WATCHDOG_NOWAYOUT;
120 module_param(nowayout, bool, 0);
121 MODULE_PARM_DESC(nowayout,
122 	"Watchdog cannot be stopped once started (default="
123 				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
124 
125 static int turn_SMI_watchdog_clear_off = 1;
126 module_param(turn_SMI_watchdog_clear_off, int, 0);
127 MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
128 	"Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
129 
130 /*
131  * Some TCO specific functions
132  */
133 
134 /*
135  * The iTCO v1 and v2's internal timer is stored as ticks which decrement
136  * every 0.6 seconds.  v3's internal timer is stored as seconds (some
137  * datasheets incorrectly state 0.6 seconds).
138  */
139 static inline unsigned int seconds_to_ticks(struct iTCO_wdt_private *p,
140 					    int secs)
141 {
142 	return p->iTCO_version == 3 ? secs : (secs * 10) / 6;
143 }
144 
145 static inline unsigned int ticks_to_seconds(struct iTCO_wdt_private *p,
146 					    int ticks)
147 {
148 	return p->iTCO_version == 3 ? ticks : (ticks * 6) / 10;
149 }
150 
151 static inline u32 no_reboot_bit(struct iTCO_wdt_private *p)
152 {
153 	u32 enable_bit;
154 
155 	switch (p->iTCO_version) {
156 	case 5:
157 	case 3:
158 		enable_bit = 0x00000010;
159 		break;
160 	case 2:
161 		enable_bit = 0x00000020;
162 		break;
163 	case 4:
164 	case 1:
165 	default:
166 		enable_bit = 0x00000002;
167 		break;
168 	}
169 
170 	return enable_bit;
171 }
172 
173 static int update_no_reboot_bit_def(void *priv, bool set)
174 {
175 	return 0;
176 }
177 
178 static int update_no_reboot_bit_pci(void *priv, bool set)
179 {
180 	struct iTCO_wdt_private *p = priv;
181 	u32 val32 = 0, newval32 = 0;
182 
183 	pci_read_config_dword(p->pci_dev, 0xd4, &val32);
184 	if (set)
185 		val32 |= no_reboot_bit(p);
186 	else
187 		val32 &= ~no_reboot_bit(p);
188 	pci_write_config_dword(p->pci_dev, 0xd4, val32);
189 	pci_read_config_dword(p->pci_dev, 0xd4, &newval32);
190 
191 	/* make sure the update is successful */
192 	if (val32 != newval32)
193 		return -EIO;
194 
195 	return 0;
196 }
197 
198 static int update_no_reboot_bit_mem(void *priv, bool set)
199 {
200 	struct iTCO_wdt_private *p = priv;
201 	u32 val32 = 0, newval32 = 0;
202 
203 	val32 = readl(p->gcs_pmc);
204 	if (set)
205 		val32 |= no_reboot_bit(p);
206 	else
207 		val32 &= ~no_reboot_bit(p);
208 	writel(val32, p->gcs_pmc);
209 	newval32 = readl(p->gcs_pmc);
210 
211 	/* make sure the update is successful */
212 	if (val32 != newval32)
213 		return -EIO;
214 
215 	return 0;
216 }
217 
218 static void iTCO_wdt_no_reboot_bit_setup(struct iTCO_wdt_private *p,
219 		struct itco_wdt_platform_data *pdata)
220 {
221 	if (pdata->update_no_reboot_bit) {
222 		p->update_no_reboot_bit = pdata->update_no_reboot_bit;
223 		p->no_reboot_priv = pdata->no_reboot_priv;
224 		return;
225 	}
226 
227 	if (p->iTCO_version >= 2)
228 		p->update_no_reboot_bit = update_no_reboot_bit_mem;
229 	else if (p->iTCO_version == 1)
230 		p->update_no_reboot_bit = update_no_reboot_bit_pci;
231 	else
232 		p->update_no_reboot_bit = update_no_reboot_bit_def;
233 
234 	p->no_reboot_priv = p;
235 }
236 
237 static int iTCO_wdt_start(struct watchdog_device *wd_dev)
238 {
239 	struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
240 	unsigned int val;
241 
242 	spin_lock(&p->io_lock);
243 
244 	iTCO_vendor_pre_start(p->smi_res, wd_dev->timeout);
245 
246 	/* disable chipset's NO_REBOOT bit */
247 	if (p->update_no_reboot_bit(p->no_reboot_priv, false)) {
248 		spin_unlock(&p->io_lock);
249 		pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
250 		return -EIO;
251 	}
252 
253 	/* Force the timer to its reload value by writing to the TCO_RLD
254 	   register */
255 	if (p->iTCO_version >= 2)
256 		outw(0x01, TCO_RLD(p));
257 	else if (p->iTCO_version == 1)
258 		outb(0x01, TCO_RLD(p));
259 
260 	/* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
261 	val = inw(TCO1_CNT(p));
262 	val &= 0xf7ff;
263 	outw(val, TCO1_CNT(p));
264 	val = inw(TCO1_CNT(p));
265 	spin_unlock(&p->io_lock);
266 
267 	if (val & 0x0800)
268 		return -1;
269 	return 0;
270 }
271 
272 static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
273 {
274 	struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
275 	unsigned int val;
276 
277 	spin_lock(&p->io_lock);
278 
279 	iTCO_vendor_pre_stop(p->smi_res);
280 
281 	/* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
282 	val = inw(TCO1_CNT(p));
283 	val |= 0x0800;
284 	outw(val, TCO1_CNT(p));
285 	val = inw(TCO1_CNT(p));
286 
287 	/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
288 	p->update_no_reboot_bit(p->no_reboot_priv, true);
289 
290 	spin_unlock(&p->io_lock);
291 
292 	if ((val & 0x0800) == 0)
293 		return -1;
294 	return 0;
295 }
296 
297 static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
298 {
299 	struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
300 
301 	spin_lock(&p->io_lock);
302 
303 	/* Reload the timer by writing to the TCO Timer Counter register */
304 	if (p->iTCO_version >= 2) {
305 		outw(0x01, TCO_RLD(p));
306 	} else if (p->iTCO_version == 1) {
307 		/* Reset the timeout status bit so that the timer
308 		 * needs to count down twice again before rebooting */
309 		outw(0x0008, TCO1_STS(p));	/* write 1 to clear bit */
310 
311 		outb(0x01, TCO_RLD(p));
312 	}
313 
314 	spin_unlock(&p->io_lock);
315 	return 0;
316 }
317 
318 static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
319 {
320 	struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
321 	unsigned int val16;
322 	unsigned char val8;
323 	unsigned int tmrval;
324 
325 	tmrval = seconds_to_ticks(p, t);
326 
327 	/* For TCO v1 the timer counts down twice before rebooting */
328 	if (p->iTCO_version == 1)
329 		tmrval /= 2;
330 
331 	/* from the specs: */
332 	/* "Values of 0h-3h are ignored and should not be attempted" */
333 	if (tmrval < 0x04)
334 		return -EINVAL;
335 	if ((p->iTCO_version >= 2 && tmrval > 0x3ff) ||
336 	    (p->iTCO_version == 1 && tmrval > 0x03f))
337 		return -EINVAL;
338 
339 	/* Write new heartbeat to watchdog */
340 	if (p->iTCO_version >= 2) {
341 		spin_lock(&p->io_lock);
342 		val16 = inw(TCOv2_TMR(p));
343 		val16 &= 0xfc00;
344 		val16 |= tmrval;
345 		outw(val16, TCOv2_TMR(p));
346 		val16 = inw(TCOv2_TMR(p));
347 		spin_unlock(&p->io_lock);
348 
349 		if ((val16 & 0x3ff) != tmrval)
350 			return -EINVAL;
351 	} else if (p->iTCO_version == 1) {
352 		spin_lock(&p->io_lock);
353 		val8 = inb(TCOv1_TMR(p));
354 		val8 &= 0xc0;
355 		val8 |= (tmrval & 0xff);
356 		outb(val8, TCOv1_TMR(p));
357 		val8 = inb(TCOv1_TMR(p));
358 		spin_unlock(&p->io_lock);
359 
360 		if ((val8 & 0x3f) != tmrval)
361 			return -EINVAL;
362 	}
363 
364 	wd_dev->timeout = t;
365 	return 0;
366 }
367 
368 static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
369 {
370 	struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
371 	unsigned int val16;
372 	unsigned char val8;
373 	unsigned int time_left = 0;
374 
375 	/* read the TCO Timer */
376 	if (p->iTCO_version >= 2) {
377 		spin_lock(&p->io_lock);
378 		val16 = inw(TCO_RLD(p));
379 		val16 &= 0x3ff;
380 		spin_unlock(&p->io_lock);
381 
382 		time_left = ticks_to_seconds(p, val16);
383 	} else if (p->iTCO_version == 1) {
384 		spin_lock(&p->io_lock);
385 		val8 = inb(TCO_RLD(p));
386 		val8 &= 0x3f;
387 		if (!(inw(TCO1_STS(p)) & 0x0008))
388 			val8 += (inb(TCOv1_TMR(p)) & 0x3f);
389 		spin_unlock(&p->io_lock);
390 
391 		time_left = ticks_to_seconds(p, val8);
392 	}
393 	return time_left;
394 }
395 
396 /*
397  *	Kernel Interfaces
398  */
399 
400 static const struct watchdog_info ident = {
401 	.options =		WDIOF_SETTIMEOUT |
402 				WDIOF_KEEPALIVEPING |
403 				WDIOF_MAGICCLOSE,
404 	.firmware_version =	0,
405 	.identity =		DRV_NAME,
406 };
407 
408 static const struct watchdog_ops iTCO_wdt_ops = {
409 	.owner =		THIS_MODULE,
410 	.start =		iTCO_wdt_start,
411 	.stop =			iTCO_wdt_stop,
412 	.ping =			iTCO_wdt_ping,
413 	.set_timeout =		iTCO_wdt_set_timeout,
414 	.get_timeleft =		iTCO_wdt_get_timeleft,
415 };
416 
417 /*
418  *	Init & exit routines
419  */
420 
421 static int iTCO_wdt_probe(struct platform_device *pdev)
422 {
423 	struct device *dev = &pdev->dev;
424 	struct itco_wdt_platform_data *pdata = dev_get_platdata(dev);
425 	struct iTCO_wdt_private *p;
426 	unsigned long val32;
427 	int ret;
428 
429 	if (!pdata)
430 		return -ENODEV;
431 
432 	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
433 	if (!p)
434 		return -ENOMEM;
435 
436 	spin_lock_init(&p->io_lock);
437 
438 	p->tco_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_TCO);
439 	if (!p->tco_res)
440 		return -ENODEV;
441 
442 	p->smi_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_SMI);
443 	if (!p->smi_res)
444 		return -ENODEV;
445 
446 	p->iTCO_version = pdata->version;
447 	p->pci_dev = to_pci_dev(dev->parent);
448 
449 	iTCO_wdt_no_reboot_bit_setup(p, pdata);
450 
451 	/*
452 	 * Get the Memory-Mapped GCS or PMC register, we need it for the
453 	 * NO_REBOOT flag (TCO v2 and v3).
454 	 */
455 	if (p->iTCO_version >= 2 && !pdata->update_no_reboot_bit) {
456 		p->gcs_pmc_res = platform_get_resource(pdev,
457 						       IORESOURCE_MEM,
458 						       ICH_RES_MEM_GCS_PMC);
459 		p->gcs_pmc = devm_ioremap_resource(dev, p->gcs_pmc_res);
460 		if (IS_ERR(p->gcs_pmc))
461 			return PTR_ERR(p->gcs_pmc);
462 	}
463 
464 	/* Check chipset's NO_REBOOT bit */
465 	if (p->update_no_reboot_bit(p->no_reboot_priv, false) &&
466 	    iTCO_vendor_check_noreboot_on()) {
467 		pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
468 		return -ENODEV;	/* Cannot reset NO_REBOOT bit */
469 	}
470 
471 	/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
472 	p->update_no_reboot_bit(p->no_reboot_priv, true);
473 
474 	/* The TCO logic uses the TCO_EN bit in the SMI_EN register */
475 	if (!devm_request_region(dev, p->smi_res->start,
476 				 resource_size(p->smi_res),
477 				 pdev->name)) {
478 		pr_err("I/O address 0x%04llx already in use, device disabled\n",
479 		       (u64)SMI_EN(p));
480 		return -EBUSY;
481 	}
482 	if (turn_SMI_watchdog_clear_off >= p->iTCO_version) {
483 		/*
484 		 * Bit 13: TCO_EN -> 0
485 		 * Disables TCO logic generating an SMI#
486 		 */
487 		val32 = inl(SMI_EN(p));
488 		val32 &= 0xffffdfff;	/* Turn off SMI clearing watchdog */
489 		outl(val32, SMI_EN(p));
490 	}
491 
492 	if (!devm_request_region(dev, p->tco_res->start,
493 				 resource_size(p->tco_res),
494 				 pdev->name)) {
495 		pr_err("I/O address 0x%04llx already in use, device disabled\n",
496 		       (u64)TCOBASE(p));
497 		return -EBUSY;
498 	}
499 
500 	pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
501 		pdata->name, pdata->version, (u64)TCOBASE(p));
502 
503 	/* Clear out the (probably old) status */
504 	switch (p->iTCO_version) {
505 	case 5:
506 	case 4:
507 		outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
508 		outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
509 		break;
510 	case 3:
511 		outl(0x20008, TCO1_STS(p));
512 		break;
513 	case 2:
514 	case 1:
515 	default:
516 		outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
517 		outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
518 		outw(0x0004, TCO2_STS(p)); /* Clear BOOT_STS bit */
519 		break;
520 	}
521 
522 	p->wddev.info =	&ident,
523 	p->wddev.ops = &iTCO_wdt_ops,
524 	p->wddev.bootstatus = 0;
525 	p->wddev.timeout = WATCHDOG_TIMEOUT;
526 	watchdog_set_nowayout(&p->wddev, nowayout);
527 	p->wddev.parent = dev;
528 
529 	watchdog_set_drvdata(&p->wddev, p);
530 	platform_set_drvdata(pdev, p);
531 
532 	/* Make sure the watchdog is not running */
533 	iTCO_wdt_stop(&p->wddev);
534 
535 	/* Check that the heartbeat value is within it's range;
536 	   if not reset to the default */
537 	if (iTCO_wdt_set_timeout(&p->wddev, heartbeat)) {
538 		iTCO_wdt_set_timeout(&p->wddev, WATCHDOG_TIMEOUT);
539 		pr_info("timeout value out of range, using %d\n",
540 			WATCHDOG_TIMEOUT);
541 	}
542 
543 	watchdog_stop_on_reboot(&p->wddev);
544 	watchdog_stop_on_unregister(&p->wddev);
545 	ret = devm_watchdog_register_device(dev, &p->wddev);
546 	if (ret != 0) {
547 		pr_err("cannot register watchdog device (err=%d)\n", ret);
548 		return ret;
549 	}
550 
551 	pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n",
552 		heartbeat, nowayout);
553 
554 	return 0;
555 }
556 
557 #ifdef CONFIG_PM_SLEEP
558 /*
559  * Suspend-to-idle requires this, because it stops the ticks and timekeeping, so
560  * the watchdog cannot be pinged while in that state.  In ACPI sleep states the
561  * watchdog is stopped by the platform firmware.
562  */
563 
564 #ifdef CONFIG_ACPI
565 static inline bool need_suspend(void)
566 {
567 	return acpi_target_system_state() == ACPI_STATE_S0;
568 }
569 #else
570 static inline bool need_suspend(void) { return true; }
571 #endif
572 
573 static int iTCO_wdt_suspend_noirq(struct device *dev)
574 {
575 	struct iTCO_wdt_private *p = dev_get_drvdata(dev);
576 	int ret = 0;
577 
578 	p->suspended = false;
579 	if (watchdog_active(&p->wddev) && need_suspend()) {
580 		ret = iTCO_wdt_stop(&p->wddev);
581 		if (!ret)
582 			p->suspended = true;
583 	}
584 	return ret;
585 }
586 
587 static int iTCO_wdt_resume_noirq(struct device *dev)
588 {
589 	struct iTCO_wdt_private *p = dev_get_drvdata(dev);
590 
591 	if (p->suspended)
592 		iTCO_wdt_start(&p->wddev);
593 
594 	return 0;
595 }
596 
597 static const struct dev_pm_ops iTCO_wdt_pm = {
598 	.suspend_noirq = iTCO_wdt_suspend_noirq,
599 	.resume_noirq = iTCO_wdt_resume_noirq,
600 };
601 
602 #define ITCO_WDT_PM_OPS	(&iTCO_wdt_pm)
603 #else
604 #define ITCO_WDT_PM_OPS	NULL
605 #endif /* CONFIG_PM_SLEEP */
606 
607 static struct platform_driver iTCO_wdt_driver = {
608 	.probe          = iTCO_wdt_probe,
609 	.driver         = {
610 		.name   = DRV_NAME,
611 		.pm     = ITCO_WDT_PM_OPS,
612 	},
613 };
614 
615 static int __init iTCO_wdt_init_module(void)
616 {
617 	pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION);
618 
619 	return platform_driver_register(&iTCO_wdt_driver);
620 }
621 
622 static void __exit iTCO_wdt_cleanup_module(void)
623 {
624 	platform_driver_unregister(&iTCO_wdt_driver);
625 	pr_info("Watchdog Module Unloaded\n");
626 }
627 
628 module_init(iTCO_wdt_init_module);
629 module_exit(iTCO_wdt_cleanup_module);
630 
631 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
632 MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
633 MODULE_VERSION(DRV_VERSION);
634 MODULE_LICENSE("GPL");
635 MODULE_ALIAS("platform:" DRV_NAME);
636