1 /* 2 * intel TCO Watchdog Driver 3 * 4 * (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 * 11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor 12 * provide warranty for any of this software. This material is 13 * provided "AS-IS" and at no charge. 14 * 15 * The TCO watchdog is implemented in the following I/O controller hubs: 16 * (See the intel documentation on http://developer.intel.com.) 17 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO) 18 * document number 290687-002, 298242-027: 82801BA (ICH2) 19 * document number 290733-003, 290739-013: 82801CA (ICH3-S) 20 * document number 290716-001, 290718-007: 82801CAM (ICH3-M) 21 * document number 290744-001, 290745-025: 82801DB (ICH4) 22 * document number 252337-001, 252663-008: 82801DBM (ICH4-M) 23 * document number 273599-001, 273645-002: 82801E (C-ICH) 24 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R) 25 * document number 300641-004, 300884-013: 6300ESB 26 * document number 301473-002, 301474-026: 82801F (ICH6) 27 * document number 313082-001, 313075-006: 631xESB, 632xESB 28 * document number 307013-003, 307014-024: 82801G (ICH7) 29 * document number 322896-001, 322897-001: NM10 30 * document number 313056-003, 313057-017: 82801H (ICH8) 31 * document number 316972-004, 316973-012: 82801I (ICH9) 32 * document number 319973-002, 319974-002: 82801J (ICH10) 33 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH) 34 * document number 320066-003, 320257-008: EP80597 (IICH) 35 * document number 324645-001, 324646-001: Cougar Point (CPT) 36 * document number TBD : Patsburg (PBG) 37 * document number TBD : DH89xxCC 38 * document number TBD : Panther Point 39 * document number TBD : Lynx Point 40 */ 41 42 /* 43 * Includes, defines, variables, module parameters, ... 44 */ 45 46 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 47 48 /* Module and version information */ 49 #define DRV_NAME "iTCO_wdt" 50 #define DRV_VERSION "1.07" 51 52 /* Includes */ 53 #include <linux/module.h> /* For module specific items */ 54 #include <linux/moduleparam.h> /* For new moduleparam's */ 55 #include <linux/types.h> /* For standard types (like size_t) */ 56 #include <linux/errno.h> /* For the -ENODEV/... values */ 57 #include <linux/kernel.h> /* For printk/panic/... */ 58 #include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV 59 (WATCHDOG_MINOR) */ 60 #include <linux/watchdog.h> /* For the watchdog specific items */ 61 #include <linux/init.h> /* For __init/__exit/... */ 62 #include <linux/fs.h> /* For file operations */ 63 #include <linux/platform_device.h> /* For platform_driver framework */ 64 #include <linux/pci.h> /* For pci functions */ 65 #include <linux/ioport.h> /* For io-port access */ 66 #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */ 67 #include <linux/uaccess.h> /* For copy_to_user/put_user/... */ 68 #include <linux/io.h> /* For inb/outb/... */ 69 70 #include "iTCO_vendor.h" 71 72 /* TCO related info */ 73 enum iTCO_chipsets { 74 TCO_ICH = 0, /* ICH */ 75 TCO_ICH0, /* ICH0 */ 76 TCO_ICH2, /* ICH2 */ 77 TCO_ICH2M, /* ICH2-M */ 78 TCO_ICH3, /* ICH3-S */ 79 TCO_ICH3M, /* ICH3-M */ 80 TCO_ICH4, /* ICH4 */ 81 TCO_ICH4M, /* ICH4-M */ 82 TCO_CICH, /* C-ICH */ 83 TCO_ICH5, /* ICH5 & ICH5R */ 84 TCO_6300ESB, /* 6300ESB */ 85 TCO_ICH6, /* ICH6 & ICH6R */ 86 TCO_ICH6M, /* ICH6-M */ 87 TCO_ICH6W, /* ICH6W & ICH6RW */ 88 TCO_631XESB, /* 631xESB/632xESB */ 89 TCO_ICH7, /* ICH7 & ICH7R */ 90 TCO_ICH7DH, /* ICH7DH */ 91 TCO_ICH7M, /* ICH7-M & ICH7-U */ 92 TCO_ICH7MDH, /* ICH7-M DH */ 93 TCO_NM10, /* NM10 */ 94 TCO_ICH8, /* ICH8 & ICH8R */ 95 TCO_ICH8DH, /* ICH8DH */ 96 TCO_ICH8DO, /* ICH8DO */ 97 TCO_ICH8M, /* ICH8M */ 98 TCO_ICH8ME, /* ICH8M-E */ 99 TCO_ICH9, /* ICH9 */ 100 TCO_ICH9R, /* ICH9R */ 101 TCO_ICH9DH, /* ICH9DH */ 102 TCO_ICH9DO, /* ICH9DO */ 103 TCO_ICH9M, /* ICH9M */ 104 TCO_ICH9ME, /* ICH9M-E */ 105 TCO_ICH10, /* ICH10 */ 106 TCO_ICH10R, /* ICH10R */ 107 TCO_ICH10D, /* ICH10D */ 108 TCO_ICH10DO, /* ICH10DO */ 109 TCO_PCH, /* PCH Desktop Full Featured */ 110 TCO_PCHM, /* PCH Mobile Full Featured */ 111 TCO_P55, /* P55 */ 112 TCO_PM55, /* PM55 */ 113 TCO_H55, /* H55 */ 114 TCO_QM57, /* QM57 */ 115 TCO_H57, /* H57 */ 116 TCO_HM55, /* HM55 */ 117 TCO_Q57, /* Q57 */ 118 TCO_HM57, /* HM57 */ 119 TCO_PCHMSFF, /* PCH Mobile SFF Full Featured */ 120 TCO_QS57, /* QS57 */ 121 TCO_3400, /* 3400 */ 122 TCO_3420, /* 3420 */ 123 TCO_3450, /* 3450 */ 124 TCO_EP80579, /* EP80579 */ 125 TCO_CPT, /* Cougar Point */ 126 TCO_CPTD, /* Cougar Point Desktop */ 127 TCO_CPTM, /* Cougar Point Mobile */ 128 TCO_PBG, /* Patsburg */ 129 TCO_DH89XXCC, /* DH89xxCC */ 130 TCO_PPT, /* Panther Point */ 131 TCO_LPT, /* Lynx Point */ 132 }; 133 134 static struct { 135 char *name; 136 unsigned int iTCO_version; 137 } iTCO_chipset_info[] __devinitdata = { 138 {"ICH", 1}, 139 {"ICH0", 1}, 140 {"ICH2", 1}, 141 {"ICH2-M", 1}, 142 {"ICH3-S", 1}, 143 {"ICH3-M", 1}, 144 {"ICH4", 1}, 145 {"ICH4-M", 1}, 146 {"C-ICH", 1}, 147 {"ICH5 or ICH5R", 1}, 148 {"6300ESB", 1}, 149 {"ICH6 or ICH6R", 2}, 150 {"ICH6-M", 2}, 151 {"ICH6W or ICH6RW", 2}, 152 {"631xESB/632xESB", 2}, 153 {"ICH7 or ICH7R", 2}, 154 {"ICH7DH", 2}, 155 {"ICH7-M or ICH7-U", 2}, 156 {"ICH7-M DH", 2}, 157 {"NM10", 2}, 158 {"ICH8 or ICH8R", 2}, 159 {"ICH8DH", 2}, 160 {"ICH8DO", 2}, 161 {"ICH8M", 2}, 162 {"ICH8M-E", 2}, 163 {"ICH9", 2}, 164 {"ICH9R", 2}, 165 {"ICH9DH", 2}, 166 {"ICH9DO", 2}, 167 {"ICH9M", 2}, 168 {"ICH9M-E", 2}, 169 {"ICH10", 2}, 170 {"ICH10R", 2}, 171 {"ICH10D", 2}, 172 {"ICH10DO", 2}, 173 {"PCH Desktop Full Featured", 2}, 174 {"PCH Mobile Full Featured", 2}, 175 {"P55", 2}, 176 {"PM55", 2}, 177 {"H55", 2}, 178 {"QM57", 2}, 179 {"H57", 2}, 180 {"HM55", 2}, 181 {"Q57", 2}, 182 {"HM57", 2}, 183 {"PCH Mobile SFF Full Featured", 2}, 184 {"QS57", 2}, 185 {"3400", 2}, 186 {"3420", 2}, 187 {"3450", 2}, 188 {"EP80579", 2}, 189 {"Cougar Point", 2}, 190 {"Cougar Point Desktop", 2}, 191 {"Cougar Point Mobile", 2}, 192 {"Patsburg", 2}, 193 {"DH89xxCC", 2}, 194 {"Panther Point", 2}, 195 {"Lynx Point", 2}, 196 {NULL, 0} 197 }; 198 199 /* 200 * This data only exists for exporting the supported PCI ids 201 * via MODULE_DEVICE_TABLE. We do not actually register a 202 * pci_driver, because the I/O Controller Hub has also other 203 * functions that probably will be registered by other drivers. 204 */ 205 static DEFINE_PCI_DEVICE_TABLE(iTCO_wdt_pci_tbl) = { 206 { PCI_VDEVICE(INTEL, 0x2410), TCO_ICH}, 207 { PCI_VDEVICE(INTEL, 0x2420), TCO_ICH0}, 208 { PCI_VDEVICE(INTEL, 0x2440), TCO_ICH2}, 209 { PCI_VDEVICE(INTEL, 0x244c), TCO_ICH2M}, 210 { PCI_VDEVICE(INTEL, 0x2480), TCO_ICH3}, 211 { PCI_VDEVICE(INTEL, 0x248c), TCO_ICH3M}, 212 { PCI_VDEVICE(INTEL, 0x24c0), TCO_ICH4}, 213 { PCI_VDEVICE(INTEL, 0x24cc), TCO_ICH4M}, 214 { PCI_VDEVICE(INTEL, 0x2450), TCO_CICH}, 215 { PCI_VDEVICE(INTEL, 0x24d0), TCO_ICH5}, 216 { PCI_VDEVICE(INTEL, 0x25a1), TCO_6300ESB}, 217 { PCI_VDEVICE(INTEL, 0x2640), TCO_ICH6}, 218 { PCI_VDEVICE(INTEL, 0x2641), TCO_ICH6M}, 219 { PCI_VDEVICE(INTEL, 0x2642), TCO_ICH6W}, 220 { PCI_VDEVICE(INTEL, 0x2670), TCO_631XESB}, 221 { PCI_VDEVICE(INTEL, 0x2671), TCO_631XESB}, 222 { PCI_VDEVICE(INTEL, 0x2672), TCO_631XESB}, 223 { PCI_VDEVICE(INTEL, 0x2673), TCO_631XESB}, 224 { PCI_VDEVICE(INTEL, 0x2674), TCO_631XESB}, 225 { PCI_VDEVICE(INTEL, 0x2675), TCO_631XESB}, 226 { PCI_VDEVICE(INTEL, 0x2676), TCO_631XESB}, 227 { PCI_VDEVICE(INTEL, 0x2677), TCO_631XESB}, 228 { PCI_VDEVICE(INTEL, 0x2678), TCO_631XESB}, 229 { PCI_VDEVICE(INTEL, 0x2679), TCO_631XESB}, 230 { PCI_VDEVICE(INTEL, 0x267a), TCO_631XESB}, 231 { PCI_VDEVICE(INTEL, 0x267b), TCO_631XESB}, 232 { PCI_VDEVICE(INTEL, 0x267c), TCO_631XESB}, 233 { PCI_VDEVICE(INTEL, 0x267d), TCO_631XESB}, 234 { PCI_VDEVICE(INTEL, 0x267e), TCO_631XESB}, 235 { PCI_VDEVICE(INTEL, 0x267f), TCO_631XESB}, 236 { PCI_VDEVICE(INTEL, 0x27b8), TCO_ICH7}, 237 { PCI_VDEVICE(INTEL, 0x27b0), TCO_ICH7DH}, 238 { PCI_VDEVICE(INTEL, 0x27b9), TCO_ICH7M}, 239 { PCI_VDEVICE(INTEL, 0x27bd), TCO_ICH7MDH}, 240 { PCI_VDEVICE(INTEL, 0x27bc), TCO_NM10}, 241 { PCI_VDEVICE(INTEL, 0x2810), TCO_ICH8}, 242 { PCI_VDEVICE(INTEL, 0x2812), TCO_ICH8DH}, 243 { PCI_VDEVICE(INTEL, 0x2814), TCO_ICH8DO}, 244 { PCI_VDEVICE(INTEL, 0x2815), TCO_ICH8M}, 245 { PCI_VDEVICE(INTEL, 0x2811), TCO_ICH8ME}, 246 { PCI_VDEVICE(INTEL, 0x2918), TCO_ICH9}, 247 { PCI_VDEVICE(INTEL, 0x2916), TCO_ICH9R}, 248 { PCI_VDEVICE(INTEL, 0x2912), TCO_ICH9DH}, 249 { PCI_VDEVICE(INTEL, 0x2914), TCO_ICH9DO}, 250 { PCI_VDEVICE(INTEL, 0x2919), TCO_ICH9M}, 251 { PCI_VDEVICE(INTEL, 0x2917), TCO_ICH9ME}, 252 { PCI_VDEVICE(INTEL, 0x3a18), TCO_ICH10}, 253 { PCI_VDEVICE(INTEL, 0x3a16), TCO_ICH10R}, 254 { PCI_VDEVICE(INTEL, 0x3a1a), TCO_ICH10D}, 255 { PCI_VDEVICE(INTEL, 0x3a14), TCO_ICH10DO}, 256 { PCI_VDEVICE(INTEL, 0x3b00), TCO_PCH}, 257 { PCI_VDEVICE(INTEL, 0x3b01), TCO_PCHM}, 258 { PCI_VDEVICE(INTEL, 0x3b02), TCO_P55}, 259 { PCI_VDEVICE(INTEL, 0x3b03), TCO_PM55}, 260 { PCI_VDEVICE(INTEL, 0x3b06), TCO_H55}, 261 { PCI_VDEVICE(INTEL, 0x3b07), TCO_QM57}, 262 { PCI_VDEVICE(INTEL, 0x3b08), TCO_H57}, 263 { PCI_VDEVICE(INTEL, 0x3b09), TCO_HM55}, 264 { PCI_VDEVICE(INTEL, 0x3b0a), TCO_Q57}, 265 { PCI_VDEVICE(INTEL, 0x3b0b), TCO_HM57}, 266 { PCI_VDEVICE(INTEL, 0x3b0d), TCO_PCHMSFF}, 267 { PCI_VDEVICE(INTEL, 0x3b0f), TCO_QS57}, 268 { PCI_VDEVICE(INTEL, 0x3b12), TCO_3400}, 269 { PCI_VDEVICE(INTEL, 0x3b14), TCO_3420}, 270 { PCI_VDEVICE(INTEL, 0x3b16), TCO_3450}, 271 { PCI_VDEVICE(INTEL, 0x5031), TCO_EP80579}, 272 { PCI_VDEVICE(INTEL, 0x1c41), TCO_CPT}, 273 { PCI_VDEVICE(INTEL, 0x1c42), TCO_CPTD}, 274 { PCI_VDEVICE(INTEL, 0x1c43), TCO_CPTM}, 275 { PCI_VDEVICE(INTEL, 0x1c44), TCO_CPT}, 276 { PCI_VDEVICE(INTEL, 0x1c45), TCO_CPT}, 277 { PCI_VDEVICE(INTEL, 0x1c46), TCO_CPT}, 278 { PCI_VDEVICE(INTEL, 0x1c47), TCO_CPT}, 279 { PCI_VDEVICE(INTEL, 0x1c48), TCO_CPT}, 280 { PCI_VDEVICE(INTEL, 0x1c49), TCO_CPT}, 281 { PCI_VDEVICE(INTEL, 0x1c4a), TCO_CPT}, 282 { PCI_VDEVICE(INTEL, 0x1c4b), TCO_CPT}, 283 { PCI_VDEVICE(INTEL, 0x1c4c), TCO_CPT}, 284 { PCI_VDEVICE(INTEL, 0x1c4d), TCO_CPT}, 285 { PCI_VDEVICE(INTEL, 0x1c4e), TCO_CPT}, 286 { PCI_VDEVICE(INTEL, 0x1c4f), TCO_CPT}, 287 { PCI_VDEVICE(INTEL, 0x1c50), TCO_CPT}, 288 { PCI_VDEVICE(INTEL, 0x1c51), TCO_CPT}, 289 { PCI_VDEVICE(INTEL, 0x1c52), TCO_CPT}, 290 { PCI_VDEVICE(INTEL, 0x1c53), TCO_CPT}, 291 { PCI_VDEVICE(INTEL, 0x1c54), TCO_CPT}, 292 { PCI_VDEVICE(INTEL, 0x1c55), TCO_CPT}, 293 { PCI_VDEVICE(INTEL, 0x1c56), TCO_CPT}, 294 { PCI_VDEVICE(INTEL, 0x1c57), TCO_CPT}, 295 { PCI_VDEVICE(INTEL, 0x1c58), TCO_CPT}, 296 { PCI_VDEVICE(INTEL, 0x1c59), TCO_CPT}, 297 { PCI_VDEVICE(INTEL, 0x1c5a), TCO_CPT}, 298 { PCI_VDEVICE(INTEL, 0x1c5b), TCO_CPT}, 299 { PCI_VDEVICE(INTEL, 0x1c5c), TCO_CPT}, 300 { PCI_VDEVICE(INTEL, 0x1c5d), TCO_CPT}, 301 { PCI_VDEVICE(INTEL, 0x1c5e), TCO_CPT}, 302 { PCI_VDEVICE(INTEL, 0x1c5f), TCO_CPT}, 303 { PCI_VDEVICE(INTEL, 0x1d40), TCO_PBG}, 304 { PCI_VDEVICE(INTEL, 0x1d41), TCO_PBG}, 305 { PCI_VDEVICE(INTEL, 0x2310), TCO_DH89XXCC}, 306 { PCI_VDEVICE(INTEL, 0x1e40), TCO_PPT}, 307 { PCI_VDEVICE(INTEL, 0x1e41), TCO_PPT}, 308 { PCI_VDEVICE(INTEL, 0x1e42), TCO_PPT}, 309 { PCI_VDEVICE(INTEL, 0x1e43), TCO_PPT}, 310 { PCI_VDEVICE(INTEL, 0x1e44), TCO_PPT}, 311 { PCI_VDEVICE(INTEL, 0x1e45), TCO_PPT}, 312 { PCI_VDEVICE(INTEL, 0x1e46), TCO_PPT}, 313 { PCI_VDEVICE(INTEL, 0x1e47), TCO_PPT}, 314 { PCI_VDEVICE(INTEL, 0x1e48), TCO_PPT}, 315 { PCI_VDEVICE(INTEL, 0x1e49), TCO_PPT}, 316 { PCI_VDEVICE(INTEL, 0x1e4a), TCO_PPT}, 317 { PCI_VDEVICE(INTEL, 0x1e4b), TCO_PPT}, 318 { PCI_VDEVICE(INTEL, 0x1e4c), TCO_PPT}, 319 { PCI_VDEVICE(INTEL, 0x1e4d), TCO_PPT}, 320 { PCI_VDEVICE(INTEL, 0x1e4e), TCO_PPT}, 321 { PCI_VDEVICE(INTEL, 0x1e4f), TCO_PPT}, 322 { PCI_VDEVICE(INTEL, 0x1e50), TCO_PPT}, 323 { PCI_VDEVICE(INTEL, 0x1e51), TCO_PPT}, 324 { PCI_VDEVICE(INTEL, 0x1e52), TCO_PPT}, 325 { PCI_VDEVICE(INTEL, 0x1e53), TCO_PPT}, 326 { PCI_VDEVICE(INTEL, 0x1e54), TCO_PPT}, 327 { PCI_VDEVICE(INTEL, 0x1e55), TCO_PPT}, 328 { PCI_VDEVICE(INTEL, 0x1e56), TCO_PPT}, 329 { PCI_VDEVICE(INTEL, 0x1e57), TCO_PPT}, 330 { PCI_VDEVICE(INTEL, 0x1e58), TCO_PPT}, 331 { PCI_VDEVICE(INTEL, 0x1e59), TCO_PPT}, 332 { PCI_VDEVICE(INTEL, 0x1e5a), TCO_PPT}, 333 { PCI_VDEVICE(INTEL, 0x1e5b), TCO_PPT}, 334 { PCI_VDEVICE(INTEL, 0x1e5c), TCO_PPT}, 335 { PCI_VDEVICE(INTEL, 0x1e5d), TCO_PPT}, 336 { PCI_VDEVICE(INTEL, 0x1e5e), TCO_PPT}, 337 { PCI_VDEVICE(INTEL, 0x1e5f), TCO_PPT}, 338 { PCI_VDEVICE(INTEL, 0x8c40), TCO_LPT}, 339 { PCI_VDEVICE(INTEL, 0x8c41), TCO_LPT}, 340 { PCI_VDEVICE(INTEL, 0x8c42), TCO_LPT}, 341 { PCI_VDEVICE(INTEL, 0x8c43), TCO_LPT}, 342 { PCI_VDEVICE(INTEL, 0x8c44), TCO_LPT}, 343 { PCI_VDEVICE(INTEL, 0x8c45), TCO_LPT}, 344 { PCI_VDEVICE(INTEL, 0x8c46), TCO_LPT}, 345 { PCI_VDEVICE(INTEL, 0x8c47), TCO_LPT}, 346 { PCI_VDEVICE(INTEL, 0x8c48), TCO_LPT}, 347 { PCI_VDEVICE(INTEL, 0x8c49), TCO_LPT}, 348 { PCI_VDEVICE(INTEL, 0x8c4a), TCO_LPT}, 349 { PCI_VDEVICE(INTEL, 0x8c4b), TCO_LPT}, 350 { PCI_VDEVICE(INTEL, 0x8c4c), TCO_LPT}, 351 { PCI_VDEVICE(INTEL, 0x8c4d), TCO_LPT}, 352 { PCI_VDEVICE(INTEL, 0x8c4e), TCO_LPT}, 353 { PCI_VDEVICE(INTEL, 0x8c4f), TCO_LPT}, 354 { PCI_VDEVICE(INTEL, 0x8c50), TCO_LPT}, 355 { PCI_VDEVICE(INTEL, 0x8c51), TCO_LPT}, 356 { PCI_VDEVICE(INTEL, 0x8c52), TCO_LPT}, 357 { PCI_VDEVICE(INTEL, 0x8c53), TCO_LPT}, 358 { PCI_VDEVICE(INTEL, 0x8c54), TCO_LPT}, 359 { PCI_VDEVICE(INTEL, 0x8c55), TCO_LPT}, 360 { PCI_VDEVICE(INTEL, 0x8c56), TCO_LPT}, 361 { PCI_VDEVICE(INTEL, 0x8c57), TCO_LPT}, 362 { PCI_VDEVICE(INTEL, 0x8c58), TCO_LPT}, 363 { PCI_VDEVICE(INTEL, 0x8c59), TCO_LPT}, 364 { PCI_VDEVICE(INTEL, 0x8c5a), TCO_LPT}, 365 { PCI_VDEVICE(INTEL, 0x8c5b), TCO_LPT}, 366 { PCI_VDEVICE(INTEL, 0x8c5c), TCO_LPT}, 367 { PCI_VDEVICE(INTEL, 0x8c5d), TCO_LPT}, 368 { PCI_VDEVICE(INTEL, 0x8c5e), TCO_LPT}, 369 { PCI_VDEVICE(INTEL, 0x8c5f), TCO_LPT}, 370 { 0, }, /* End of list */ 371 }; 372 MODULE_DEVICE_TABLE(pci, iTCO_wdt_pci_tbl); 373 374 /* Address definitions for the TCO */ 375 /* TCO base address */ 376 #define TCOBASE (iTCO_wdt_private.ACPIBASE + 0x60) 377 /* SMI Control and Enable Register */ 378 #define SMI_EN (iTCO_wdt_private.ACPIBASE + 0x30) 379 380 #define TCO_RLD (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */ 381 #define TCOv1_TMR (TCOBASE + 0x01) /* TCOv1 Timer Initial Value */ 382 #define TCO_DAT_IN (TCOBASE + 0x02) /* TCO Data In Register */ 383 #define TCO_DAT_OUT (TCOBASE + 0x03) /* TCO Data Out Register */ 384 #define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */ 385 #define TCO2_STS (TCOBASE + 0x06) /* TCO2 Status Register */ 386 #define TCO1_CNT (TCOBASE + 0x08) /* TCO1 Control Register */ 387 #define TCO2_CNT (TCOBASE + 0x0a) /* TCO2 Control Register */ 388 #define TCOv2_TMR (TCOBASE + 0x12) /* TCOv2 Timer Initial Value */ 389 390 /* internal variables */ 391 static unsigned long is_active; 392 static char expect_release; 393 static struct { /* this is private data for the iTCO_wdt device */ 394 /* TCO version/generation */ 395 unsigned int iTCO_version; 396 /* The device's ACPIBASE address (TCOBASE = ACPIBASE+0x60) */ 397 unsigned long ACPIBASE; 398 /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/ 399 unsigned long __iomem *gcs; 400 /* the lock for io operations */ 401 spinlock_t io_lock; 402 /* the PCI-device */ 403 struct pci_dev *pdev; 404 } iTCO_wdt_private; 405 406 /* the watchdog platform device */ 407 static struct platform_device *iTCO_wdt_platform_device; 408 409 /* module parameters */ 410 #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */ 411 static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */ 412 module_param(heartbeat, int, 0); 413 MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. " 414 "5..76 (TCO v1) or 3..614 (TCO v2), default=" 415 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); 416 417 static bool nowayout = WATCHDOG_NOWAYOUT; 418 module_param(nowayout, bool, 0); 419 MODULE_PARM_DESC(nowayout, 420 "Watchdog cannot be stopped once started (default=" 421 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 422 423 static int turn_SMI_watchdog_clear_off = 1; 424 module_param(turn_SMI_watchdog_clear_off, int, 0); 425 MODULE_PARM_DESC(turn_SMI_watchdog_clear_off, 426 "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)"); 427 428 /* 429 * Some TCO specific functions 430 */ 431 432 static inline unsigned int seconds_to_ticks(int seconds) 433 { 434 /* the internal timer is stored as ticks which decrement 435 * every 0.6 seconds */ 436 return (seconds * 10) / 6; 437 } 438 439 static void iTCO_wdt_set_NO_REBOOT_bit(void) 440 { 441 u32 val32; 442 443 /* Set the NO_REBOOT bit: this disables reboots */ 444 if (iTCO_wdt_private.iTCO_version == 2) { 445 val32 = readl(iTCO_wdt_private.gcs); 446 val32 |= 0x00000020; 447 writel(val32, iTCO_wdt_private.gcs); 448 } else if (iTCO_wdt_private.iTCO_version == 1) { 449 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32); 450 val32 |= 0x00000002; 451 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32); 452 } 453 } 454 455 static int iTCO_wdt_unset_NO_REBOOT_bit(void) 456 { 457 int ret = 0; 458 u32 val32; 459 460 /* Unset the NO_REBOOT bit: this enables reboots */ 461 if (iTCO_wdt_private.iTCO_version == 2) { 462 val32 = readl(iTCO_wdt_private.gcs); 463 val32 &= 0xffffffdf; 464 writel(val32, iTCO_wdt_private.gcs); 465 466 val32 = readl(iTCO_wdt_private.gcs); 467 if (val32 & 0x00000020) 468 ret = -EIO; 469 } else if (iTCO_wdt_private.iTCO_version == 1) { 470 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32); 471 val32 &= 0xfffffffd; 472 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32); 473 474 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32); 475 if (val32 & 0x00000002) 476 ret = -EIO; 477 } 478 479 return ret; /* returns: 0 = OK, -EIO = Error */ 480 } 481 482 static int iTCO_wdt_start(void) 483 { 484 unsigned int val; 485 486 spin_lock(&iTCO_wdt_private.io_lock); 487 488 iTCO_vendor_pre_start(iTCO_wdt_private.ACPIBASE, heartbeat); 489 490 /* disable chipset's NO_REBOOT bit */ 491 if (iTCO_wdt_unset_NO_REBOOT_bit()) { 492 spin_unlock(&iTCO_wdt_private.io_lock); 493 pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n"); 494 return -EIO; 495 } 496 497 /* Force the timer to its reload value by writing to the TCO_RLD 498 register */ 499 if (iTCO_wdt_private.iTCO_version == 2) 500 outw(0x01, TCO_RLD); 501 else if (iTCO_wdt_private.iTCO_version == 1) 502 outb(0x01, TCO_RLD); 503 504 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */ 505 val = inw(TCO1_CNT); 506 val &= 0xf7ff; 507 outw(val, TCO1_CNT); 508 val = inw(TCO1_CNT); 509 spin_unlock(&iTCO_wdt_private.io_lock); 510 511 if (val & 0x0800) 512 return -1; 513 return 0; 514 } 515 516 static int iTCO_wdt_stop(void) 517 { 518 unsigned int val; 519 520 spin_lock(&iTCO_wdt_private.io_lock); 521 522 iTCO_vendor_pre_stop(iTCO_wdt_private.ACPIBASE); 523 524 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */ 525 val = inw(TCO1_CNT); 526 val |= 0x0800; 527 outw(val, TCO1_CNT); 528 val = inw(TCO1_CNT); 529 530 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ 531 iTCO_wdt_set_NO_REBOOT_bit(); 532 533 spin_unlock(&iTCO_wdt_private.io_lock); 534 535 if ((val & 0x0800) == 0) 536 return -1; 537 return 0; 538 } 539 540 static int iTCO_wdt_keepalive(void) 541 { 542 spin_lock(&iTCO_wdt_private.io_lock); 543 544 iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat); 545 546 /* Reload the timer by writing to the TCO Timer Counter register */ 547 if (iTCO_wdt_private.iTCO_version == 2) 548 outw(0x01, TCO_RLD); 549 else if (iTCO_wdt_private.iTCO_version == 1) { 550 /* Reset the timeout status bit so that the timer 551 * needs to count down twice again before rebooting */ 552 outw(0x0008, TCO1_STS); /* write 1 to clear bit */ 553 554 outb(0x01, TCO_RLD); 555 } 556 557 spin_unlock(&iTCO_wdt_private.io_lock); 558 return 0; 559 } 560 561 static int iTCO_wdt_set_heartbeat(int t) 562 { 563 unsigned int val16; 564 unsigned char val8; 565 unsigned int tmrval; 566 567 tmrval = seconds_to_ticks(t); 568 569 /* For TCO v1 the timer counts down twice before rebooting */ 570 if (iTCO_wdt_private.iTCO_version == 1) 571 tmrval /= 2; 572 573 /* from the specs: */ 574 /* "Values of 0h-3h are ignored and should not be attempted" */ 575 if (tmrval < 0x04) 576 return -EINVAL; 577 if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) || 578 ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f))) 579 return -EINVAL; 580 581 iTCO_vendor_pre_set_heartbeat(tmrval); 582 583 /* Write new heartbeat to watchdog */ 584 if (iTCO_wdt_private.iTCO_version == 2) { 585 spin_lock(&iTCO_wdt_private.io_lock); 586 val16 = inw(TCOv2_TMR); 587 val16 &= 0xfc00; 588 val16 |= tmrval; 589 outw(val16, TCOv2_TMR); 590 val16 = inw(TCOv2_TMR); 591 spin_unlock(&iTCO_wdt_private.io_lock); 592 593 if ((val16 & 0x3ff) != tmrval) 594 return -EINVAL; 595 } else if (iTCO_wdt_private.iTCO_version == 1) { 596 spin_lock(&iTCO_wdt_private.io_lock); 597 val8 = inb(TCOv1_TMR); 598 val8 &= 0xc0; 599 val8 |= (tmrval & 0xff); 600 outb(val8, TCOv1_TMR); 601 val8 = inb(TCOv1_TMR); 602 spin_unlock(&iTCO_wdt_private.io_lock); 603 604 if ((val8 & 0x3f) != tmrval) 605 return -EINVAL; 606 } 607 608 heartbeat = t; 609 return 0; 610 } 611 612 static int iTCO_wdt_get_timeleft(int *time_left) 613 { 614 unsigned int val16; 615 unsigned char val8; 616 617 /* read the TCO Timer */ 618 if (iTCO_wdt_private.iTCO_version == 2) { 619 spin_lock(&iTCO_wdt_private.io_lock); 620 val16 = inw(TCO_RLD); 621 val16 &= 0x3ff; 622 spin_unlock(&iTCO_wdt_private.io_lock); 623 624 *time_left = (val16 * 6) / 10; 625 } else if (iTCO_wdt_private.iTCO_version == 1) { 626 spin_lock(&iTCO_wdt_private.io_lock); 627 val8 = inb(TCO_RLD); 628 val8 &= 0x3f; 629 if (!(inw(TCO1_STS) & 0x0008)) 630 val8 += (inb(TCOv1_TMR) & 0x3f); 631 spin_unlock(&iTCO_wdt_private.io_lock); 632 633 *time_left = (val8 * 6) / 10; 634 } else 635 return -EINVAL; 636 return 0; 637 } 638 639 /* 640 * /dev/watchdog handling 641 */ 642 643 static int iTCO_wdt_open(struct inode *inode, struct file *file) 644 { 645 /* /dev/watchdog can only be opened once */ 646 if (test_and_set_bit(0, &is_active)) 647 return -EBUSY; 648 649 /* 650 * Reload and activate timer 651 */ 652 iTCO_wdt_start(); 653 return nonseekable_open(inode, file); 654 } 655 656 static int iTCO_wdt_release(struct inode *inode, struct file *file) 657 { 658 /* 659 * Shut off the timer. 660 */ 661 if (expect_release == 42) { 662 iTCO_wdt_stop(); 663 } else { 664 pr_crit("Unexpected close, not stopping watchdog!\n"); 665 iTCO_wdt_keepalive(); 666 } 667 clear_bit(0, &is_active); 668 expect_release = 0; 669 return 0; 670 } 671 672 static ssize_t iTCO_wdt_write(struct file *file, const char __user *data, 673 size_t len, loff_t *ppos) 674 { 675 /* See if we got the magic character 'V' and reload the timer */ 676 if (len) { 677 if (!nowayout) { 678 size_t i; 679 680 /* note: just in case someone wrote the magic 681 character five months ago... */ 682 expect_release = 0; 683 684 /* scan to see whether or not we got the 685 magic character */ 686 for (i = 0; i != len; i++) { 687 char c; 688 if (get_user(c, data + i)) 689 return -EFAULT; 690 if (c == 'V') 691 expect_release = 42; 692 } 693 } 694 695 /* someone wrote to us, we should reload the timer */ 696 iTCO_wdt_keepalive(); 697 } 698 return len; 699 } 700 701 static long iTCO_wdt_ioctl(struct file *file, unsigned int cmd, 702 unsigned long arg) 703 { 704 int new_options, retval = -EINVAL; 705 int new_heartbeat; 706 void __user *argp = (void __user *)arg; 707 int __user *p = argp; 708 static const struct watchdog_info ident = { 709 .options = WDIOF_SETTIMEOUT | 710 WDIOF_KEEPALIVEPING | 711 WDIOF_MAGICCLOSE, 712 .firmware_version = 0, 713 .identity = DRV_NAME, 714 }; 715 716 switch (cmd) { 717 case WDIOC_GETSUPPORT: 718 return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; 719 case WDIOC_GETSTATUS: 720 case WDIOC_GETBOOTSTATUS: 721 return put_user(0, p); 722 723 case WDIOC_SETOPTIONS: 724 { 725 if (get_user(new_options, p)) 726 return -EFAULT; 727 728 if (new_options & WDIOS_DISABLECARD) { 729 iTCO_wdt_stop(); 730 retval = 0; 731 } 732 if (new_options & WDIOS_ENABLECARD) { 733 iTCO_wdt_keepalive(); 734 iTCO_wdt_start(); 735 retval = 0; 736 } 737 return retval; 738 } 739 case WDIOC_KEEPALIVE: 740 iTCO_wdt_keepalive(); 741 return 0; 742 743 case WDIOC_SETTIMEOUT: 744 { 745 if (get_user(new_heartbeat, p)) 746 return -EFAULT; 747 if (iTCO_wdt_set_heartbeat(new_heartbeat)) 748 return -EINVAL; 749 iTCO_wdt_keepalive(); 750 /* Fall */ 751 } 752 case WDIOC_GETTIMEOUT: 753 return put_user(heartbeat, p); 754 case WDIOC_GETTIMELEFT: 755 { 756 int time_left; 757 if (iTCO_wdt_get_timeleft(&time_left)) 758 return -EINVAL; 759 return put_user(time_left, p); 760 } 761 default: 762 return -ENOTTY; 763 } 764 } 765 766 /* 767 * Kernel Interfaces 768 */ 769 770 static const struct file_operations iTCO_wdt_fops = { 771 .owner = THIS_MODULE, 772 .llseek = no_llseek, 773 .write = iTCO_wdt_write, 774 .unlocked_ioctl = iTCO_wdt_ioctl, 775 .open = iTCO_wdt_open, 776 .release = iTCO_wdt_release, 777 }; 778 779 static struct miscdevice iTCO_wdt_miscdev = { 780 .minor = WATCHDOG_MINOR, 781 .name = "watchdog", 782 .fops = &iTCO_wdt_fops, 783 }; 784 785 /* 786 * Init & exit routines 787 */ 788 789 static int __devinit iTCO_wdt_init(struct pci_dev *pdev, 790 const struct pci_device_id *ent, struct platform_device *dev) 791 { 792 int ret; 793 u32 base_address; 794 unsigned long RCBA; 795 unsigned long val32; 796 797 /* 798 * Find the ACPI/PM base I/O address which is the base 799 * for the TCO registers (TCOBASE=ACPIBASE + 0x60) 800 * ACPIBASE is bits [15:7] from 0x40-0x43 801 */ 802 pci_read_config_dword(pdev, 0x40, &base_address); 803 base_address &= 0x0000ff80; 804 if (base_address == 0x00000000) { 805 /* Something's wrong here, ACPIBASE has to be set */ 806 pr_err("failed to get TCOBASE address, device disabled by hardware/BIOS\n"); 807 return -ENODEV; 808 } 809 iTCO_wdt_private.iTCO_version = 810 iTCO_chipset_info[ent->driver_data].iTCO_version; 811 iTCO_wdt_private.ACPIBASE = base_address; 812 iTCO_wdt_private.pdev = pdev; 813 814 /* Get the Memory-Mapped GCS register, we need it for the 815 NO_REBOOT flag (TCO v2). To get access to it you have to 816 read RCBA from PCI Config space 0xf0 and use it as base. 817 GCS = RCBA + ICH6_GCS(0x3410). */ 818 if (iTCO_wdt_private.iTCO_version == 2) { 819 pci_read_config_dword(pdev, 0xf0, &base_address); 820 if ((base_address & 1) == 0) { 821 pr_err("RCBA is disabled by hardware/BIOS, device disabled\n"); 822 ret = -ENODEV; 823 goto out; 824 } 825 RCBA = base_address & 0xffffc000; 826 iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410), 4); 827 } 828 829 /* Check chipset's NO_REBOOT bit */ 830 if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) { 831 pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n"); 832 ret = -ENODEV; /* Cannot reset NO_REBOOT bit */ 833 goto out_unmap; 834 } 835 836 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ 837 iTCO_wdt_set_NO_REBOOT_bit(); 838 839 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */ 840 if (!request_region(SMI_EN, 4, "iTCO_wdt")) { 841 pr_err("I/O address 0x%04lx already in use, device disabled\n", 842 SMI_EN); 843 ret = -EIO; 844 goto out_unmap; 845 } 846 if (turn_SMI_watchdog_clear_off >= iTCO_wdt_private.iTCO_version) { 847 /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */ 848 val32 = inl(SMI_EN); 849 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ 850 outl(val32, SMI_EN); 851 } 852 853 /* The TCO I/O registers reside in a 32-byte range pointed to 854 by the TCOBASE value */ 855 if (!request_region(TCOBASE, 0x20, "iTCO_wdt")) { 856 pr_err("I/O address 0x%04lx already in use, device disabled\n", 857 TCOBASE); 858 ret = -EIO; 859 goto unreg_smi_en; 860 } 861 862 pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n", 863 iTCO_chipset_info[ent->driver_data].name, 864 iTCO_chipset_info[ent->driver_data].iTCO_version, 865 TCOBASE); 866 867 /* Clear out the (probably old) status */ 868 outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */ 869 outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */ 870 outw(0x0004, TCO2_STS); /* Clear BOOT_STS bit */ 871 872 /* Make sure the watchdog is not running */ 873 iTCO_wdt_stop(); 874 875 /* Check that the heartbeat value is within it's range; 876 if not reset to the default */ 877 if (iTCO_wdt_set_heartbeat(heartbeat)) { 878 iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT); 879 pr_info("timeout value out of range, using %d\n", heartbeat); 880 } 881 882 ret = misc_register(&iTCO_wdt_miscdev); 883 if (ret != 0) { 884 pr_err("cannot register miscdev on minor=%d (err=%d)\n", 885 WATCHDOG_MINOR, ret); 886 goto unreg_region; 887 } 888 889 pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n", 890 heartbeat, nowayout); 891 892 return 0; 893 894 unreg_region: 895 release_region(TCOBASE, 0x20); 896 unreg_smi_en: 897 release_region(SMI_EN, 4); 898 out_unmap: 899 if (iTCO_wdt_private.iTCO_version == 2) 900 iounmap(iTCO_wdt_private.gcs); 901 out: 902 iTCO_wdt_private.ACPIBASE = 0; 903 return ret; 904 } 905 906 static void __devexit iTCO_wdt_cleanup(void) 907 { 908 /* Stop the timer before we leave */ 909 if (!nowayout) 910 iTCO_wdt_stop(); 911 912 /* Deregister */ 913 misc_deregister(&iTCO_wdt_miscdev); 914 release_region(TCOBASE, 0x20); 915 release_region(SMI_EN, 4); 916 if (iTCO_wdt_private.iTCO_version == 2) 917 iounmap(iTCO_wdt_private.gcs); 918 pci_dev_put(iTCO_wdt_private.pdev); 919 iTCO_wdt_private.ACPIBASE = 0; 920 } 921 922 static int __devinit iTCO_wdt_probe(struct platform_device *dev) 923 { 924 int ret = -ENODEV; 925 int found = 0; 926 struct pci_dev *pdev = NULL; 927 const struct pci_device_id *ent; 928 929 spin_lock_init(&iTCO_wdt_private.io_lock); 930 931 for_each_pci_dev(pdev) { 932 ent = pci_match_id(iTCO_wdt_pci_tbl, pdev); 933 if (ent) { 934 found++; 935 ret = iTCO_wdt_init(pdev, ent, dev); 936 if (!ret) 937 break; 938 } 939 } 940 941 if (!found) 942 pr_info("No device detected\n"); 943 944 return ret; 945 } 946 947 static int __devexit iTCO_wdt_remove(struct platform_device *dev) 948 { 949 if (iTCO_wdt_private.ACPIBASE) 950 iTCO_wdt_cleanup(); 951 952 return 0; 953 } 954 955 static void iTCO_wdt_shutdown(struct platform_device *dev) 956 { 957 iTCO_wdt_stop(); 958 } 959 960 static struct platform_driver iTCO_wdt_driver = { 961 .probe = iTCO_wdt_probe, 962 .remove = __devexit_p(iTCO_wdt_remove), 963 .shutdown = iTCO_wdt_shutdown, 964 .driver = { 965 .owner = THIS_MODULE, 966 .name = DRV_NAME, 967 }, 968 }; 969 970 static int __init iTCO_wdt_init_module(void) 971 { 972 int err; 973 974 pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION); 975 976 err = platform_driver_register(&iTCO_wdt_driver); 977 if (err) 978 return err; 979 980 iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME, 981 -1, NULL, 0); 982 if (IS_ERR(iTCO_wdt_platform_device)) { 983 err = PTR_ERR(iTCO_wdt_platform_device); 984 goto unreg_platform_driver; 985 } 986 987 return 0; 988 989 unreg_platform_driver: 990 platform_driver_unregister(&iTCO_wdt_driver); 991 return err; 992 } 993 994 static void __exit iTCO_wdt_cleanup_module(void) 995 { 996 platform_device_unregister(iTCO_wdt_platform_device); 997 platform_driver_unregister(&iTCO_wdt_driver); 998 pr_info("Watchdog Module Unloaded\n"); 999 } 1000 1001 module_init(iTCO_wdt_init_module); 1002 module_exit(iTCO_wdt_cleanup_module); 1003 1004 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>"); 1005 MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver"); 1006 MODULE_VERSION(DRV_VERSION); 1007 MODULE_LICENSE("GPL"); 1008 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); 1009